34 lines
994 B
C
34 lines
994 B
C
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/*
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* Copyright 2012 GE Intelligent Platforms, Inc.
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#ifndef FSL_DDR_MEMCTL_H
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#define FSL_DDR_MEMCTL_H
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/*
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* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
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*/
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#define SDRAM_CFG_MEM_EN 0x80000000
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#define SDRAM_CFG_SREN 0x40000000
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#define SDRAM_CFG_ECC_EN 0x20000000
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#define SDRAM_CFG_RD_EN 0x10000000
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#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
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#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
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#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
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#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
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#define SDRAM_CFG_DYN_PWR 0x00200000
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#define SDRAM_CFG_32_BE 0x00080000
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#define SDRAM_CFG_8_BE 0x00040000
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#define SDRAM_CFG_NCAP 0x00020000
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#define SDRAM_CFG_2T_EN 0x00008000
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#define SDRAM_CFG_BI 0x00000001
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extern phys_size_t fixed_sdram(void);
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#endif
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