ARM: Add atomic.h from u-boot v2016.03
atomic-long.h: * Replace __UBOOT__ with __BAREBOX__ Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Alexander Stein
Sascha Hauer
parent
caed8a92bc
commit
013f33ac3a
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/*
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* linux/include/asm-arm/atomic.h
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*
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* Copyright (c) 1996 Russell King.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Changelog:
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* 27-06-1996 RMK Created
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* 13-04-1997 RMK Made functions atomic!
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* 07-12-1997 RMK Upgraded for v2.1.
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* 26-08-1998 PJB Added #ifdef __KERNEL__
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*/
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#ifndef __ASM_ARM_ATOMIC_H
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#define __ASM_ARM_ATOMIC_H
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#ifdef CONFIG_SMP
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#error SMP not supported
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#endif
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typedef struct { volatile int counter; } atomic_t;
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#define ATOMIC_INIT(i) { (i) }
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#ifdef __KERNEL__
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#include <asm/proc-armv/system.h>
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#define atomic_read(v) ((v)->counter)
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#define atomic_set(v,i) (((v)->counter) = (i))
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static inline void atomic_add(int i, volatile atomic_t *v)
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{
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unsigned long flags = 0;
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local_irq_save(flags);
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v->counter += i;
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local_irq_restore(flags);
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}
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static inline void atomic_sub(int i, volatile atomic_t *v)
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{
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unsigned long flags = 0;
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local_irq_save(flags);
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v->counter -= i;
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local_irq_restore(flags);
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}
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static inline void atomic_inc(volatile atomic_t *v)
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{
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unsigned long flags = 0;
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local_irq_save(flags);
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v->counter += 1;
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local_irq_restore(flags);
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}
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static inline void atomic_dec(volatile atomic_t *v)
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{
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unsigned long flags = 0;
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local_irq_save(flags);
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v->counter -= 1;
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local_irq_restore(flags);
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}
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static inline int atomic_dec_and_test(volatile atomic_t *v)
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{
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unsigned long flags = 0;
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int val;
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local_irq_save(flags);
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val = v->counter;
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v->counter = val -= 1;
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local_irq_restore(flags);
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return val == 0;
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}
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static inline int atomic_add_negative(int i, volatile atomic_t *v)
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{
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unsigned long flags = 0;
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int val;
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local_irq_save(flags);
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val = v->counter;
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v->counter = val += i;
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local_irq_restore(flags);
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return val < 0;
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}
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static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
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{
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unsigned long flags = 0;
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local_irq_save(flags);
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*addr &= ~mask;
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local_irq_restore(flags);
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}
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/* Atomic operations are already serializing on ARM */
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#define smp_mb__before_atomic_dec() barrier()
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#define smp_mb__after_atomic_dec() barrier()
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#define smp_mb__before_atomic_inc() barrier()
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#define smp_mb__after_atomic_inc() barrier()
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#endif
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#endif
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@ -0,0 +1,224 @@
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/*
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* linux/include/asm-arm/proc-armv/system.h
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*
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* Copyright (C) 1996 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_PROC_SYSTEM_H
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#define __ASM_PROC_SYSTEM_H
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/*
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* Save the current interrupt enable state & disable IRQs
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*/
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#ifdef CONFIG_ARM64
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/*
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* Save the current interrupt enable state
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* and disable IRQs/FIQs
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*/
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#define local_irq_save(flags) \
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({ \
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asm volatile( \
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"mrs %0, daif\n" \
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"msr daifset, #3" \
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: "=r" (flags) \
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: \
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: "memory"); \
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})
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/*
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* restore saved IRQ & FIQ state
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*/
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#define local_irq_restore(flags) \
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({ \
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asm volatile( \
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"msr daif, %0" \
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: \
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: "r" (flags) \
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: "memory"); \
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})
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/*
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* Enable IRQs/FIQs
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*/
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#define local_irq_enable() \
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({ \
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asm volatile( \
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"msr daifclr, #3" \
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: \
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: \
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: "memory"); \
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})
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/*
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* Disable IRQs/FIQs
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*/
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#define local_irq_disable() \
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({ \
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asm volatile( \
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"msr daifset, #3" \
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: \
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: \
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: "memory"); \
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})
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#else /* CONFIG_ARM64 */
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#define local_irq_save(x) \
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({ \
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unsigned long temp; \
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__asm__ __volatile__( \
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"mrs %0, cpsr @ local_irq_save\n" \
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" orr %1, %0, #128\n" \
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" msr cpsr_c, %1" \
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: "=r" (x), "=r" (temp) \
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: \
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: "memory"); \
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})
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/*
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* Enable IRQs
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*/
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#define local_irq_enable() \
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({ \
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unsigned long temp; \
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__asm__ __volatile__( \
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"mrs %0, cpsr @ local_irq_enable\n" \
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" bic %0, %0, #128\n" \
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" msr cpsr_c, %0" \
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: "=r" (temp) \
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: \
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: "memory"); \
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})
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/*
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* Disable IRQs
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*/
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#define local_irq_disable() \
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({ \
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unsigned long temp; \
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__asm__ __volatile__( \
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"mrs %0, cpsr @ local_irq_disable\n" \
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" orr %0, %0, #128\n" \
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" msr cpsr_c, %0" \
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: "=r" (temp) \
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: \
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: "memory"); \
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})
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/*
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* Enable FIQs
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*/
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#define __stf() \
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({ \
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unsigned long temp; \
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__asm__ __volatile__( \
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"mrs %0, cpsr @ stf\n" \
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" bic %0, %0, #64\n" \
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" msr cpsr_c, %0" \
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: "=r" (temp) \
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: \
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: "memory"); \
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})
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/*
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* Disable FIQs
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*/
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#define __clf() \
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({ \
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unsigned long temp; \
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__asm__ __volatile__( \
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"mrs %0, cpsr @ clf\n" \
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" orr %0, %0, #64\n" \
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" msr cpsr_c, %0" \
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: "=r" (temp) \
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: \
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: "memory"); \
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})
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/*
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* Save the current interrupt enable state.
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*/
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#define local_save_flags(x) \
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({ \
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__asm__ __volatile__( \
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"mrs %0, cpsr @ local_save_flags\n" \
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: "=r" (x) \
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: \
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: "memory"); \
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})
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/*
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* restore saved IRQ & FIQ state
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*/
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#define local_irq_restore(x) \
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__asm__ __volatile__( \
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"msr cpsr_c, %0 @ local_irq_restore\n" \
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: \
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: "r" (x) \
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: "memory")
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#endif /* CONFIG_ARM64 */
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#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) || \
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defined(CONFIG_ARM64)
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/*
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* On the StrongARM, "swp" is terminally broken since it bypasses the
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* cache totally. This means that the cache becomes inconsistent, and,
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* since we use normal loads/stores as well, this is really bad.
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* Typically, this causes oopsen in filp_close, but could have other,
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* more disasterous effects. There are two work-arounds:
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* 1. Disable interrupts and emulate the atomic swap
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* 2. Clean the cache, perform atomic swap, flush the cache
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*
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* We choose (1) since its the "easiest" to achieve here and is not
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* dependent on the processor type.
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*/
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#define swp_is_buggy
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#endif
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static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
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{
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extern void __bad_xchg(volatile void *, int);
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unsigned long ret;
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#ifdef swp_is_buggy
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unsigned long flags;
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#endif
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switch (size) {
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#ifdef swp_is_buggy
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case 1:
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local_irq_save(flags);
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ret = *(volatile unsigned char *)ptr;
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*(volatile unsigned char *)ptr = x;
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local_irq_restore(flags);
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break;
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case 4:
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local_irq_save(flags);
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ret = *(volatile unsigned long *)ptr;
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*(volatile unsigned long *)ptr = x;
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local_irq_restore(flags);
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break;
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#else
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case 1: __asm__ __volatile__ ("swpb %0, %1, [%2]"
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: "=&r" (ret)
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: "r" (x), "r" (ptr)
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: "memory");
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break;
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case 4: __asm__ __volatile__ ("swp %0, %1, [%2]"
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: "=&r" (ret)
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: "r" (x), "r" (ptr)
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: "memory");
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break;
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#endif
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default: __bad_xchg(ptr, size), ret = 0;
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}
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return ret;
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}
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#endif
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@ -0,0 +1,260 @@
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#ifndef _ASM_GENERIC_ATOMIC_LONG_H
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#define _ASM_GENERIC_ATOMIC_LONG_H
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/*
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* Copyright (C) 2005 Silicon Graphics, Inc.
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* Christoph Lameter
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*
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* Allows to provide arch independent atomic definitions without the need to
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* edit all arch specific atomic.h files.
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*/
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#include <asm/types.h>
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/*
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* Suppport for atomic_long_t
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*
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* Casts for parameters are avoided for existing atomic functions in order to
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* avoid issues with cast-as-lval under gcc 4.x and other limitations that the
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* macros of a platform may have.
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*/
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#if BITS_PER_LONG == 64
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typedef atomic64_t atomic_long_t;
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#define ATOMIC_LONG_INIT(i) ATOMIC64_INIT(i)
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static inline long atomic_long_read(atomic_long_t *l)
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{
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atomic64_t *v = (atomic64_t *)l;
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return (long)atomic64_read(v);
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}
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static inline void atomic_long_set(atomic_long_t *l, long i)
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{
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atomic64_t *v = (atomic64_t *)l;
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atomic64_set(v, i);
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}
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static inline void atomic_long_inc(atomic_long_t *l)
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{
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atomic64_t *v = (atomic64_t *)l;
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atomic64_inc(v);
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}
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static inline void atomic_long_dec(atomic_long_t *l)
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{
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atomic64_t *v = (atomic64_t *)l;
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atomic64_dec(v);
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}
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static inline void atomic_long_add(long i, atomic_long_t *l)
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{
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atomic64_t *v = (atomic64_t *)l;
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atomic64_add(i, v);
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}
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static inline void atomic_long_sub(long i, atomic_long_t *l)
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{
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atomic64_t *v = (atomic64_t *)l;
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atomic64_sub(i, v);
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}
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static inline int atomic_long_sub_and_test(long i, atomic_long_t *l)
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{
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atomic64_t *v = (atomic64_t *)l;
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return atomic64_sub_and_test(i, v);
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}
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static inline int atomic_long_dec_and_test(atomic_long_t *l)
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{
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atomic64_t *v = (atomic64_t *)l;
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return atomic64_dec_and_test(v);
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}
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static inline int atomic_long_inc_and_test(atomic_long_t *l)
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{
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atomic64_t *v = (atomic64_t *)l;
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return atomic64_inc_and_test(v);
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}
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static inline int atomic_long_add_negative(long i, atomic_long_t *l)
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{
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atomic64_t *v = (atomic64_t *)l;
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return atomic64_add_negative(i, v);
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}
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static inline long atomic_long_add_return(long i, atomic_long_t *l)
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{
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atomic64_t *v = (atomic64_t *)l;
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return (long)atomic64_add_return(i, v);
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}
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static inline long atomic_long_sub_return(long i, atomic_long_t *l)
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{
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atomic64_t *v = (atomic64_t *)l;
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return (long)atomic64_sub_return(i, v);
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}
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static inline long atomic_long_inc_return(atomic_long_t *l)
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{
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atomic64_t *v = (atomic64_t *)l;
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return (long)atomic64_inc_return(v);
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}
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static inline long atomic_long_dec_return(atomic_long_t *l)
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{
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atomic64_t *v = (atomic64_t *)l;
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return (long)atomic64_dec_return(v);
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}
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static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u)
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{
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atomic64_t *v = (atomic64_t *)l;
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return (long)atomic64_add_unless(v, a, u);
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}
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#define atomic_long_inc_not_zero(l) atomic64_inc_not_zero((atomic64_t *)(l))
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#define atomic_long_cmpxchg(l, old, new) \
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(atomic64_cmpxchg((atomic64_t *)(l), (old), (new)))
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#define atomic_long_xchg(v, new) \
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(atomic64_xchg((atomic64_t *)(v), (new)))
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#else /* BITS_PER_LONG == 64 */
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typedef atomic_t atomic_long_t;
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#define ATOMIC_LONG_INIT(i) ATOMIC_INIT(i)
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static inline long atomic_long_read(atomic_long_t *l)
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{
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atomic_t *v = (atomic_t *)l;
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return (long)atomic_read(v);
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}
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static inline void atomic_long_set(atomic_long_t *l, long i)
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{
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atomic_t *v = (atomic_t *)l;
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atomic_set(v, i);
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}
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static inline void atomic_long_inc(atomic_long_t *l)
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{
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atomic_t *v = (atomic_t *)l;
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atomic_inc(v);
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}
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static inline void atomic_long_dec(atomic_long_t *l)
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{
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atomic_t *v = (atomic_t *)l;
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atomic_dec(v);
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}
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static inline void atomic_long_add(long i, atomic_long_t *l)
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{
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atomic_t *v = (atomic_t *)l;
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atomic_add(i, v);
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}
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static inline void atomic_long_sub(long i, atomic_long_t *l)
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{
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atomic_t *v = (atomic_t *)l;
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atomic_sub(i, v);
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}
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#ifndef __BAREBOX__
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static inline int atomic_long_sub_and_test(long i, atomic_long_t *l)
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{
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atomic_t *v = (atomic_t *)l;
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return atomic_sub_and_test(i, v);
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}
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|
||||
static inline int atomic_long_dec_and_test(atomic_long_t *l)
|
||||
{
|
||||
atomic_t *v = (atomic_t *)l;
|
||||
|
||||
return atomic_dec_and_test(v);
|
||||
}
|
||||
|
||||
static inline int atomic_long_inc_and_test(atomic_long_t *l)
|
||||
{
|
||||
atomic_t *v = (atomic_t *)l;
|
||||
|
||||
return atomic_inc_and_test(v);
|
||||
}
|
||||
|
||||
static inline int atomic_long_add_negative(long i, atomic_long_t *l)
|
||||
{
|
||||
atomic_t *v = (atomic_t *)l;
|
||||
|
||||
return atomic_add_negative(i, v);
|
||||
}
|
||||
|
||||
static inline long atomic_long_add_return(long i, atomic_long_t *l)
|
||||
{
|
||||
atomic_t *v = (atomic_t *)l;
|
||||
|
||||
return (long)atomic_add_return(i, v);
|
||||
}
|
||||
|
||||
static inline long atomic_long_sub_return(long i, atomic_long_t *l)
|
||||
{
|
||||
atomic_t *v = (atomic_t *)l;
|
||||
|
||||
return (long)atomic_sub_return(i, v);
|
||||
}
|
||||
|
||||
static inline long atomic_long_inc_return(atomic_long_t *l)
|
||||
{
|
||||
atomic_t *v = (atomic_t *)l;
|
||||
|
||||
return (long)atomic_inc_return(v);
|
||||
}
|
||||
|
||||
static inline long atomic_long_dec_return(atomic_long_t *l)
|
||||
{
|
||||
atomic_t *v = (atomic_t *)l;
|
||||
|
||||
return (long)atomic_dec_return(v);
|
||||
}
|
||||
|
||||
static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u)
|
||||
{
|
||||
atomic_t *v = (atomic_t *)l;
|
||||
|
||||
return (long)atomic_add_unless(v, a, u);
|
||||
}
|
||||
|
||||
#define atomic_long_inc_not_zero(l) atomic_inc_not_zero((atomic_t *)(l))
|
||||
|
||||
#define atomic_long_cmpxchg(l, old, new) \
|
||||
(atomic_cmpxchg((atomic_t *)(l), (old), (new)))
|
||||
#define atomic_long_xchg(v, new) \
|
||||
(atomic_xchg((atomic_t *)(v), (new)))
|
||||
#endif /* __BAREBOX__ */
|
||||
|
||||
#endif /* BITS_PER_LONG == 64 */
|
||||
|
||||
#endif /* _ASM_GENERIC_ATOMIC_LONG_H */
|
||||
Loading…
Reference in New Issue