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Merge branch 'for-next/net' 

Conflicts:
	arch/arm/boards/animeo_ip/init.c
This commit is contained in:
Sascha Hauer 2013-10-07 08:00:36 +02:00
parent 71fbdfbb13 7ccaaf71fe
commit 01f37a992f
10 changed files with 294 additions and 94 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

73
arch/arm/boards/animeo_ip/init.c
View File

@ -19,6 +19,7 @@
#include <nand.h>
#include <sizes.h>
#include <linux/mtd/nand.h>
#include <linux/clk.h>
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
#include <gpio.h>
@ -26,6 +27,7 @@
#include <mach/io.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
#include <local_mac_address.h>
static bool animeo_ip_is_buco;
static bool animeo_ip_is_io;
@ -226,12 +228,79 @@ static void animeo_ip_power_control(void)
animeo_export_gpio_out(AT91_PIN_PC4, "power_save");
}
static void animeo_ip_phy_reset(void)
{
unsigned long rstc;
int i;
struct clk *clk = clk_get(NULL, "macb_clk");
clk_enable(clk);
for (i = AT91_PIN_PA12; i <= AT91_PIN_PA29; i++)
at91_set_gpio_input(i, 0);
rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(AT91_RSTC_ERSTL & (0x0d << 8)) |
AT91_RSTC_URSTEN);
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
/* Wait for end hardware reset */
while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL))
;
/* Restore NRST value */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | (rstc) | AT91_RSTC_URSTEN);
}
#define MACB_SA1B 0x0098
#define MACB_SA1T 0x009c
static int animeo_ip_get_macb_ethaddr(u8 *addr)
{
u32 top, bottom;
void __iomem *base = IOMEM(AT91SAM9260_BASE_EMAC);
bottom = readl(base + MACB_SA1B);
top = readl(base + MACB_SA1T);
addr[0] = bottom & 0xff;
addr[1] = (bottom >> 8) & 0xff;
addr[2] = (bottom >> 16) & 0xff;
addr[3] = (bottom >> 24) & 0xff;
addr[4] = top & 0xff;
addr[5] = (top >> 8) & 0xff;
/* valid and not private */
if (is_valid_ether_addr(addr) && !(addr[0] & 0x02))
return 0;
return -EINVAL;
}
static void animeo_ip_add_device_eth(void)
{
u8 enetaddr[6];
if (!animeo_ip_get_macb_ethaddr(enetaddr))
eth_register_ethaddr(0, enetaddr);
else
local_mac_address_register(0, "smf");
/* for usb asix */
local_mac_address_register(1, "smf");
animeo_ip_phy_reset();
at91_add_device_eth(0, &macb_pdata);
}
static int animeo_ip_devices_init(void)
{
animeo_ip_detect_version();
animeo_ip_power_control();
animeo_ip_add_device_nand();
at91_add_device_eth(0, &macb_pdata);
animeo_ip_add_device_usb();
animeo_ip_add_device_mci();
animeo_ip_add_device_buttons();
@ -251,6 +320,8 @@ static int animeo_ip_devices_init(void)
devfs_add_partition("nand0", SZ_256K + SZ_32K, SZ_32K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
animeo_ip_add_device_eth();
return 0;
}

7
arch/arm/boards/versatile/versatilepb.c
View File

@ -28,6 +28,7 @@
#include <environment.h>
#include <partition.h>
#include <sizes.h>
#include <net/smc91111.h>
static int vpb_console_init(void)
{
@ -47,6 +48,10 @@ static int vpb_mem_init(void)
}
mem_initcall(vpb_mem_init);
static struct smc91c111_pdata net_pdata = {
.qemu_fixup = 1,
};
static int vpb_devices_init(void)
{
add_cfi_flash_device(DEVICE_ID_DYNAMIC, VERSATILE_FLASH_BASE, VERSATILE_FLASH_SIZE, 0);
@ -55,7 +60,7 @@ static int vpb_devices_init(void)
devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, VERSATILE_ETH_BASE,
64 * 1024, IORESOURCE_MEM, NULL);
64 * 1024, IORESOURCE_MEM, &net_pdata);
armlinux_set_architecture(MACH_TYPE_VERSATILE_PB);
armlinux_set_bootparams((void *)(0x00000100));

6
drivers/net/Kconfig
View File

@ -130,16 +130,10 @@ config DRIVER_NET_KS8851_MLL
config DRIVER_NET_DESIGNWARE
bool "Designware Universal MAC ethernet driver"
select PHYLIB
depends on HAS_DESIGNWARE_ETH
help
This option enables support for the Synopsys
Designware Core Univesal MAC 10M/100M/1G ethernet IP.
config DRIVER_NET_DESIGNWARE_ALTDESCRIPTOR
bool
depends on DRIVER_NET_DESIGNWARE
default n
config DRIVER_NET_GIANFAR
bool "Gianfar Ethernet"
depends on ARCH_MPC85XX

133
drivers/net/designware.c
View File

@ -29,12 +29,12 @@
#include <init.h>
#include <io.h>
#include <net.h>
#include <of_net.h>
#include <asm/mmu.h>
#include <net/designware.h>
#include <linux/phy.h>
#include "designware.h"
struct dw_eth_dev {
struct eth_device netdev;
struct mii_bus miibus;
@ -54,6 +54,15 @@ struct dw_eth_dev {
struct eth_dma_regs *dma_regs_p;
int phy_addr;
phy_interface_t interface;
int enh_desc;
};
struct dw_eth_drvdata {
bool enh_desc;
};
static struct dw_eth_drvdata dwmac_370a_drvdata = {
.enh_desc = 1,
};
/* Speed specific definitions */
@ -73,7 +82,7 @@ static int dwc_ether_mii_read(struct mii_bus *dev, int addr, int reg)
u64 start;
u32 miiaddr;
miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
((reg << MIIREGSHIFT) & MII_REGMSK);
writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
@ -96,7 +105,7 @@ static int dwc_ether_mii_write(struct mii_bus *dev, int addr, int reg, u16 val)
u32 miiaddr;
writel(val, &mac_p->miidata);
miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
@ -149,19 +158,19 @@ static void tx_descs_init(struct eth_device *dev)
desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
desc_p->dmamac_next = &desc_table_p[idx + 1];
#if defined(CONFIG_DRIVER_NET_DESIGNWARE_ALTDESCRIPTOR)
desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
DESC_TXSTS_TXCHECKINSCTRL | \
DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
if (priv->enh_desc) {
desc_p->txrx_status &= ~(DESC_ENH_TXSTS_TXINT | DESC_ENH_TXSTS_TXLAST |
DESC_ENH_TXSTS_TXFIRST | DESC_ENH_TXSTS_TXCRCDIS |
DESC_ENH_TXSTS_TXCHECKINSCTRL |
DESC_ENH_TXSTS_TXRINGEND | DESC_ENH_TXSTS_TXPADDIS);
desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
desc_p->dmamac_cntl = 0;
desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
#else
desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
desc_p->txrx_status = 0;
#endif
desc_p->txrx_status |= DESC_ENH_TXSTS_TXCHAIN;
desc_p->dmamac_cntl = 0;
desc_p->txrx_status &= ~(DESC_ENH_TXSTS_MSK | DESC_ENH_TXSTS_OWNBYDMA);
} else {
desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
desc_p->txrx_status = 0;
}
}
/* Correcting the last pointer of the chain */
@ -184,9 +193,11 @@ static void rx_descs_init(struct eth_device *dev)
desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
desc_p->dmamac_next = &desc_table_p[idx + 1];
desc_p->dmamac_cntl =
(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
DESC_RXCTRL_RXCHAIN;
desc_p->dmamac_cntl = MAC_MAX_FRAME_SZ;
if (priv->enh_desc)
desc_p->dmamac_cntl |= DESC_ENH_RXCTRL_RXCHAIN;
else
desc_p->dmamac_cntl |= DESC_RXCTRL_RXCHAIN;
dma_inv_range((unsigned long)desc_p->dmamac_addr,
(unsigned long)desc_p->dmamac_addr + CONFIG_ETH_BUFSIZE);
@ -282,11 +293,12 @@ static int dwc_ether_send(struct eth_device *dev, void *packet, int length)
{
struct dw_eth_dev *priv = dev->priv;
struct eth_dma_regs *dma_p = priv->dma_regs_p;
u32 desc_num = priv->tx_currdescnum;
u32 owndma, desc_num = priv->tx_currdescnum;
struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
owndma = priv->enh_desc ? DESC_ENH_TXSTS_OWNBYDMA : DESC_TXSTS_OWNBYDMA;
/* Check if the descriptor is owned by CPU */
if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
if (desc_p->txrx_status & owndma) {
dev_err(&dev->dev, "CPU not owner of tx frame\n");
return -1;
}
@ -295,20 +307,20 @@ static int dwc_ether_send(struct eth_device *dev, void *packet, int length)
dma_flush_range((unsigned long)desc_p->dmamac_addr,
(unsigned long)desc_p->dmamac_addr + length);
#if defined(CONFIG_DRIVER_NET_DESIGNWARE_ALTDESCRIPTOR)
desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
DESC_TXCTRL_SIZE1MASK;
if (priv->enh_desc) {
desc_p->txrx_status |= DESC_ENH_TXSTS_TXFIRST | DESC_ENH_TXSTS_TXLAST;
desc_p->dmamac_cntl |= (length << DESC_ENH_TXCTRL_SIZE1SHFT) &
DESC_ENH_TXCTRL_SIZE1MASK;
desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
#else
desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
DESC_TXCTRL_TXFIRST;
desc_p->txrx_status &= ~(DESC_ENH_TXSTS_MSK);
desc_p->txrx_status |= DESC_ENH_TXSTS_OWNBYDMA;
} else {
desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) &
DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
DESC_TXCTRL_TXFIRST;
desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
#endif
desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
}
/* Test the wrap-around condition. */
if (++desc_num >= CONFIG_TX_DESCR_NUM)
@ -334,17 +346,18 @@ static int dwc_ether_rx(struct eth_device *dev)
if (status & DESC_RXSTS_OWNBYDMA)
return 0;
length = (status & DESC_RXSTS_FRMLENMSK) >> \
length = (status & DESC_RXSTS_FRMLENMSK) >>
DESC_RXSTS_FRMLENSHFT;
net_receive(desc_p->dmamac_addr, length);
/*
* Make the current descriptor valid again and go to
* the next one
*/
dma_inv_range((unsigned long)desc_p->dmamac_addr,
(unsigned long)desc_p->dmamac_addr + length);
net_receive(desc_p->dmamac_addr, length);
desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
/* Test the wrap-around condition. */
@ -376,7 +389,7 @@ static int dwc_ether_set_ethaddr(struct eth_device *dev, u8 adr[6])
struct eth_mac_regs *mac_p = priv->mac_regs_p;
u32 macid_lo, macid_hi;
macid_lo = adr[0] + (adr[1] << 8) + \
macid_lo = adr[0] + (adr[1] << 8) +
(adr[2] << 16) + (adr[3] << 24);
macid_hi = adr[4] + (adr[5] << 8);
writel(macid_hi, &mac_p->macaddr0hi);
@ -394,6 +407,14 @@ static void dwc_version(struct device_d *dev, u32 hwid)
uid, synid);
}
static int dwc_probe_dt(struct device_d *dev, struct dw_eth_dev *priv)
{
priv->phy_addr = -1;
priv->interface = of_get_phy_mode(dev->device_node);
return 0;
}
static int dwc_ether_probe(struct device_d *dev)
{
struct dw_eth_dev *priv;
@ -401,14 +422,27 @@ static int dwc_ether_probe(struct device_d *dev)
struct mii_bus *miibus;
void __iomem *base;
struct dwc_ether_platform_data *pdata = dev->platform_data;
if (!pdata) {
printf("dwc_ether: no platform_data\n");
return -ENODEV;
}
int ret;
struct dw_eth_drvdata *drvdata;
priv = xzalloc(sizeof(struct dw_eth_dev));
ret = dev_get_drvdata(dev, (unsigned long *)&drvdata);
if (ret)
return ret;
priv->enh_desc = drvdata->enh_desc;
if (pdata) {
priv->phy_addr = pdata->phy_addr;
priv->interface = pdata->interface;
priv->fix_mac_speed = pdata->fix_mac_speed;
} else {
ret = dwc_probe_dt(dev, priv);
if (ret)
return ret;
}
base = dev_request_mem_region(dev, 0);
priv->mac_regs_p = base;
dwc_version(dev, readl(&priv->mac_regs_p->version));
@ -417,9 +451,8 @@ static int dwc_ether_probe(struct device_d *dev)
CONFIG_TX_DESCR_NUM * sizeof(struct dmamacdescr));
priv->rx_mac_descrtable = dma_alloc_coherent(
CONFIG_RX_DESCR_NUM * sizeof(struct dmamacdescr));
priv->txbuffs = malloc(TX_TOTAL_BUFSIZE);
priv->rxbuffs = malloc(RX_TOTAL_BUFSIZE);
priv->fix_mac_speed = pdata->fix_mac_speed;
priv->txbuffs = dma_alloc(TX_TOTAL_BUFSIZE);
priv->rxbuffs = dma_alloc(RX_TOTAL_BUFSIZE);
edev = &priv->netdev;
miibus = &priv->miibus;
@ -434,8 +467,6 @@ static int dwc_ether_probe(struct device_d *dev)
edev->get_ethaddr = dwc_ether_get_ethaddr;
edev->set_ethaddr = dwc_ether_set_ethaddr;
priv->phy_addr = pdata->phy_addr;
priv->interface = pdata->interface;
miibus->parent = dev;
miibus->read = dwc_ether_mii_read;
miibus->write = dwc_ether_mii_write;
@ -450,9 +481,19 @@ static void dwc_ether_remove(struct device_d *dev)
{
}
static __maybe_unused struct of_device_id dwc_ether_compatible[] = {
{
.compatible = "snps,dwmac-3.70a",
.data = (unsigned long)&dwmac_370a_drvdata,
}, {
/* sentinel */
}
};
static struct driver_d dwc_ether_driver = {
.name = "designware_eth",
.probe = dwc_ether_probe,
.remove = dwc_ether_remove,
.of_compatible = DRV_OF_COMPAT(dwc_ether_compatible),
};
device_platform_driver(dwc_ether_driver);

60
drivers/net/designware.h
View File

@ -130,27 +130,21 @@ struct dmamacdescr {
*/
/* tx status bits definitions */
#if defined(CONFIG_DRIVER_NET_DESIGNWARE_ALTDESCRIPTOR)
#define DESC_ENH_TXSTS_OWNBYDMA (1 << 31)
#define DESC_ENH_TXSTS_TXINT (1 << 30)
#define DESC_ENH_TXSTS_TXLAST (1 << 29)
#define DESC_ENH_TXSTS_TXFIRST (1 << 28)
#define DESC_ENH_TXSTS_TXCRCDIS (1 << 27)
#define DESC_TXSTS_OWNBYDMA (1 << 31)
#define DESC_TXSTS_TXINT (1 << 30)
#define DESC_TXSTS_TXLAST (1 << 29)
#define DESC_TXSTS_TXFIRST (1 << 28)
#define DESC_TXSTS_TXCRCDIS (1 << 27)
#define DESC_TXSTS_TXPADDIS (1 << 26)
#define DESC_TXSTS_TXCHECKINSCTRL (3 << 22)
#define DESC_TXSTS_TXRINGEND (1 << 21)
#define DESC_TXSTS_TXCHAIN (1 << 20)
#define DESC_TXSTS_MSK (0x1FFFF << 0)
#else
#define DESC_ENH_TXSTS_TXPADDIS (1 << 26)
#define DESC_ENH_TXSTS_TXCHECKINSCTRL (3 << 22)
#define DESC_ENH_TXSTS_TXRINGEND (1 << 21)
#define DESC_ENH_TXSTS_TXCHAIN (1 << 20)
#define DESC_ENH_TXSTS_MSK (0x1FFFF << 0)
#define DESC_TXSTS_OWNBYDMA (1 << 31)
#define DESC_TXSTS_MSK (0x1FFFF << 0)
#endif
/* rx status bits definitions */
#define DESC_RXSTS_OWNBYDMA (1 << 31)
#define DESC_RXSTS_DAFILTERFAIL (1 << 30)
@ -178,14 +172,10 @@ struct dmamacdescr {
*/
/* tx control bits definitions */
#if defined(CONFIG_DRIVER_NET_DESIGNWARE_ALTDESCRIPTOR)
#define DESC_TXCTRL_SIZE1MASK (0x1FFF << 0)
#define DESC_TXCTRL_SIZE1SHFT (0)
#define DESC_TXCTRL_SIZE2MASK (0x1FFF << 16)
#define DESC_TXCTRL_SIZE2SHFT (16)
#else
#define DESC_ENH_TXCTRL_SIZE1MASK (0x1FFF << 0)
#define DESC_ENH_TXCTRL_SIZE1SHFT (0)
#define DESC_ENH_TXCTRL_SIZE2MASK (0x1FFF << 16)
#define DESC_ENH_TXCTRL_SIZE2SHFT (16)
#define DESC_TXCTRL_TXINT (1 << 31)
#define DESC_TXCTRL_TXLAST (1 << 30)
@ -200,21 +190,15 @@ struct dmamacdescr {
#define DESC_TXCTRL_SIZE2MASK (0x7FF << 11)
#define DESC_TXCTRL_SIZE2SHFT (11)
#endif
/* rx control bits definitions */
#if defined(CONFIG_DRIVER_NET_DESIGNWARE_ALTDESCRIPTOR)
#define DESC_ENH_RXCTRL_RXINTDIS (1 << 31)
#define DESC_ENH_RXCTRL_RXRINGEND (1 << 15)
#define DESC_ENH_RXCTRL_RXCHAIN (1 << 14)
#define DESC_RXCTRL_RXINTDIS (1 << 31)
#define DESC_RXCTRL_RXRINGEND (1 << 15)
#define DESC_RXCTRL_RXCHAIN (1 << 14)
#define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0)
#define DESC_RXCTRL_SIZE1SHFT (0)
#define DESC_RXCTRL_SIZE2MASK (0x1FFF << 16)
#define DESC_RXCTRL_SIZE2SHFT (16)
#else
#define DESC_ENH_RXCTRL_SIZE1MASK (0x1FFF << 0)
#define DESC_ENH_RXCTRL_SIZE1SHFT (0)
#define DESC_ENH_RXCTRL_SIZE2MASK (0x1FFF << 16)
#define DESC_ENH_RXCTRL_SIZE2SHFT (16)
#define DESC_RXCTRL_RXINTDIS (1 << 31)
#define DESC_RXCTRL_RXRINGEND (1 << 25)
@ -226,5 +210,3 @@ struct dmamacdescr {
#define DESC_RXCTRL_SIZE2SHFT (11)
#endif
#endif

22
drivers/net/macb.c
View File

@ -458,9 +458,31 @@ static int macb_phy_write(struct mii_bus *bus, int addr, int reg, u16 value)
static int macb_get_ethaddr(struct eth_device *edev, unsigned char *adr)
{
struct macb_device *macb = edev->priv;
u32 bottom;
u16 top;
u8 addr[6];
int i;
dev_dbg(macb->dev, "%s\n", __func__);
/* Check all 4 address register for vaild address */
for (i = 0; i < 4; i++) {
bottom = macb_or_gem_readl(macb, SA1B + i * 8);
top = macb_or_gem_readl(macb, SA1T + i * 8);
addr[0] = bottom & 0xff;
addr[1] = (bottom >> 8) & 0xff;
addr[2] = (bottom >> 16) & 0xff;
addr[3] = (bottom >> 24) & 0xff;
addr[4] = top & 0xff;
addr[5] = (top >> 8) & 0xff;
if (is_valid_ether_addr(addr)) {
memcpy(adr, addr, sizeof(addr));
return 0;
}
}
return -1;
}

30
drivers/net/smc91111.c
View File

@ -66,6 +66,7 @@
#include <clock.h>
#include <io.h>
#include <linux/phy.h>
#include <net/smc91111.h>
/*---------------------------------------------------------------
.
@ -446,6 +447,7 @@ struct smc91c111_priv {
struct mii_bus miibus;
struct accessors a;
void __iomem *base;
int qemu_fixup;
};
#if (SMC_DEBUG > 2 )
@ -882,6 +884,7 @@ static void smc91c111_enable(struct eth_device *edev)
static int smc91c111_eth_open(struct eth_device *edev)
{
struct smc91c111_priv *priv = (struct smc91c111_priv *)edev->priv;
int ret;
/* Configure the Receive/Phy Control register */
SMC_SELECT_BANK(priv, 0);
@ -889,8 +892,27 @@ static int smc91c111_eth_open(struct eth_device *edev)
smc91c111_enable(edev);
return phy_device_connect(edev, &priv->miibus, 0, NULL,
ret = phy_device_connect(edev, &priv->miibus, 0, NULL,
0, PHY_INTERFACE_MODE_NA);
if (ret)
return ret;
if (priv->qemu_fixup && edev->phydev->phy_id == 0x00000000) {
struct phy_device *dev = edev->phydev;
dev->speed = SPEED_100;
dev->duplex = DUPLEX_FULL;
dev->autoneg = !AUTONEG_ENABLE;
dev->force = 1;
dev->link = 1;
dev_info(edev->parent, "phy with id 0x%08x detected this might be qemu\n",
dev->phy_id);
dev_info(edev->parent, "force link at 100Mpbs\n");
}
return 0;
}
static int smc91c111_eth_send(struct eth_device *edev, void *packet,
@ -1286,6 +1308,12 @@ static int smc91c111_probe(struct device_d *dev)
priv = edev->priv;
if (dev->platform_data) {
struct smc91c111_pdata *pdata = dev->platform_data;
priv->qemu_fixup = pdata->qemu_fixup;
}
priv->a = access_via_32bit;
edev->init = smc91c111_init_dev;

42
include/local_mac_address.h Normal file
View File

@ -0,0 +1,42 @@
/*
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
*
* Under GPLv2 only
*/
#ifndef __LOCAL_MAC_ADDRESS_H__
#define __LOCAL_MAC_ADDRESS_H__
#include <net.h>
/**
* local_mac_address_register - use random number with fix
* OUI provided device to provide an Ethernet address
* @ethid: ethernet device id
* @oui: Ethernet OUI (3 bytes)
*
* Generate a local Ethernet address (MAC) that is not multicast using a 1-wire id.
*/
static inline int local_mac_address_register(int ethid, char * oui)
{
char addr[6];
int nb_oui = 3;
int i;
if (!oui)
return -EINVAL;
random_ether_addr(addr);
for (i = 0; i < nb_oui; i++)
addr[i] = oui[i];
addr[0] &= 0xfe; /* clear multicast bit */
addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
eth_register_ethaddr(ethid, addr);
return 0;
}
#endif /* __LOCAL_MAC_ADDRESS_H__ */

1
include/net/designware.h
View File

@ -7,6 +7,7 @@ struct dwc_ether_platform_data {
int phy_addr;
phy_interface_t interface;
void (*fix_mac_speed)(int speed);
bool enh_desc; /* use Alternate/Enhanced Descriptor configurations */
};
#endif

14
include/net/smc91111.h Normal file
View File

@ -0,0 +1,14 @@
/*
* Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
*
* Under GPLv2 only
*/
#ifndef __SMC91111_H__
#define __SMC91111_H__
struct smc91c111_pdata {
int qemu_fixup;
};
#endif /* __SMC91111_H__ */