From 1515c7f091d5e2edd104fb7026cc50f13ab43f9a Mon Sep 17 00:00:00 2001 From: Cristiano De Alti Date: Mon, 3 Feb 2014 23:31:55 +0100 Subject: [PATCH 01/16] i.MX21 ADS defconfig: set CONFIG_NAND_IMX since this board has a 64MBi NAND flash Signed-off-by: Cristiano De Alti Signed-off-by: Sascha Hauer --- arch/arm/configs/freescale-mx21-ads_defconfig | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/arm/configs/freescale-mx21-ads_defconfig b/arch/arm/configs/freescale-mx21-ads_defconfig index 530f4837e..05f21d317 100644 --- a/arch/arm/configs/freescale-mx21-ads_defconfig +++ b/arch/arm/configs/freescale-mx21-ads_defconfig @@ -1,7 +1,5 @@ CONFIG_ARCH_IMX=y -CONFIG_ARCH_IMX21=y CONFIG_MACH_IMX21ADS=y -CONFIG_IMX_CLKO=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_TEXT_BASE=0xc3000000 CONFIG_MALLOC_SIZE=0x2000000 @@ -13,14 +11,12 @@ CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx21-ads/env" CONFIG_CMD_EDIT=y CONFIG_CMD_SLEEP=y CONFIG_CMD_SAVEENV=y -CONFIG_CMD_LOADENV=y CONFIG_CMD_EXPORT=y CONFIG_CMD_PRINTENV=y CONFIG_CMD_READLINE=y +CONFIG_CMD_TFTP=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_CRC=y -CONFIG_CMD_MTEST=y -CONFIG_CMD_MTEST_ALTERNATIVE=y CONFIG_CMD_FLASH=y CONFIG_CMD_BOOTM_SHOW_TYPE=y CONFIG_CMD_RESET=y @@ -32,11 +28,13 @@ CONFIG_NET=y CONFIG_NET_DHCP=y CONFIG_NET_NFS=y CONFIG_NET_PING=y -CONFIG_CMD_TFTP=y -CONFIG_FS_TFTP=y CONFIG_DRIVER_NET_CS8900=y # CONFIG_SPI is not set CONFIG_MTD=y CONFIG_DRIVER_CFI=y # CONFIG_DRIVER_CFI_INTEL is not set CONFIG_CFI_BUFFER_WRITE=y +CONFIG_NAND=y +CONFIG_NAND_IMX=y +CONFIG_NAND_IMX_BBM=y +CONFIG_FS_TFTP=y From 4395095ab5206c9d97618be3dab152fceaef6509 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20B=C3=A9nard?= Date: Sat, 8 Feb 2014 15:16:06 +0100 Subject: [PATCH 02/16] sata-imx: i.MX53, use the internal 120MHz clock by default MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit this allows SATA to work on i.MX53 QSB-R : barebox@Freescale i.MX53 Quick Start-R Board:/ ata0.probe=1 imx-sata 10000000.sata: port 0: SATA link ok imx-sata 10000000.sata: port 0: Spinning up device... imx-sata 10000000.sata: port 0: ok. ata0: registered /dev/ata0 before this fix the log was : barebox@Freescale i.MX53 Quick Start-R Board:/ ata0.probe=1 imx-sata 10000000.sata: port 0: SATA link timeout set parameter: Connection timed out Signed-off-by: Eric Bénard Signed-off-by: Sascha Hauer --- drivers/ata/sata-imx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ata/sata-imx.c b/drivers/ata/sata-imx.c index b7bd1107c..450cf4f53 100644 --- a/drivers/ata/sata-imx.c +++ b/drivers/ata/sata-imx.c @@ -59,7 +59,7 @@ static int imx53_sata_init(struct imx_ahci *imx_ahci) */ val = readl(base + 0x180c); val &= (0x3 << 1); - val |= (0x1 << 1); + val |= (0x2 << 1); writel(val, base + 0x180c); return 0; From 1c15af075f627c52d1e1e167115baa62dea97837 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20B=C3=A9nard?= Date: Sat, 8 Feb 2014 15:16:07 +0100 Subject: [PATCH 03/16] ARM: i.MX53: Add sata to devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Eric Bénard Signed-off-by: Sascha Hauer --- arch/arm/dts/imx53.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi index 678547cf1..91659b8ca 100644 --- a/arch/arm/dts/imx53.dtsi +++ b/arch/arm/dts/imx53.dtsi @@ -75,6 +75,15 @@ interrupt-parent = <&tzic>; ranges; + sata: sata@10000000 { + compatible = "fsl,imx53-ahci"; + reg = <0x10000000 0x1000>; + interrupts = <28>; + clocks = <&clks 173>, <&clks 5>, <&clks 188>; + clock-names = "sata", "ahb", "per"; + status = "disabled"; + }; + ipu: ipu@18000000 { #crtc-cells = <1>; compatible = "fsl,imx53-ipu"; From b43dee1a4323aa0d9460a68f5bbdf6e5681f4d30 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20B=C3=A9nard?= Date: Sat, 8 Feb 2014 15:16:08 +0100 Subject: [PATCH 04/16] ARM: mx53-qsrb: fix USB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - configure the MC34708 properly so that USB can work (the sequence is taken from u-boot) - add the required defines to the mc13xxx include file Signed-off-by: Eric Bénard Signed-off-by: Sascha Hauer --- arch/arm/boards/freescale-mx53-qsb/board.c | 45 ++++++++++++++++++++++ include/mfd/mc13xxx.h | 11 ++++++ 2 files changed, 56 insertions(+) diff --git a/arch/arm/boards/freescale-mx53-qsb/board.c b/arch/arm/boards/freescale-mx53-qsb/board.c index 69036dafc..74826e4a5 100644 --- a/arch/arm/boards/freescale-mx53-qsb/board.c +++ b/arch/arm/boards/freescale-mx53-qsb/board.c @@ -93,11 +93,56 @@ static int loco_late_init(void) mc34708 = mc13xxx_get(); if (mc34708) { + unsigned int val; + int ret; /* get the board revision from fuse */ rev = readl(MX53_IIM_BASE_ADDR + 0x878); set_board_rev(rev); printf("MCIMX53-START-R board 1.0 rev %c\n", (rev == 1) ? 'A' : 'B' ); armlinux_set_revision(loco_system_rev); + /* Set VDDGP to 1.25V for 1GHz on SW1 */ + mc13xxx_reg_read(mc34708, MC13892_REG_SW_0, &val); + val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708; + ret = mc13xxx_reg_write(mc34708, MC13892_REG_SW_0, val); + if (ret) { + printf("Writing to REG_SW_0 failed: %d\n", ret); + return ret; + } + + /* Set VCC as 1.30V on SW2 */ + mc13xxx_reg_read(mc34708, MC13892_REG_SW_1, &val); + val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708; + ret = mc13xxx_reg_write(mc34708, MC13892_REG_SW_1, val); + if (ret) { + printf("Writing to REG_SW_1 failed: %d\n", ret); + return ret; + } + + /* Set global reset timer to 4s */ + mc13xxx_reg_read(mc34708, MC13892_REG_POWER_CTL2, &val); + val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708; + ret = mc13xxx_reg_write(mc34708, MC13892_REG_POWER_CTL2, val); + if (ret) { + printf("Writing to REG_POWER_CTL2 failed: %d\n", ret); + return ret; + } + + /* Set VUSBSEL and VUSBEN for USB PHY supply*/ + mc13xxx_reg_read(mc34708, MC13892_REG_MODE_0, &val); + val |= (VUSBSEL_MC34708 | VUSBEN_MC34708); + ret = mc13xxx_reg_write(mc34708, MC13892_REG_MODE_0, val); + if (ret) { + printf("Writing to REG_MODE_0 failed: %d\n", ret); + return ret; + } + + /* Set SWBST to 5V in auto mode */ + val = SWBST_AUTO; + ret = mc13xxx_reg_write(mc34708, SWBST_CTRL, val); + if (ret) { + printf("Writing to SWBST_CTRL failed: %d\n", ret); + return ret; + } } else { /* so we have a DA9053 based board */ printf("MCIMX53-START board 1.0\n"); diff --git a/include/mfd/mc13xxx.h b/include/mfd/mc13xxx.h index cba85890c..1946b1a1c 100644 --- a/include/mfd/mc13xxx.h +++ b/include/mfd/mc13xxx.h @@ -152,6 +152,17 @@ #define MC13783_SW1B_SOFTSTART (1 << 17) #define MC13783_SW_PLL_FACTOR(x) (((x) - 28) << 19) +/* MC34708 Definitions */ +#define SWx_VOLT_MASK_MC34708 0x3F +#define SWx_1_250V_MC34708 0x30 +#define SWx_1_300V_MC34708 0x34 +#define TIMER_MASK_MC34708 0x300 +#define TIMER_4S_MC34708 0x100 +#define VUSBSEL_MC34708 (1 << 2) +#define VUSBEN_MC34708 (1 << 3) +#define SWBST_CTRL 31 +#define SWBST_AUTO 0x8 + struct mc13xxx; #ifdef CONFIG_MFD_MC13XXX From 9eaee0bb725faeb1819d0a85490f8a72422fbc95 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20B=C3=A9nard?= Date: Sat, 8 Feb 2014 15:16:09 +0100 Subject: [PATCH 05/16] ARM: mx53-qsrb: enable USB host MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - declare the rigth mux for the GPIO used to enable the USB's 5V - enable USB host controller tested on i.MX53 START-R : barebox@Freescale i.MX53 Quick Start-R Board:/ usb -f USB: scanning bus for devices... Bus 001 Device 001: ID 0000:0000 EHCI Host Controller Using index 0 for the new disk Bus 002 Device 003: ID 0951:1654 DT R500 Bus 002 Device 002: ID 0000:0000 EHCI Host Controller 3 USB Device(s) found Signed-off-by: Eric Bénard Signed-off-by: Sascha Hauer --- arch/arm/dts/imx53-qsb-common.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/imx53-qsb-common.dtsi b/arch/arm/dts/imx53-qsb-common.dtsi index f2f912b07..344b0b483 100644 --- a/arch/arm/dts/imx53-qsb-common.dtsi +++ b/arch/arm/dts/imx53-qsb-common.dtsi @@ -158,6 +158,7 @@ MX53_PAD_EIM_DA13__GPIO3_13 0x80000000 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 MX53_PAD_GPIO_16__GPIO7_11 0x80000000 + MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 >; }; @@ -216,7 +217,9 @@ }; &usbh1 { - status = "okay"; + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; }; &usbotg { From c65ac4d991a8ec954b3afb266d44382c3ac3f254 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20B=C3=A9nard?= Date: Sat, 8 Feb 2014 15:16:10 +0100 Subject: [PATCH 06/16] ARM: mx53-qsrb: enable USB OTG in host mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit tested on i.MX53 START-R : barebox@Freescale i.MX53 Quick Start-R Board:/ usb -f USB: scanning bus for devices... Using index 0 for the new disk Bus 001 Device 002: ID 0951:1654 DT R500 Bus 001 Device 001: ID 0000:0000 EHCI Host Controller Bus 002 Device 003: ID 0000:0000 EHCI Host Controller 3 USB Device(s) found Signed-off-by: Eric Bénard Signed-off-by: Sascha Hauer --- arch/arm/dts/imx53-qsb-common.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/imx53-qsb-common.dtsi b/arch/arm/dts/imx53-qsb-common.dtsi index 344b0b483..94dc5233e 100644 --- a/arch/arm/dts/imx53-qsb-common.dtsi +++ b/arch/arm/dts/imx53-qsb-common.dtsi @@ -223,5 +223,6 @@ }; &usbotg { - status = "okay"; + phy_type = "utmi"; + status = "okay"; }; From 9c08524f8ae37951b16451a50b149e7bb2577f51 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20B=C3=A9nard?= Date: Sat, 8 Feb 2014 15:16:11 +0100 Subject: [PATCH 07/16] ARM: mx53-qsrb: enable sata MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit tested on i.MX53 START-R : barebox@Freescale i.MX53 Quick Start-R Board:/ ata0.probe=1 imx-sata 10000000.sata: port 0: SATA link ok imx-sata 10000000.sata: port 0: Spinning up device... imx-sata 10000000.sata: port 0: ok. ata0: registered /dev/ata0 Signed-off-by: Eric Bénard Signed-off-by: Sascha Hauer --- arch/arm/dts/imx53-qsb-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/imx53-qsb-common.dtsi b/arch/arm/dts/imx53-qsb-common.dtsi index 94dc5233e..571da92ad 100644 --- a/arch/arm/dts/imx53-qsb-common.dtsi +++ b/arch/arm/dts/imx53-qsb-common.dtsi @@ -226,3 +226,7 @@ phy_type = "utmi"; status = "okay"; }; + +&sata { + status = "okay"; +}; From ef08a80de89f897ed38336e5223cac43dbc697d6 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 5 Feb 2014 14:35:20 +0100 Subject: [PATCH 08/16] ARM: i.MX25: Fix LCDC clocks - Make sure the LCDC ipg clock is turned off during startup - register all LCDC clocks (ahb, ipg, per) and pass them to driver This is necessary because the LCDC doesn't have an enable bit. It just starts working once the clocks are turned on. If the registers have invalid values at that time the controller goes into some error state. So we have to make sure the clocks are turned off during startup and only turned on in the driver. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/clk-imx25.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index 4d8631cb0..1114ad277 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c @@ -55,7 +55,20 @@ enum mx25_clks { per7_sel, per8_sel, per9_sel, per10_sel, per11_sel, per12_sel, per13_sel, per14_sel, per15_sel, per0, per1, per2, per3, per4, per5, per6, per7, per8, per9, per10, per11, per12, per13, per14, per15, - lcdc_per_gate, clk_max + csi_ipg_per, epit_ipg_per, esai_ipg_per, esdhc1_ipg_per, esdhc2_ipg_per, + gpt_ipg_per, i2c_ipg_per, lcdc_ipg_per, nfc_ipg_per, owire_ipg_per, + pwm_ipg_per, sim1_ipg_per, sim2_ipg_per, ssi1_ipg_per, ssi2_ipg_per, + uart_ipg_per, ata_ahb, reserved1, csi_ahb, emi_ahb, esai_ahb, esdhc1_ahb, + esdhc2_ahb, fec_ahb, lcdc_ahb, rtic_ahb, sdma_ahb, slcdc_ahb, usbotg_ahb, + reserved2, reserved3, reserved4, reserved5, can1_ipg, can2_ipg, csi_ipg, + cspi1_ipg, cspi2_ipg, cspi3_ipg, dryice_ipg, ect_ipg, epit1_ipg, epit2_ipg, + reserved6, esdhc1_ipg, esdhc2_ipg, fec_ipg, reserved7, reserved8, reserved9, + gpt1_ipg, gpt2_ipg, gpt3_ipg, gpt4_ipg, reserved10, reserved11, reserved12, + iim_ipg, reserved13, reserved14, kpp_ipg, lcdc_ipg, reserved15, pwm1_ipg, + pwm2_ipg, pwm3_ipg, pwm4_ipg, rngb_ipg, reserved16, scc_ipg, sdma_ipg, + sim1_ipg, sim2_ipg, slcdc_ipg, spba_ipg, ssi1_ipg, ssi2_ipg, tsc_ipg, + uart1_ipg, uart2_ipg, uart3_ipg, uart4_ipg, uart5_ipg, reserved17, + wdt_ipg, clk_max }; static struct clk *clks[clk_max]; @@ -83,7 +96,7 @@ static int imx25_ccm_probe(struct device_d *dev) writel((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 13) | (1 << 14) | (1 << 15) | (1 << 19) | (1 << 20) | (1 << 21) | (1 << 22) | - (1 << 26) | (1 << 29) | (1 << 31), + (1 << 26) | (1 << 31), base + CCM_CGCR1); writel((1 << 0) | (1 << 1) | (1 << 2) | (1 << 10) | (1 << 13) | (1 << 14) | @@ -132,7 +145,9 @@ static int imx25_ccm_probe(struct device_d *dev) clks[per13] = imx_clk_divider("per13", "per13_sel", base + CCM_PCDR3, 8, 6); clks[per14] = imx_clk_divider("per14", "per14_sel", base + CCM_PCDR3, 16, 6); clks[per15] = imx_clk_divider("per15", "per15_sel", base + CCM_PCDR3, 24, 6); - clks[lcdc_per_gate] = imx_clk_gate("lcdc_per_gate", "per7", base + CCM_CGCR0, 7); + clks[lcdc_ahb] = imx_clk_gate("lcdc_ahb", "ahb", base + CCM_CGCR0, 24); + clks[lcdc_ipg] = imx_clk_gate("lcdc_ipg", "ipg", base + CCM_CGCR1, 29); + clks[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per7", base + CCM_CGCR0, 7); clkdev_add_physbase(clks[per15], MX25_UART1_BASE_ADDR, NULL); clkdev_add_physbase(clks[per15], MX25_UART2_BASE_ADDR, NULL); @@ -152,9 +167,9 @@ static int imx25_ccm_probe(struct device_d *dev) clkdev_add_physbase(clks[ipg], MX25_CSPI3_BASE_ADDR, NULL); clkdev_add_physbase(clks[per3], MX25_ESDHC1_BASE_ADDR, NULL); clkdev_add_physbase(clks[per4], MX25_ESDHC2_BASE_ADDR, NULL); - clkdev_add_physbase(clks[lcdc_per_gate], MX25_LCDC_BASE_ADDR, NULL); - clkdev_add_physbase(clks[dummy], MX25_LCDC_BASE_ADDR, "ipg"); - clkdev_add_physbase(clks[dummy], MX25_LCDC_BASE_ADDR, "ahb"); + clkdev_add_physbase(clks[lcdc_ipg_per], MX25_LCDC_BASE_ADDR, "per"); + clkdev_add_physbase(clks[lcdc_ipg], MX25_LCDC_BASE_ADDR, "ipg"); + clkdev_add_physbase(clks[lcdc_ahb], MX25_LCDC_BASE_ADDR, "ahb"); return 0; } From 0d70fb43e0f52ecc2ad5d7a0fdaa20eee7a70048 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 5 Feb 2014 14:39:16 +0100 Subject: [PATCH 09/16] video: imx: Add a name to perclk perclk should be named 'per' to make sure we get the correct clock. Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/clk-imx21.c | 2 +- arch/arm/mach-imx/clk-imx27.c | 2 +- drivers/video/imx.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c index 295ef3aee..be9c46611 100644 --- a/arch/arm/mach-imx/clk-imx21.c +++ b/arch/arm/mach-imx/clk-imx21.c @@ -164,7 +164,7 @@ static int imx21_ccm_probe(struct device_d *dev) clkdev_add_physbase(clks[ipg], MX21_I2C_BASE_ADDR, NULL); clkdev_add_physbase(clks[ipg], MX21_SDHC1_BASE_ADDR, NULL); clkdev_add_physbase(clks[ipg], MX21_SDHC2_BASE_ADDR, NULL); - clkdev_add_physbase(clks[lcdc_per_gate], MX21_LCDC_BASE_ADDR, NULL); + clkdev_add_physbase(clks[lcdc_per_gate], MX21_LCDC_BASE_ADDR, "per"); clkdev_add_physbase(clks[lcdc_ahb_gate], MX21_LCDC_BASE_ADDR, "ahb"); clkdev_add_physbase(clks[lcdc_ipg_gate], MX21_LCDC_BASE_ADDR, "ipg"); diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c index c7922612e..2423627cf 100644 --- a/arch/arm/mach-imx/clk-imx27.c +++ b/arch/arm/mach-imx/clk-imx27.c @@ -237,7 +237,7 @@ static int imx27_ccm_probe(struct device_d *dev) clkdev_add_physbase(clks[per2_div], MX27_SDHC1_BASE_ADDR, NULL); clkdev_add_physbase(clks[per2_div], MX27_SDHC2_BASE_ADDR, NULL); clkdev_add_physbase(clks[per2_div], MX27_SDHC3_BASE_ADDR, NULL); - clkdev_add_physbase(clks[per3_gate], MX27_LCDC_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per3_gate], MX27_LCDC_BASE_ADDR, "per"); clkdev_add_physbase(clks[lcdc_ahb_gate], MX27_LCDC_BASE_ADDR, "ahb"); clkdev_add_physbase(clks[lcdc_ipg_gate], MX27_LCDC_BASE_ADDR, "ipg"); clkdev_add_physbase(clks[ipg], MX27_FEC_BASE_ADDR, NULL); diff --git a/drivers/video/imx.c b/drivers/video/imx.c index 6e2d8d6f7..05c6105c7 100644 --- a/drivers/video/imx.c +++ b/drivers/video/imx.c @@ -530,7 +530,7 @@ static int imxfb_probe(struct device_d *dev) fbi = xzalloc(sizeof(*fbi)); info = &fbi->info; - fbi->per_clk = clk_get(dev, NULL); + fbi->per_clk = clk_get(dev, "per"); if (IS_ERR(fbi->per_clk)) return PTR_ERR(fbi->per_clk); From 42f9e4d8fe069264d4c68b3680b623584b5fcd4e Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 18 Feb 2014 12:17:16 +0100 Subject: [PATCH 10/16] ARM: i.MX: Karo-tx25: build image for internal boot This adds an image for the TX25 in internal boot mode. This can be used for USB booting. Signed-off-by: Sascha Hauer --- images/Makefile.imx | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/images/Makefile.imx b/images/Makefile.imx index 9aca871fd..b57776a19 100644 --- a/images/Makefile.imx +++ b/images/Makefile.imx @@ -14,6 +14,11 @@ pblx-$(CONFIG_MACH_TX25) += start_imx25_karo_tx25 FILE_barebox-karo-tx25.img = start_imx25_karo_tx25.pblx image-$(CONFIG_MACH_TX25) += barebox-karo-tx25.img +pblx-$(CONFIG_MACH_TX25) += start_imx25_karo_tx25 +CFG_start_imx25_karo_tx25.pblx.imximg = $(board)/karo-tx25/flash-header-tx25.imxcfg +FILE_barebox-karo-tx25-internal.img = start_imx25_karo_tx25.pblx.imximg +image-$(CONFIG_MACH_TX25) += barebox-karo-tx25-internal.img + # ----------------------- i.MX51 based boards --------------------------- pblx-$(CONFIG_MACH_FREESCALE_MX51_PDK) += start_imx51_babbage CFG_start_imx51_babbage.pblx.imximg = $(board)/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg From c0afc9f425a38c485c06fea0e75f7d43aea9bdcb Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 17 Feb 2014 13:04:11 +0100 Subject: [PATCH 11/16] ARM: i.MX6: sabresd: set USB PHY and DR mode Signed-off-by: Lucas Stach Signed-off-by: Sascha Hauer --- arch/arm/dts/imx6qdl-sabresd.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/imx6qdl-sabresd.dtsi b/arch/arm/dts/imx6qdl-sabresd.dtsi index 346e32a22..78c9fd54e 100644 --- a/arch/arm/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/dts/imx6qdl-sabresd.dtsi @@ -280,6 +280,8 @@ &usbh1 { vbus-supply = <®_usb_h1_vbus>; + phy_type = "utmi"; + dr_mode = "host"; status = "okay"; }; @@ -287,6 +289,8 @@ vbus-supply = <®_usb_otg_vbus>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; disable-over-current; status = "okay"; }; From 6613e2d8fbd68c0f520363b74329f066864864ff Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 20 Feb 2014 14:43:13 +0100 Subject: [PATCH 12/16] ARM: i.MX: Make mxc_iomux_v3_setup_multiple_pads argument const Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/include/mach/iomux-v3.h | 2 +- drivers/pinctrl/imx-iomux-v3.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/include/mach/iomux-v3.h b/arch/arm/mach-imx/include/mach/iomux-v3.h index 219786be3..b8cc9af68 100644 --- a/arch/arm/mach-imx/include/mach/iomux-v3.h +++ b/arch/arm/mach-imx/include/mach/iomux-v3.h @@ -113,6 +113,6 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad); * setups mutliple pads * convenient way to call the above function with tables */ -int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count); +int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list, unsigned count); #endif /* __MACH_IOMUX_V3_H__*/ diff --git a/drivers/pinctrl/imx-iomux-v3.c b/drivers/pinctrl/imx-iomux-v3.c index 7fcbb98d0..1319690d5 100644 --- a/drivers/pinctrl/imx-iomux-v3.c +++ b/drivers/pinctrl/imx-iomux-v3.c @@ -76,9 +76,9 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad) EXPORT_SYMBOL(mxc_iomux_v3_setup_pad); -int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) +int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list, unsigned count) { - iomux_v3_cfg_t *p = pad_list; + const iomux_v3_cfg_t *p = pad_list; int i; int ret; From 1d8a49ae881e336f15b89ea3005f30bb82a1793c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rapha=C3=ABl=20POGGI?= Date: Mon, 17 Feb 2014 14:04:12 -0800 Subject: [PATCH 13/16] ARM: add minimal support for the Freescale Quad UDOO Board Adding minimal support for the UDOO board. For more information about the board: http://www.udoo.org/ Signed-off-by: Raphael Poggi Signed-off-by: Sascha Hauer --- arch/arm/boards/Makefile | 1 + arch/arm/boards/udoo/Makefile | 3 + arch/arm/boards/udoo/board.c | 194 ++++++++++++++++++ arch/arm/boards/udoo/env/config-board | 6 + .../boards/udoo/flash-header-mx6-udoo.imxcfg | 104 ++++++++++ arch/arm/boards/udoo/lowlevel.c | 17 ++ arch/arm/configs/imx_v7_defconfig | 1 + arch/arm/dts/Makefile | 4 +- arch/arm/dts/imx6q-udoo.dts | 22 ++ arch/arm/dts/imx6qdl-udoo.dtsi | 118 +++++++++++ arch/arm/mach-imx/Kconfig | 5 + images/Makefile.imx | 5 + 12 files changed, 479 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boards/udoo/Makefile create mode 100644 arch/arm/boards/udoo/board.c create mode 100644 arch/arm/boards/udoo/env/config-board create mode 100644 arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg create mode 100644 arch/arm/boards/udoo/lowlevel.c create mode 100644 arch/arm/dts/imx6q-udoo.dts create mode 100644 arch/arm/dts/imx6qdl-udoo.dtsi diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index befddd039..a45adee0f 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -91,6 +91,7 @@ obj-$(CONFIG_MACH_TX25) += karo-tx25/ obj-$(CONFIG_MACH_TX28) += karo-tx28/ obj-$(CONFIG_MACH_TX51) += karo-tx51/ obj-$(CONFIG_MACH_TX53) += karo-tx53/ +obj-$(CONFIG_MACH_UDOO) += udoo/ obj-$(CONFIG_MACH_USB_A9260) += usb-a926x/ obj-$(CONFIG_MACH_USB_A9263) += usb-a926x/ obj-$(CONFIG_MACH_USB_A9G20) += usb-a926x/ diff --git a/arch/arm/boards/udoo/Makefile b/arch/arm/boards/udoo/Makefile new file mode 100644 index 000000000..ae17789b8 --- /dev/null +++ b/arch/arm/boards/udoo/Makefile @@ -0,0 +1,3 @@ +obj-y += board.o flash-header-mx6-udoo.dcd.o +extra-y += flash-header-mx6-udoo.dcd.S flash-header-mx6-udoo.dcd +lwl-y += lowlevel.o diff --git a/arch/arm/boards/udoo/board.c b/arch/arm/boards/udoo/board.c new file mode 100644 index 000000000..3846d4b1b --- /dev/null +++ b/arch/arm/boards/udoo/board.c @@ -0,0 +1,194 @@ +/* + * Copyright (C) 2014 Raphaël Poggi + * Copyright (C) 2012 Steffen Trumtrar, Pengutronix + * + * based on arch/arm/boards/freescale-mx6-arm2/board.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static iomux_v3_cfg_t udoo_enet_gpio_pads_1[] = { + /* RGMII reset */ + MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* alimentazione ethernet*/ + MX6Q_PAD_EIM_EB3__GPIO_2_31 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 32 - 1 - (MODE0) all */ + MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 31 - 1 - (MODE1) all */ + MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 28 - 1 - (MODE2) all */ + MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 27 - 1 - (MODE3) all */ + MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t udoo_enet_gpio_pads_2[] = { + /* Ethernet */ + MX6Q_PAD_RGMII_RXC__GPIO_6_30, /* PHYAD */ + MX6Q_PAD_RGMII_RD0__GPIO_6_25, /* MODE0 */ + MX6Q_PAD_RGMII_RD1__GPIO_6_27, /* MODE1 */ + MX6Q_PAD_RGMII_RD2__GPIO_6_28, /* MODE2 */ + MX6Q_PAD_RGMII_RD3__GPIO_6_29, /* MODE3 */ + MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL, +}; + +static int ksz9021rn_phy_fixup(struct phy_device *dev) +{ + + phy_write(dev, 0x09, 0x1c00); + phy_write(dev, 0x4, 0x0000); + phy_write(dev, 0x5, 0x0000); + phy_write(dev, 0x6, 0x0000); + phy_write(dev, 0x8, 0x03ff); + + /* do same as linux kernel */ + /* min rx data delay */ + phy_write(dev, 0x0b, 0x8105); + phy_write(dev, 0x0c, 0x0000); + + /* max rx/tx clock delay, min rx/tx control delay */ + phy_write(dev, 0x0b, 0x8104); + phy_write(dev, 0x0c, 0xf0f0); + phy_write(dev, 0x0b, 0x104); + + return 0; +} + +static int udoo_ksz9021rn_setup(void) +{ + if (!of_machine_is_compatible("udoo,imx6qdl-udoo")) + return 0; + + mxc_iomux_v3_setup_multiple_pads(udoo_enet_gpio_pads_1, + ARRAY_SIZE(udoo_enet_gpio_pads_1)); + + gpio_direction_output(IMX_GPIO_NR(2, 31) , 1); /* Power on enet */ + + /* MODE strap-in pins: advertise all capabilities */ + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); + + mdelay(100); + + gpio_free(IMX_GPIO_NR(6, 24)); + gpio_free(IMX_GPIO_NR(6, 25)); + gpio_free(IMX_GPIO_NR(6, 27)); + gpio_free(IMX_GPIO_NR(6, 28)); + gpio_free(IMX_GPIO_NR(6, 29)); + + mxc_iomux_v3_setup_multiple_pads(udoo_enet_gpio_pads_2, ARRAY_SIZE(udoo_enet_gpio_pads_2)); + + return 0; +} +/* + * Do this before the fec initializes but after our + * gpios are available. + */ +fs_initcall(udoo_ksz9021rn_setup); + +static void udoo_ehci_init(void) +{ + /* hub reset */ + gpio_direction_output(204, 0); + udelay(2000); + gpio_set_value(204, 1); +} + +static iomux_v3_cfg_t const wdog_pads[] = { + MX6Q_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6Q_PAD_EIM_D19__EPIT1_EPITO, +}; + +#define WDT_EN IMX_GPIO_NR(5, 4) +#define WDT_TRG IMX_GPIO_NR(3, 19) +static void udoo_wdog_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + gpio_direction_output(WDT_TRG, 0); + gpio_direction_output(WDT_EN, 1); + gpio_direction_input(WDT_TRG); +} + +static void udoo_epit_init(void) +{ + writel(0x0000000, MX6_EPIT1_BASE_ADDR); + writel(0x142000F, MX6_EPIT1_BASE_ADDR); + writel(0x30000, MX6_EPIT1_BASE_ADDR + 0x8); + writel(0x0, MX6_EPIT1_BASE_ADDR + 0xC); +} + +static int udoo_devices_init(void) +{ + if (!of_machine_is_compatible("udoo,imx6qdl-udoo")) + return 0; + + udoo_wdog_init(); + udoo_ehci_init(); + udoo_epit_init(); + + armlinux_set_bootparams((void *)0x10000100); + + return 0; +} +device_initcall(udoo_devices_init); + +static int udoo_coredevices_init(void) +{ + if (!of_machine_is_compatible("udoo,imx6qdl-udoo")) + return 0; + + phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, + ksz9021rn_phy_fixup); + return 0; +} +coredevice_initcall(udoo_coredevices_init); + +static int udoo_postcore_init(void) +{ + if (!of_machine_is_compatible("udoo,imx6qdl-udoo")) + return 0; + + imx6_init_lowlevel(); + + barebox_set_hostname("udoo"); + + return 0; +} +postcore_initcall(udoo_postcore_init); diff --git a/arch/arm/boards/udoo/env/config-board b/arch/arm/boards/udoo/env/config-board new file mode 100644 index 000000000..4cabac63d --- /dev/null +++ b/arch/arm/boards/udoo/env/config-board @@ -0,0 +1,6 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.linux.bootargs.base="console=ttymxc1,115200" diff --git a/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg b/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg new file mode 100644 index 000000000..b142f59aa --- /dev/null +++ b/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg @@ -0,0 +1,104 @@ +soc imx6 +loadaddr 0x20000000 +dcdofs 0x400 + + +/* MX6_IOM_DRAM_SDQS0 -> MX6_IOM_DRAM_SDQS7 */ +wm 32 0x020e05a8 0x00000030 +wm 32 0x020e05b0 0x00000030 +wm 32 0x020e0524 0x00000030 +wm 32 0x020e051c 0x00000030 +wm 32 0x020e0518 0x00000030 +wm 32 0x020e050c 0x00000030 +wm 32 0x020e05b8 0x00000030 +wm 32 0x020e05c0 0x00000030 +/********************************************/ + +/* MX6_IOM_DRAM_DQM0 -> MX6_IOM_DRAM_DQM7 */ +wm 32 0x020e05ac 0x00020030 +wm 32 0x020e05b4 0x00020030 +wm 32 0x020e0528 0x00020030 +wm 32 0x020e0520 0x00020030 +wm 32 0x020e0514 0x00020030 +wm 32 0x020e0510 0x00020030 +wm 32 0x020e05bc 0x00020030 +wm 32 0x020e05c4 0x00020030 +/******************************************/ + +wm 32 0x020e056c 0x00020030 /* MX6_IOM_DRAM_CAS */ +wm 32 0x020e0578 0x00020030 /* MX6_IOM_DRAM_RAS */ +wm 32 0x020e0588 0x00020030 /* MX6_IOM_DRAM_SDCLK_0 */ +wm 32 0x020e0594 0x00020030 /* MX6_IOM_DRAM_SDCLK_1 */ +wm 32 0x020e057c 0x00020030 /* MX6_IOM_DRAM_RESET */ +wm 32 0x020e0590 0x00003000 +wm 32 0x020e0598 0x00003000 +wm 32 0x020e058c 0x00000000 +wm 32 0x020e059c 0x00003030 +wm 32 0x020e05a0 0x00003030 + +/* MX6_IOM_GRP_B0DS -> MX6_IOM_GRP_B7DS */ +wm 32 0x020e0784 0x00000030 +wm 32 0x020e0788 0x00000030 +wm 32 0x020e0794 0x00000030 +wm 32 0x020e079c 0x00000030 +wm 32 0x020e07a0 0x00000030 +wm 32 0x020e07a4 0x00000030 +wm 32 0x020e07a8 0x00000030 +wm 32 0x020e0748 0x00000030 +/***************************************/ + +wm 32 0x020e074c 0x00000030 /* MX6_IOM_GRP_ADDDS */ +wm 32 0x020e0750 0x00020000 +wm 32 0x020e0758 0x00000000 +wm 32 0x020e0774 0x00020000 +wm 32 0x020e078c 0x00000030 /* MX6_IOM_GRP_CTLDS */ +wm 32 0x020e0798 0x000c0000 +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + + +wm 32 0x021b0004 0x00020036 +wm 32 0x021b0008 0x09444040 +wm 32 0x021b000c 0x54597955 +wm 32 0x021b0010 0xFF328F64 +wm 32 0x021b0014 0x01FF00DB +wm 32 0x021b0018 0x00001740 +wm 32 0x021b001c 0x00008000 +wm 32 0x021b002c 0x000026D2 +wm 32 0x021b0030 0x00591023 +wm 32 0x021b0040 0x00000027 +wm 32 0x021b0000 0x831A0000 +wm 32 0x021b001c 0x04088032 +wm 32 0x021b001c 0x00008033 +wm 32 0x021b001c 0x00048031 +wm 32 0x021b001c 0x09408030 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b0800 0xA1380003 +wm 32 0x021b4800 0xA1380003 +wm 32 0x021b0020 0x00005800 +wm 32 0x021b0818 0x00011117 +wm 32 0x021b4818 0x00011117 +wm 32 0x021b083c 0x43510360 +wm 32 0x021b0840 0x0342033F +wm 32 0x021b483c 0x033F033F +wm 32 0x021b4840 0x03290266 +wm 32 0x021b0848 0x4B3E4141 +wm 32 0x021b4848 0x47413B4A +wm 32 0x021b0850 0x42404843 +wm 32 0x021b4850 0x4C3F4C45 +wm 32 0x021b080c 0x00350035 +wm 32 0x021b0810 0x001F001F +wm 32 0x021b480c 0x00010001 +wm 32 0x021b4810 0x00010001 +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 +wm 32 0x021b0004 0x00025576 +wm 32 0x021b0404 0x00011006 +wm 32 0x021b001c 0x00000000 + diff --git a/arch/arm/boards/udoo/lowlevel.c b/arch/arm/boards/udoo/lowlevel.c new file mode 100644 index 000000000..b54ddfec7 --- /dev/null +++ b/arch/arm/boards/udoo/lowlevel.c @@ -0,0 +1,17 @@ +#include +#include +#include +#include + +extern char __dtb_imx6q_udoo_start[]; + +ENTRY_FUNCTION(start_imx6_udoo, r0, r1, r2) +{ + uint32_t fdt; + + arm_cpu_lowlevel_init(); + + fdt = (uint32_t)__dtb_imx6q_udoo_start - get_runtime_offset(); + + barebox_arm_entry(0x10000000, SZ_1G, fdt); +} diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index 0f8b3ef0d..9634615ce 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -13,6 +13,7 @@ CONFIG_MACH_TQMA6X=y CONFIG_MACH_SABRELITE=y CONFIG_MACH_NITROGEN6X=y CONFIG_MACH_SOLIDRUN_HUMMINGBOARD=y +CONFIG_MACH_UDOO=y CONFIG_IMX_IIM=y CONFIG_IMX_IIM_FUSE_BLOW=y CONFIG_IMX_OCOTP=y diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 07508e3b2..950acd5bf 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -23,7 +23,8 @@ dtb-$(CONFIG_ARCH_IMX6) += imx6q-gk802.dtb \ imx6q-phytec-pbab01.dtb \ imx6dl-hummingboard.dtb \ imx6q-nitrogen6x.dtb \ - imx6dl-nitrogen6x.dtb + imx6dl-nitrogen6x.dtb \ + imx6q-udoo.dtb dtb-$(CONFIG_ARCH_MVEBU) += dove-cubox.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb @@ -55,6 +56,7 @@ pbl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o pbl-$(CONFIG_MACH_SOLIDRUN_HUMMINGBOARD) += imx6dl-hummingboard.dtb.o pbl-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o pbl-$(CONFIG_MACH_NITROGEN6X) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o +pbl-$(CONFIG_MACH_UDOO) += imx6q-udoo.dtb.o .SECONDARY: $(obj)/$(BUILTIN_DTB).dtb.S .SECONDARY: $(patsubst %,$(obj)/%.S,$(dtb-y)) diff --git a/arch/arm/dts/imx6q-udoo.dts b/arch/arm/dts/imx6q-udoo.dts new file mode 100644 index 000000000..5c79e9209 --- /dev/null +++ b/arch/arm/dts/imx6q-udoo.dts @@ -0,0 +1,22 @@ +/* + * Copyright 2014 Raphaël Poggi + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-udoo.dtsi" + +/ { + model = "Freescale i.MX6 Quad UDOO Board"; + compatible = "udoo,imx6q-udoo", "udoo,imx6qdl-udoo", "fsl,imx6q"; +}; diff --git a/arch/arm/dts/imx6qdl-udoo.dtsi b/arch/arm/dts/imx6qdl-udoo.dtsi new file mode 100644 index 000000000..e1ab2df46 --- /dev/null +++ b/arch/arm/dts/imx6qdl-udoo.dtsi @@ -0,0 +1,118 @@ +/* + * Copyright 2014 Raphaël Poggi + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include + +/ { + model = "Freescale i.MX6 UDOO Board"; + compatible = "udoo,imx6qdl-udoo", "fsl,imx6q"; + + chosen { + linux,stdout-path = &uart2; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_2p5v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6q-udoo { + pinctrl_hog: hoggrp { + fsl,pins = < + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = ; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = ; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = ; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = ; + }; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + status = "okay"; +}; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 5933f81e9..c5cc508ff 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -37,6 +37,7 @@ config ARCH_TEXT_BASE default 0x2fc00000 if MACH_TQMA6X default 0x4fc00000 if MACH_PHYTEC_PFLA02 default 0x4fc00000 if MACH_DFI_FS700_M60 + default 0x4fc00000 if MACH_UDOO config ARCH_IMX_INTERNAL_BOOT bool "support internal boot mode" @@ -233,6 +234,10 @@ config MACH_SOLIDRUN_HUMMINGBOARD bool "SolidRun Hummingboard" select ARCH_IMX6 +config MACH_UDOO + bool "Freescale i.MX6 UDOO Board" + select ARCH_IMX6 + endif # ---------------------------------------------------------- diff --git a/images/Makefile.imx b/images/Makefile.imx index b57776a19..a1e9bc41f 100644 --- a/images/Makefile.imx +++ b/images/Makefile.imx @@ -128,3 +128,8 @@ pblx-$(CONFIG_MACH_NITROGEN6X) += start_imx6dl_nitrogen6x_1g CFG_start_imx6dl_nitrogen6x_1g.pblx.imximg = $(board)/boundarydevices-nitrogen6x/flash-header-nitrogen6x-1g.imxcfg FILE_barebox-boundarydevices-imx6dl-nitrogen6x-1g.img = start_imx6dl_nitrogen6x_1g.pblx.imximg image-$(CONFIG_MACH_NITROGEN6X) += barebox-boundarydevices-imx6dl-nitrogen6x-1g.img + +pblx-$(CONFIG_MACH_UDOO) += start_imx6_udoo +CFG_start_imx6_udoo.pblx.imximg = $(board)/udoo/flash-header-mx6-udoo.imxcfg +FILE_barebox-udoo-imx6q.img = start_imx6_udoo.pblx.imximg +image-$(CONFIG_MACH_UDOO) += barebox-udoo-imx6q.img From 1ce7999774f25a51fd550e1d6c9b7c7751ba4826 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 20 Feb 2014 21:17:38 +0100 Subject: [PATCH 14/16] ARM: i.MX6: Add Garz+Fricke Santaro board support Most devices relevant for barebox like sd/emmc/network/uarts work. Devicetree contains several undefined drive strength settings, these can be fixed once the kernel has sorted this out. Signed-off-by: Sascha Hauer --- arch/arm/boards/Makefile | 1 + arch/arm/boards/guf-santaro/Makefile | 2 + arch/arm/boards/guf-santaro/board.c | 70 +++ .../boards/guf-santaro/flash-header.imxcfg | 109 ++++ arch/arm/boards/guf-santaro/lowlevel.c | 48 ++ arch/arm/configs/imx_v7_defconfig | 1 + arch/arm/dts/Makefile | 2 + arch/arm/dts/imx6q-guf-santaro.dts | 571 ++++++++++++++++++ arch/arm/mach-imx/Kconfig | 4 + images/Makefile.imx | 5 + 10 files changed, 813 insertions(+) create mode 100644 arch/arm/boards/guf-santaro/Makefile create mode 100644 arch/arm/boards/guf-santaro/board.c create mode 100644 arch/arm/boards/guf-santaro/flash-header.imxcfg create mode 100644 arch/arm/boards/guf-santaro/lowlevel.c create mode 100644 arch/arm/dts/imx6q-guf-santaro.dts diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index a45adee0f..aa8da3537 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += freescale-mx53-vmx53/ obj-$(CONFIG_MACH_GE863) += telit-evk-pro3/ obj-$(CONFIG_MACH_GK802) += gk802/ obj-$(CONFIG_MACH_GUF_CUPID) += guf-cupid/ +obj-$(CONFIG_MACH_GUF_SANTARO) += guf-santaro/ obj-$(CONFIG_MACH_GUF_VINCELL) += guf-vincell/ obj-$(CONFIG_MACH_HIGHBANK) += highbank/ obj-$(CONFIG_MACH_IMX21ADS) += freescale-mx21-ads/ diff --git a/arch/arm/boards/guf-santaro/Makefile b/arch/arm/boards/guf-santaro/Makefile new file mode 100644 index 000000000..01c7a259e --- /dev/null +++ b/arch/arm/boards/guf-santaro/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/guf-santaro/board.c b/arch/arm/boards/guf-santaro/board.c new file mode 100644 index 000000000..198c90a3c --- /dev/null +++ b/arch/arm/boards/guf-santaro/board.c @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2014 Sascha Hauer + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int santaro_postcore_init(void) +{ + if (!of_machine_is_compatible("guf,imx6q-santaro")) + return 0; + + imx6_init_lowlevel(); + + return 0; +} +postcore_initcall(santaro_postcore_init); + +static int santaro_device_init(void) +{ + uint32_t flag_sd = 0, flag_emmc = 0; + + if (!of_machine_is_compatible("guf,imx6q-santaro")) + return 0; + + barebox_set_hostname("santaro"); + + writew(0x0, MX6_WDOG1_BASE_ADDR + 0x8); + writew(0x0, MX6_WDOG2_BASE_ADDR + 0x8); + + if (bootsource_get() == BOOTSOURCE_MMC) { + switch (bootsource_get_instance()) { + case 1: + flag_sd |= BBU_HANDLER_FLAG_DEFAULT; + break; + case 3: + flag_emmc |= BBU_HANDLER_FLAG_DEFAULT; + break; + } + } + + imx6_bbu_internal_mmc_register_handler("sd", "/dev/mmc1", + flag_sd, NULL, 0, 0); + imx6_bbu_internal_mmc_register_handler("emmc", "/dev/mmc3.boot0", + flag_emmc, NULL, 0, 0); + + return 0; +} +device_initcall(santaro_device_init); diff --git a/arch/arm/boards/guf-santaro/flash-header.imxcfg b/arch/arm/boards/guf-santaro/flash-header.imxcfg new file mode 100644 index 000000000..510cae3c8 --- /dev/null +++ b/arch/arm/boards/guf-santaro/flash-header.imxcfg @@ -0,0 +1,109 @@ +loadaddr 0x10000000 +soc imx6 +dcdofs 0x400 + +wm 32 0x020e0798 0x000c0000 +wm 32 0x020e0758 0x00000000 + +wm 32 0x020e0588 0x00000030 +wm 32 0x020e0594 0x00000030 + +wm 32 0x020e056c 0x00000030 +wm 32 0x020e0578 0x00000030 +wm 32 0x020e074c 0x00000030 + +wm 32 0x020e057c 0x00000030 + +wm 32 0x020e058c 0x00000000 +wm 32 0x020e059c 0x00000030 +wm 32 0x020e05a0 0x00000030 +wm 32 0x020e078c 0x00000030 + +wm 32 0x020e0750 0x00020000 + +wm 32 0x020e05a8 0x00000030 +wm 32 0x020e05b0 0x00000030 +wm 32 0x020e0524 0x00000030 +wm 32 0x020e051c 0x00000030 +wm 32 0x020e0518 0x00000030 +wm 32 0x020e050c 0x00000030 +wm 32 0x020e05b8 0x00000030 +wm 32 0x020e05c0 0x00000030 + +wm 32 0x020e0774 0x00020000 + +wm 32 0x020e0784 0x00000030 +wm 32 0x020e0788 0x00000030 +wm 32 0x020e0794 0x00000030 +wm 32 0x020e079c 0x00000030 +wm 32 0x020e07a0 0x00000030 +wm 32 0x020e07a4 0x00000030 +wm 32 0x020e07a8 0x00000030 +wm 32 0x020e0748 0x00000030 + +wm 32 0x020e05ac 0x00000030 +wm 32 0x020e05b4 0x00000030 +wm 32 0x020e0528 0x00000030 +wm 32 0x020e0520 0x00000030 +wm 32 0x020e0514 0x00000030 +wm 32 0x020e0510 0x00000030 +wm 32 0x020e05bc 0x00000030 +wm 32 0x020e05c4 0x00000030 + +wm 32 0x021b0800 0xa1390003 + +wm 32 0x021b080c 0x001f001f +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x001f001f +wm 32 0x021b4810 0x001f001f + +wm 32 0x021b083c 0x4333033f +wm 32 0x021b0840 0x032c031d +wm 32 0x021b483c 0x43200332 +wm 32 0x021b4840 0x031a026a +wm 32 0x021b0848 0x4d464746 +wm 32 0x021b4848 0x47453f4d +wm 32 0x021b0850 0x3e434440 +wm 32 0x021b4850 0x47384839 + +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 + +wm 32 0x021b0004 0x00020036 +wm 32 0x021b0008 0x09444040 +wm 32 0x021b000c 0x555a7975 +wm 32 0x021b0010 0xff538f64 +wm 32 0x021b0014 0x01ff00db +wm 32 0x021b0018 0x00001740 + +wm 32 0x021b001c 0x00008000 +wm 32 0x021b002c 0x000026d2 +wm 32 0x021b0030 0x005a1023 +wm 32 0x021b0040 0x00000027 + +wm 32 0x021b0000 0x831a0000 + +wm 32 0x021b001c 0x04088032 +wm 32 0x021b001c 0x00008033 +wm 32 0x021b001c 0x00048031 +wm 32 0x021b001c 0x09408030 +wm 32 0x021b001c 0x04008040 + +wm 32 0x021b0020 0x00005800 + +wm 32 0x021b0818 0x00011117 +wm 32 0x021b4818 0x00011117 + +wm 32 0x021b0004 0x00025576 +wm 32 0x021b0404 0x00011006 +wm 32 0x021b001c 0x00000000 + diff --git a/arch/arm/boards/guf-santaro/lowlevel.c b/arch/arm/boards/guf-santaro/lowlevel.c new file mode 100644 index 000000000..da6d92af3 --- /dev/null +++ b/arch/arm/boards/guf-santaro/lowlevel.c @@ -0,0 +1,48 @@ +#include +#include +#include +#include +#include +#include +#include + +static inline void setup_uart(void) +{ + void __iomem *uartbase = (void *)MX6_UART2_BASE_ADDR; + void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR; + + writel(0x1, iomuxbase + 0x2b0); + + writel(0x00000000, uartbase + 0x80); + writel(0x00004027, uartbase + 0x84); + writel(0x00000704, uartbase + 0x88); + writel(0x00000a81, uartbase + 0x90); + writel(0x0000002b, uartbase + 0x9c); + writel(0x00013880, uartbase + 0xb0); + writel(0x0000047f, uartbase + 0xa4); + writel(0x0000c34f, uartbase + 0xa8); + writel(0x00000001, uartbase + 0x80); + + putc_ll('>'); +} + +extern char __dtb_imx6q_guf_santaro_start[]; + +ENTRY_FUNCTION(start_imx6q_guf_santaro, r0, r1, r2) +{ + uint32_t fdt; + int i; + + arm_cpu_lowlevel_init(); + + arm_setup_stack(0x00920000 - 8); + + for (i = 0x68; i <= 0x80; i += 4) + writel(0xffffffff, MX6_CCM_BASE_ADDR + i); + + setup_uart(); + + fdt = (uint32_t)__dtb_imx6q_guf_santaro_start - get_runtime_offset(); + + barebox_arm_entry(0x10000000, SZ_1G, fdt); +} diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index 9634615ce..e821061cf 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -7,6 +7,7 @@ CONFIG_MACH_TQMA53=y CONFIG_MACH_FREESCALE_MX53_VMX53=y CONFIG_MACH_PHYTEC_PFLA02=y CONFIG_MACH_DFI_FS700_M60=y +CONFIG_MACH_GUF_SANTARO=y CONFIG_MACH_REALQ7=y CONFIG_MACH_GK802=y CONFIG_MACH_TQMA6X=y diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 950acd5bf..001972a3c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_IMX6) += imx6q-gk802.dtb \ imx6q-mba6x.dtb \ imx6q-phytec-pbab01.dtb \ imx6dl-hummingboard.dtb \ + imx6q-guf-santaro.dtb \ imx6q-nitrogen6x.dtb \ imx6dl-nitrogen6x.dtb \ imx6q-udoo.dtb @@ -55,6 +56,7 @@ pbl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o pbl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o pbl-$(CONFIG_MACH_SOLIDRUN_HUMMINGBOARD) += imx6dl-hummingboard.dtb.o pbl-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o +pbl-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o pbl-$(CONFIG_MACH_NITROGEN6X) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o pbl-$(CONFIG_MACH_UDOO) += imx6q-udoo.dtb.o diff --git a/arch/arm/dts/imx6q-guf-santaro.dts b/arch/arm/dts/imx6q-guf-santaro.dts new file mode 100644 index 000000000..db93a4881 --- /dev/null +++ b/arch/arm/dts/imx6q-guf-santaro.dts @@ -0,0 +1,571 @@ +/* + * Copyright 2014 Sascha Hauer + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http:/*www.opensource.org/licenses/gpl-license.html + * http:/*www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include +#include "imx6q.dtsi" + +/ { + model = "Garz+Fricke i.MX6q Santaro"; + compatible = "guf,imx6q-santaro", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x40000000>; + }; + + chosen { + linux,stdout-path = &uart2; + + environment-emmc { + compatible = "barebox,environment"; + device-path = &usdhc2, "partname:barebox-environment"; + }; + }; + + reg_backlight: reg_backlight { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 22 0>; + enable-active-high; + }; + + backlight { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_backlight>; + status = "okay"; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + eeprom: m24c64@50 { + compatible = "st,24c32", "at24"; + reg = <0x50>; + }; + + pmic: pf0100@08 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + compatible = "pf0100-regulator"; + reg = <0x08>; + interrupt-parent = <&gpio7>; + interrupts = <13 8>; + + regulators { + reg_vddcore: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + reg_vddsoc: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + reg_gen_3v3: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_ddr_1v5a: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + reg_ddr_1v5b: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + reg_ddr_vtt: sw4 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + reg_5v_600mA: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-always-on; + }; + + reg_snvs_3v: vsnvs { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + reg_vrefddr: vrefddr { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + }; + + reg_vgen1_1v5: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + /* not used */ + }; + + reg_vgen2_1v2_eth: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + reg_vgen3_2v8: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen4_1v8: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen5_1v8_eth: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen6_3v3: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 201>; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + temp@49 { + compatible = "ti,lm73"; + reg = <0x49>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + polytouch: edt-ft5x06@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio1 20 1>; + wake-gpios = <&gpio1 18 0>; + edt,threshold = <30>; + edt,gain = <3>; + edt,offset = <0>; + edt,report-rate = <8>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-santaro { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x80000000 /* ATDETECT */ + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x80000000 /* EXTPWR */ + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x80000000 /* LED1 */ + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x80000000 /* CLEAR_ALL */ + MX6QDL_PAD_GPIO_9__WDOG1_B 0x80000000 /* WDT_OUTPUT */ + MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x80000000 /* RTC_INT */ + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x80000000 /* TALERT */ + MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x80000000 /* KP5V_OC */ + MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x80000000 /* KP5V_PWR */ + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x80000000 /* PFO_12V */ + + MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x80000000 /* DIG_IN1 */ + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x80000000 /* DIG_IN2 */ + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000 /* DIG_OUT1 */ + MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x80000000 /* DIG_OUT2 */ + + MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x80000000 /* KP_5V0 */ + >; + }; + + pinctrl_audio: audiogrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x80000000 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x80000000 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x80000000 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x80000000 + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x80000000 /* SGTL500 sys_mclk */ + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x80000000 /* SPEAKER_ON */ + >; + }; + + pinctrl_display: displaygrp { + fsl,pins = < + /* LVDS-GPIO */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x80000000 /* LCD_ENABLE */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x80000000 /* SEL6_8 */ + >; + }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x80000000 /* BL-PWM-Out */ + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x80000000 /* BL-ON */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + /* I2C1 (internal) */ + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + /* I2C3 (HDMI-DCC, ResTOUCH, CTOUCH ) */ + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x80000000 /* CTOUCH_INT2 */ + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x80000000 /* CTOUCH_INT */ + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000 /* CTOUCH_RESET2 */ + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x80000000 /* CTOUCH_RESET */ + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x80000000 /* ResTOUCH_INT */ + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + /* CTOUCH */ + MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x80000000 + MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x80000000 + MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x80000000 + MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x80000000 + MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x80000000 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x80000000 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x80000000 + MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x80000000 + >; + }; + + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 /* CAN/RS485_PWR_EN */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b1 /* RS485_DE */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1 + MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b1 /* uC_MDB_WakeUpOut */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x80000000 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x80000000 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x80000000 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x80000000 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x80000000 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x80000000 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x80000000 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x80000000 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x80000000 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x80000000 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x80000000 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x80000000 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x80000000 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x80000000 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x80000000 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x80000000 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 /* REF_CLK (in) */ + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 /* FEC_INT */ + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000 + MX6QDL_PAD_GPIO_3__USB_H1_OC 0x80000000 + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USB_HUB_CONNECT */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* USB_HUB_INT */ + >; + }; + + pinctrl_usbh2: usbh2grp { + fsl,pins = < + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x80000000 /* USBH2_DATA */ + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x80000000 /* USBH2_STROBE */ + >; + }; + + pinctrl_usboth: usbotggrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x80000000 + MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x80000000 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x80000000 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC_INT_B */ + >; + }; + + pinctrl_pfid: pfidgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 /* PFID0 */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 /* PFID1 */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* PFID2 */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 /* PFID3 */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000 /* PFID4 */ + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 /* PFID5 */ + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* PFID6 */ + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* PFID7 */ + >; + }; + + pinctrl_sram: sramgrp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x80000000 + MX6QDL_PAD_EIM_DA0__EIM_AD00 0x80000000 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0x80000000 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0x80000000 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0x80000000 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0x80000000 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0x80000000 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0x80000000 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0x80000000 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0x80000000 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0x80000000 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0x80000000 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0x80000000 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0x80000000 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0x80000000 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0x80000000 + MX6QDL_PAD_EIM_DA15__EIM_AD15 0x80000000 + MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x80000000 + MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x80000000 + MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x80000000 + MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x80000000 + MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x80000000 + MX6QDL_PAD_EIM_D16__EIM_DATA16 0x80000000 + MX6QDL_PAD_EIM_D17__EIM_DATA17 0x80000000 + MX6QDL_PAD_EIM_D18__EIM_DATA18 0x80000000 + MX6QDL_PAD_EIM_D19__EIM_DATA19 0x80000000 + MX6QDL_PAD_EIM_D20__EIM_DATA20 0x80000000 + MX6QDL_PAD_EIM_D21__EIM_DATA21 0x80000000 + MX6QDL_PAD_EIM_D22__EIM_DATA22 0x80000000 + MX6QDL_PAD_EIM_D23__EIM_DATA23 0x80000000 + MX6QDL_PAD_EIM_D24__EIM_DATA24 0x80000000 + MX6QDL_PAD_EIM_D25__EIM_DATA25 0x80000000 + MX6QDL_PAD_EIM_D26__EIM_DATA26 0x80000000 + MX6QDL_PAD_EIM_D27__EIM_DATA27 0x80000000 + MX6QDL_PAD_EIM_D28__EIM_DATA28 0x80000000 + MX6QDL_PAD_EIM_D29__EIM_DATA29 0x80000000 + MX6QDL_PAD_EIM_D30__EIM_DATA30 0x80000000 + MX6QDL_PAD_EIM_D31__EIM_DATA31 0x80000000 + >; + }; + }; +}; + +&ldb { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_display>; + + lvds-channel@0 { + status = "okay"; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + + display-timings { + timing0: 800x480 { + clock-frequency = <35338240>; + hactive = <800>; + vactive = <480>; + hfront-porch = <100>; + hback-porch = <100>; + hsync-len = <24>; + hsync-active = <1>; + vfront-porch = <5>; + vback-porch = <5>; + vsync-len = <3>; + vsync-active = <1>; + }; + }; + }; +}; + +&uart1 { + /* RS485 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + /* RS232 debug port */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + /* TTL internal */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + /* RS232 MDB */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usdhc2 { + /* SD card socket */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + cd-gpios = <&gpio2 2 0>; + wp-gpios = <&gpio2 3 0>; + status = "okay"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox-environment"; + reg = <0x80000 0x80000>; + }; +}; + +&usdhc4 { + /* eMMC */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index c5cc508ff..ceb993f23 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -208,6 +208,10 @@ config MACH_DFI_FS700_M60 bool "DFI i.MX6 FS700 M60 Q7 Board" select ARCH_IMX6 +config MACH_GUF_SANTARO + bool "Garz+Fricke Santaro Board" + select ARCH_IMX6 + config MACH_REALQ7 bool "DataModul i.MX6Q Real Qseven Board" select ARCH_IMX6 diff --git a/images/Makefile.imx b/images/Makefile.imx index a1e9bc41f..597e4c388 100644 --- a/images/Makefile.imx +++ b/images/Makefile.imx @@ -62,6 +62,11 @@ CFG_start_imx6_realq7.pblx.imximg = $(board)/datamodul-edm-qmx6/flash-header.imx FILE_barebox-datamodul-edm-qmx6.img = start_imx6_realq7.pblx.imximg image-$(CONFIG_MACH_REALQ7) += barebox-datamodul-edm-qmx6.img +pblx-$(CONFIG_MACH_GUF_SANTARO) += start_imx6q_guf_santaro +CFG_start_imx6q_guf_santaro.pblx.imximg = $(board)/guf-santaro/flash-header.imxcfg +FILE_barebox-guf-santaro.img = start_imx6q_guf_santaro.pblx.imximg +image-$(CONFIG_MACH_GUF_SANTARO) += barebox-guf-santaro.img + pblx-$(CONFIG_MACH_GK802) += start_imx6_gk802 CFG_start_imx6_gk802.pblx.imximg = $(board)/gk802/flash-header.imxcfg FILE_barebox-gk802.img = start_imx6_gk802.pblx.imximg From 82e69edac731131d2e942731706787ec109a5fd6 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Fri, 21 Feb 2014 18:37:57 +0100 Subject: [PATCH 15/16] ARM i.MX6: Gate clocks to graphics processing units This patch gates the clocks to GPU, IPU, and VPU units by default, significantly reducing the VDDSOC power draw while barebox is running. Signed-off-by: Philipp Zabel Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/clk-imx6.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/clk-imx6.c b/arch/arm/mach-imx/clk-imx6.c index c32b6ccb5..ac86074b6 100644 --- a/arch/arm/mach-imx/clk-imx6.c +++ b/arch/arm/mach-imx/clk-imx6.c @@ -307,12 +307,12 @@ static int imx6_ccm_probe(struct device_d *dev) clkdev_add_physbase(clks[enfc_podf], MX6_GPMI_BASE_ADDR, NULL); writel(0xffffffff, ccm_base + CCGR0); - writel(0xffffffff, ccm_base + CCGR1); + writel(0xf0ffffff, ccm_base + CCGR1); /* gate GPU3D, GPU2D */ writel(0xffffffff, ccm_base + CCGR2); - writel(0xffffffff, ccm_base + CCGR3); + writel(0x3fff0000, ccm_base + CCGR3); /* gate OpenVG, LDB, IPU1, IPU2 */ writel(0xffffffff, ccm_base + CCGR4); writel(0xffffffff, ccm_base + CCGR5); - writel(0xffffffff, ccm_base + CCGR6); + writel(0xffff3fff, ccm_base + CCGR6); /* gate VPU */ writel(0xffffffff, ccm_base + CCGR7); clk_enable(clks[pll6_enet]); From 325d844aaa39aa0072e3107f37e8e8ec4b7d4c2e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20R=C3=A9tornaz?= Date: Fri, 28 Feb 2014 17:27:59 +0100 Subject: [PATCH 16/16] ARM: i.MX31: Add support for mx31moboard board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The mx31moboard is used on the marXbot, Eyebot and Footbot robot. Signed-off-by: Philippe Rétornaz Signed-off-by: Sascha Hauer --- arch/arm/boards/Makefile | 1 + arch/arm/boards/mx31moboard/Makefile | 20 ++ arch/arm/boards/mx31moboard/env/boot/nor | 9 + arch/arm/boards/mx31moboard/env/boot/sd | 8 + arch/arm/boards/mx31moboard/env/boot/usbmsd | 8 + arch/arm/boards/mx31moboard/env/config-board | 7 + .../boards/mx31moboard/env/init/mtdparts-nor | 11 + arch/arm/boards/mx31moboard/lowlevel.c | 114 ++++++++ arch/arm/boards/mx31moboard/mx31moboard.c | 259 ++++++++++++++++++ arch/arm/boards/mx31moboard/mx31moboard.dox | 10 + arch/arm/mach-imx/Kconfig | 11 + 11 files changed, 458 insertions(+) create mode 100644 arch/arm/boards/mx31moboard/Makefile create mode 100644 arch/arm/boards/mx31moboard/env/boot/nor create mode 100644 arch/arm/boards/mx31moboard/env/boot/sd create mode 100644 arch/arm/boards/mx31moboard/env/boot/usbmsd create mode 100644 arch/arm/boards/mx31moboard/env/config-board create mode 100644 arch/arm/boards/mx31moboard/env/init/mtdparts-nor create mode 100644 arch/arm/boards/mx31moboard/lowlevel.c create mode 100644 arch/arm/boards/mx31moboard/mx31moboard.c create mode 100644 arch/arm/boards/mx31moboard/mx31moboard.dox diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index aa8da3537..8ee1bb7a0 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_MACH_MIOA701) += mioa701/ obj-$(CONFIG_MACH_MMCCPU) += mmccpu/ obj-$(CONFIG_MACH_MX23EVK) += freescale-mx23-evk/ obj-$(CONFIG_MACH_MX28EVK) += freescale-mx28-evk/ +obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard/ obj-$(CONFIG_MACH_MX6Q_ARM2) += freescale-mx6-arm2/ obj-$(CONFIG_MACH_NESO) += guf-neso/ obj-$(CONFIG_MACH_NOMADIK_8815NHK) += nhk8815/ diff --git a/arch/arm/boards/mx31moboard/Makefile b/arch/arm/boards/mx31moboard/Makefile new file mode 100644 index 000000000..83a6016b2 --- /dev/null +++ b/arch/arm/boards/mx31moboard/Makefile @@ -0,0 +1,20 @@ +# +# (C) Copyright 2007 Juergen Beisert +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# + +lwl-y += lowlevel.o +obj-y += mx31moboard.o diff --git a/arch/arm/boards/mx31moboard/env/boot/nor b/arch/arm/boards/mx31moboard/env/boot/nor new file mode 100644 index 000000000..e36655c68 --- /dev/null +++ b/arch/arm/boards/mx31moboard/env/boot/nor @@ -0,0 +1,9 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "NOR Flash" + exit +fi + +global.bootm.image="/dev/nor0.kernel" +global.linux.bootargs.dyn.root="root=/dev/mtdblock3 ro" diff --git a/arch/arm/boards/mx31moboard/env/boot/sd b/arch/arm/boards/mx31moboard/env/boot/sd new file mode 100644 index 000000000..16e734d80 --- /dev/null +++ b/arch/arm/boards/mx31moboard/env/boot/sd @@ -0,0 +1,8 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "SD Boot" + exit +fi + +boot mci0 diff --git a/arch/arm/boards/mx31moboard/env/boot/usbmsd b/arch/arm/boards/mx31moboard/env/boot/usbmsd new file mode 100644 index 000000000..6a16d3ecb --- /dev/null +++ b/arch/arm/boards/mx31moboard/env/boot/usbmsd @@ -0,0 +1,8 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "USB Boot" + exit +fi + +boot ehci0 diff --git a/arch/arm/boards/mx31moboard/env/config-board b/arch/arm/boards/mx31moboard/env/config-board new file mode 100644 index 000000000..f67b333c7 --- /dev/null +++ b/arch/arm/boards/mx31moboard/env/config-board @@ -0,0 +1,7 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.boot.default="usbmsd sd nor" +global.linux.bootargs.base="console=ttymxc0,921600" diff --git a/arch/arm/boards/mx31moboard/env/init/mtdparts-nor b/arch/arm/boards/mx31moboard/env/init/mtdparts-nor new file mode 100644 index 000000000..f09a9cc38 --- /dev/null +++ b/arch/arm/boards/mx31moboard/env/init/mtdparts-nor @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "NOR partitions" + exit +fi + +mtdparts="512k(nor0.barebox)ro,256k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)" +kernelname="physmap-flash.0" + +mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/mx31moboard/lowlevel.c b/arch/arm/boards/mx31moboard/lowlevel.c new file mode 100644 index 000000000..e9ffb74e2 --- /dev/null +++ b/arch/arm/boards/mx31moboard/lowlevel.c @@ -0,0 +1,114 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer + * (c) 2014 EPFL, Philippe Rétornaz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static noinline __noreturn void mx31moboard_startup(void) +{ + uint32_t r; + volatile int c; + + /* Enable IPU Display interface */ + writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR); + + writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR); + + for (c = 0; c < 0x4000; c++) ; + + writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR + + MX31_CCM_CCMR); + writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS, + MX31_CCM_BASE_ADDR + MX31_CCM_CCMR); + + writel(MX31_PDR0_CSI_PODF(0x1ff) | \ + MX31_PDR0_PER_PODF(7) | \ + MX31_PDR0_HSP_PODF(3) | \ + MX31_PDR0_NFC_PODF(5) | \ + MX31_PDR0_IPG_PODF(1) | \ + MX31_PDR0_MAX_PODF(3) | \ + MX31_PDR0_MCU_PODF(0), \ + MX31_CCM_BASE_ADDR + MX31_CCM_PDR0); + + writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0x33) | + IMX_PLL_MFI(0xa) | IMX_PLL_MFN(0x0C), + MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL); + writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | + IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR + + MX31_CCM_SPCTL); + + /* + * Configure IOMUXC + * Clears 0x43fa_c26c - 0x43fa_c2dc with 0, + * except 0x43fa_c278 (untouched), 0x43fa_c27c (set to 0x1000) + * and 0x43fa_c280 (untouched) + * (behaviour copied by sha, source unknown) + */ + writel(0, 0x43fac26c); /* SDCLK */ + writel(0, 0x43fac270); /* CAS */ + writel(0, 0x43fac274); /* RAS */ + + writel(0x1000, 0x43fac27c); /* CSD0 */ + + /* DQM3, DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 */ + for (r = 0x43fac284; r <= 0x43fac2dc; r += 4) + writel(0, r); + + /* Skip SDRAM initialization if we run from RAM */ + r = get_pc(); + if (r > 0x80000000 && r < 0xa0000000) + imx31_barebox_entry(0); + + writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); + writel(0x00695727, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0); + writel(0x92100000, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00); + writel(0xa2100000, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + writel(0x12344321, MX31_CSD0_BASE_ADDR); + writel(0x12344321, MX31_CSD0_BASE_ADDR); + writel(0xb2100000, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33); + writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000); + writel(0x82226080, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR); + writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); + + imx31_barebox_entry(0); + +} + +void __bare_init __naked barebox_arm_reset_vector(void) +{ + arm_cpu_lowlevel_init(); + + /* Temporary stack location in internal SRAM */ + arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 8); + + mx31moboard_startup(); +} diff --git a/arch/arm/boards/mx31moboard/mx31moboard.c b/arch/arm/boards/mx31moboard/mx31moboard.c new file mode 100644 index 000000000..2ec1f4ff8 --- /dev/null +++ b/arch/arm/boards/mx31moboard/mx31moboard.c @@ -0,0 +1,259 @@ +/* + * (C) 2007 Pengutronix, Sascha Hauer + * (C) 2014 EPFL, Philippe Rétornaz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * Board support for EPFL's, i.MX31 based CPU card + * + * Based on: + * Board support for Phytec's, i.MX31 based CPU card, called: PCM037 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6) +#define USB_RESET_B IOMUX_TO_GPIO(MX31_PIN_GPIO1_0) + +static void mx31moboard_usb_init(void) +{ + u32 tmp; + + if (!IS_ENABLED(CONFIG_USB)) + return; + + /* enable clock */ + tmp = readl(0x53f80000); + tmp |= (1 << 9); + writel(tmp, 0x53f80000); + + /* Host 2 */ + tmp = readl(MX31_IOMUXC_GPR); + tmp |= 1 << 11; /* IOMUX GPR: enable USBH2 signals */ + writel(tmp, MX31_IOMUXC_GPR); + + imx_iomux_mode(IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC)); + +#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \ + | PAD_CTL_ODE_CMOS) + imx_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG | PAD_CTL_100K_PU); + imx_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG | PAD_CTL_100K_PU); + imx_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG | PAD_CTL_100K_PU); + imx_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG | PAD_CTL_100K_PU); + imx_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */ + imx_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */ + imx_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */ + imx_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */ + imx_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */ + imx_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */ + imx_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ + imx_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ + + + gpio_request(USB_RESET_B, "usb-reset"); + gpio_direction_output(USB_RESET_B, 0); + mdelay(5); + gpio_set_value(USB_RESET_B, 1); + mdelay(10); + + gpio_request(USBH2_EN_B, "usbh2-en"); + gpio_direction_output(USBH2_EN_B, 0); + udelay(900); + gpio_set_value(USBH2_EN_B, 1); + udelay(200); + + tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600); + tmp &= ~((3 << 21) | 1); + tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20); + writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600); + + tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x584); + tmp &= ~(3 << 30); + tmp |= 2 << 30; + writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x584); + + gpio_set_value(USBH2_EN_B, 0); + + mdelay(50); + + ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x570), 1); + + /* Set to Host mode */ + tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x1a8); + writel(tmp | 0x3, MX31_USB_OTG_BASE_ADDR + 0x1a8); + +} + +static struct gpio_led mx31moboard_leds[] = { + { + .led = { + .name = "coreboard-led-0:red:running" + }, + .gpio = IOMUX_TO_GPIO(MX31_PIN_SVEN0), + }, { + .led = { + .name = "coreboard-led-1:red", + }, + .gpio = IOMUX_TO_GPIO(MX31_PIN_STX0), + }, { + .led = { + .name = "coreboard-led-2:red", + }, + .gpio = IOMUX_TO_GPIO(MX31_PIN_SRX0), + }, { + .led = { + .name = "coreboard-led-3:red", + }, + .gpio = IOMUX_TO_GPIO(MX31_PIN_SIMPD0), + }, +}; + +static void mx31moboard_add_leds(void) +{ + int i; + + if (!IS_ENABLED(CONFIG_LED_GPIO)) + return; + + for (i = 0; i < ARRAY_SIZE(mx31moboard_leds); i++) { + led_gpio_register(&mx31moboard_leds[i]); + led_set(&mx31moboard_leds[i].led, 0); + } + + led_set_trigger(LED_TRIGGER_HEARTBEAT, &mx31moboard_leds[0].led); +} + +static int mx31moboard_mmu_init(void) +{ + l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000); + + return 0; +} +postmmu_initcall(mx31moboard_mmu_init); + +static const struct devfs_partition mx31moboard_nor0_partitions[] = { + { + .offset = 0, + .size = SZ_512K, + .flags = DEVFS_PARTITION_FIXED, + .name = "self0", + }, { + .offset = DEVFS_PARTITION_APPEND, + .size = SZ_256K, + .name = "env0", + }, { + /* Sentinel */ + } +}; + +static int mx31moboard_devices_init(void) +{ + /* CS0: Nor Flash */ + imx31_setup_weimcs(0, 0x0000CC03, 0xa0330D01, 0x00220800); + + /* + * Up to 32MiB NOR type flash, connected to + * CS line 0, data width is 16 bit + */ + add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX31_CS0_BASE_ADDR, SZ_32M, 0); + + imx31_add_mmc0(NULL); + + /* + * Create partitions that should be + * not touched by any regular user + */ + devfs_create_partitions("nor0", mx31moboard_nor0_partitions); + protect_file("/dev/env0", 1); + + mx31moboard_usb_init(); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, + MX31_USB_HS2_BASE_ADDR, NULL); + + mx31moboard_add_leds(); + + armlinux_set_architecture(MACH_TYPE_MX31MOBOARD); + + return 0; +} + +device_initcall(mx31moboard_devices_init); + +static unsigned int mx31moboard_iomux[] = { + /* UART1 */ + MX31_PIN_RXD1__RXD1, + MX31_PIN_TXD1__TXD1, + MX31_PIN_CTS1__GPIO2_7, + /* SDHC1 */ + MX31_PIN_SD1_DATA3__SD1_DATA3, + MX31_PIN_SD1_DATA2__SD1_DATA2, + MX31_PIN_SD1_DATA1__SD1_DATA1, + MX31_PIN_SD1_DATA0__SD1_DATA0, + MX31_PIN_SD1_CLK__SD1_CLK, + MX31_PIN_SD1_CMD__SD1_CMD, + MX31_PIN_ATA_CS0__GPIO3_26, MX31_PIN_ATA_CS1__GPIO3_27, + /* LEDS */ + MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1, + MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3, +}; + +static int imx31_console_init(void) +{ + imx_iomux_setup_multiple_pins(mx31moboard_iomux, + ARRAY_SIZE(mx31moboard_iomux)); + + gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack"); + gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0); + + barebox_set_model("EPFL mx31moboard"); + barebox_set_hostname("mx31moboard"); + + imx31_add_uart0(); + + return 0; +} + +console_initcall(imx31_console_init); diff --git a/arch/arm/boards/mx31moboard/mx31moboard.dox b/arch/arm/boards/mx31moboard/mx31moboard.dox new file mode 100644 index 000000000..41c8bbb82 --- /dev/null +++ b/arch/arm/boards/mx31moboard/mx31moboard.dox @@ -0,0 +1,10 @@ +/** @page mx31moboard EPFL mx31moboard + +This CPU card is based on a Freescale i.MX31 CPU. The card is shipped with: + +- 32MiB NOR type Flash Memory +- 128MiB LPDDR +- A least one SD slot +- A least one USB host (H2) + +*/ diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index ceb993f23..baa316422 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -14,6 +14,7 @@ config ARCH_TEXT_BASE default 0xa7f00000 if MACH_PCA100 default 0xa0000000 if MACH_PCM038 default 0x87f00000 if MACH_PCM037 + default 0x87f00000 if MACH_MX31MOBOARD default 0x87f00000 if MACH_PCM043 default 0x08f80000 if MACH_SCB9328 default 0xa7e00000 if MACH_NESO @@ -359,6 +360,16 @@ config MACH_PCM037 Say Y here if you are using Phytec's phyCORE-i.MX31 (pcm037) equipped with a Freescale i.MX31 Processor +config MACH_MX31MOBOARD + bool "mx31moboard-i.MX31" + select ARCH_IMX31 + select USB_ULPI if USB + select HAVE_DEFAULT_ENVIRONMENT_NEW + select ARCH_HAS_L2X0 + help + Say Y here if you are using EPFL mx31moboard board equipped + with a Freescale i.MX31 Processor + # ---------------------------------------------------------- comment "i.MX35 Boards"