010-OMAP-addbase

[Patch 10/17] U-Boot-V2:ARM:OMAP3: Add support for OMAP and Cortex A8

This patch adds support for OMAP3 platforms. Mainly to setup the infrastructure.
ARMV7 requires a different I/D cache cleanup code which is introduced in this patch

Signed-off-by: Nishanth Menon<x0nishan@ti.com>

arch/arm/Kconfig

@@ -49,6 +49,9 @@ config ARM920T
 config ARM926EJS
 	bool
 
+config ARMCORTEXA8
+	bool
+
 # i.MX1, i.MXL, i.MX27 and i.MX31 are quite similar and thus
 # handled in one arch
 config ARCH_IMX
@@ -76,6 +79,10 @@ config ARCH_NETX
 	bool
 	select ARM926EJS
 
+config ARCH_OMAP
+	bool
+# ARM versions used varies on based on OMAP versions
+
 choice
 	prompt "Select your board"
 
@@ -137,6 +144,12 @@ config MACH_PCM037
 	  Say Y here if your are using Phytec's phyCORE-i.MX31 (pcm037) equipped
 	  with a Freescale i.MX31 Processor
 
+config MACH_OMAP
+	bool "Texas Instruments' OMAP based platforms"
+	select ARCH_OMAP
+	help
+	  Say Y if you are using Texas Instrument's OMAP based platforms
+
 endchoice
 
 config IMX_CLKO
@@ -146,8 +159,9 @@ config IMX_CLKO
 	  The i.MX SoCs have a Pin which can output different reference frequencies.
 	  Say y here if you want to have the clko command which lets you select the
 	  frequency to output on this pin.
-	  
+
 source arch/arm/mach-netx/Kconfig
+source arch/arm/mach-omap/Kconfig
 
 menu "Arm specific settings         "
 
@@ -170,6 +184,13 @@ config INITRD_TAG
 	  If you want to start a 2.6 kernel and use an
 	  initrd image say y here.
 
+config ARMCORTEXA8_DCACHE_SKIP
+	bool "Skip DCache Invlidate"
+	depends on ARMCORTEXA8
+	default n
+	help
+	  If your architecture configuration uses some other method of disabling caches, enable this
+	  So that the D-Cache invalidation logic is skipped
 endmenu
 
 source common/Kconfig

arch/arm/Makefile

@@ -5,6 +5,7 @@ CPPFLAGS += -D__ARM__ -fno-strict-aliasing
 machine-$(CONFIG_ARCH_IMX)	   := imx
 machine-$(CONFIG_ARCH_NETX)	   := netx
 machine-$(CONFIG_ARCH_AT91RM9200)  := at91rm9200
+machine-$(CONFIG_ARCH_OMAP)        := omap
 board-$(CONFIG_MACH_MX1ADS)	   := mx1ads
 board-$(CONFIG_MACH_ECO920)	   := eco920
 board-$(CONFIG_MACH_SCB9328)	   := scb9328
@@ -12,6 +13,7 @@ board-$(CONFIG_MACH_PCM038)	   := pcm038
 board-$(CONFIG_MACH_IMX27ADS)	   := imx27ads
 board-$(CONFIG_MACH_NXDB500)       := netx
 board-$(CONFIG_MACH_PCM037)	   := pcm037
+board-$(CONFIG_MACH_OMAP)	   := omap
 # FIXME "cpu-y" never used on ARM!
 cpu-$(CONFIG_ARM920T)              := arm920t
 cpu-$(CONFIG_ARM926EJS)            := arm926ejs
@@ -70,6 +72,10 @@ archprepare: maketools
 PHONY += maketools
 maketools: include/asm-arm/.arch
 
+# Add architecture specific flags
+ifeq ($(CONFIG_ARMCORTEXA8),y)
+CPPFLAGS += -march=armv7a
+endif
 
 ifneq ($(board-y),)
 BOARD  := board/$(board-y)/

arch/arm/cpu/Makefile

@@ -6,4 +6,5 @@ obj-y += interrupts.o
 #
 obj-$(CONFIG_ARM920T) += start-arm.o
 obj-$(CONFIG_ARM926EJS) += start-arm.o
+obj-$(CONFIG_ARMCORTEXA8) += start-arm.o
 obj-$(CONFIG_ARCH_IMX31) += start-arm.o

arch/arm/cpu/start-arm.S

@@ -136,12 +136,66 @@ reset:
 #ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT
 	bl arch_init_lowlevel
 #endif
+
+#ifdef CONFIG_ARMCORTEXA8
+	/*
+	 * Invalidate v7 I/D caches
+	 */
+	mov     r0, #0                 /* set up for MCR */
+	mcr     p15, 0, r0, c8, c7, 0  /* invalidate TLBs */
+	mcr     p15, 0, r0, c7, c5, 0  /* invalidate icache */
+	/* Invalidate all Dcaches */
+#ifndef CONFIG_ARMCORTEXA8_DCACHE_SKIP
+	/* If Arch specific ROM code SMI handling does not exist */
+	mrc	p15, 1, r0, c0, c0, 1	/* read clidr */
+	ands	r3, r0, #0x7000000	/* extract loc from clidr */
+	mov	r3, r3, lsr #23		/* left align loc bit field */
+	beq	finished_inval	/* if loc is 0, then no need to clean */
+	mov	r10, #0			/* start clean at cache level 0 */
+inval_loop1:
+	add	r2, r10, r10, lsr #1	/* work out 3x current cache level */
+	mov	r1, r0, lsr r2	/* extract cache type bits from clidr */
+	and	r1, r1, #7	/* mask of the bits for current cache only */
+	cmp	r1, #2		/* see what cache we have at this level */
+	blt	skip_inval		/* skip if no cache, or just i-cache */
+	mcr	p15, 2, r10, c0, c0, 0	/* select current cache level in cssr */
+	isb				/* isb to sych the new cssr&csidr */
+	mrc	p15, 1, r1, c0, c0, 0	/* read the new csidr */
+	and	r2, r1, #7	  /* extract the length of the cache lines */
+	add	r2, r2, #4		/* add 4 (line length offset) */
+	ldr	r4, =0x3ff
+	ands	r4, r4, r1, lsr #3	/* find maximum number on the way size*/
+	clz	r5, r4		/* find bit position of way size increment */
+	ldr	r7, =0x7fff
+	ands	r7, r7, r1, lsr #13 /* extract max number of the index size */
+inval_loop2:
+	mov	r9, r4		/* create working copy of max way size */
+inval_loop3:
+	orr	r11, r10, r9, lsl r5  /* factor way and cache number into r11*/
+	orr	r11, r11, r7, lsl r2	/* factor index number into r11 */
+	mcr	p15, 0, r11, c7, c6, 2	/* invalidate by set/way */
+	subs	r9, r9, #1		/* decrement the way */
+	bge	inval_loop3
+	subs	r7, r7, #1		/* decrement the index */
+	bge	inval_loop2
+skip_inval:
+	add	r10, r10, #2		/* increment cache number */
+	cmp	r3, r10
+	bgt	inval_loop1
+finished_inval:
+	mov	r10, #0			/* swith back to cache level 0 */
+	mcr	p15, 2, r10, c0, c0, 0	/* select current cache level in cssr */
+	isb
+#endif /* CONFIG_ARMCORTEXA8_DCACHE_SKIP */
+
+#else
 	/*
 	 * flush v4 I/D caches
 	 */
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
 	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+#endif
 
 	/*
 	 * disable MMU stuff and caches