ARM: zynq: add clk support for zynq7000
This adds support for the clocktree on zynq7000 SoCs. The patch is based on clocks.c from the larger patch ARM: zynq: add suppport for Zynq 7000 SoC by Josh Cartwright. The driver in that patch is converted to a platform_driver and code to enable plls was added. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Steffen Trumtrar
Sascha Hauer
parent
1bb8460fc1
commit
097513b8f8
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/*
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* Copyright (c) 2013 Josh Cartwright <joshc@eso.teric.us>
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* Copyright (c) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
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*
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* Based on drivers/clk-zynq.c from Linux.
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*
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* Copyright (c) 2012 National Instruments
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*
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* Josh Cartwright <josh.cartwright@ni.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <mach/zynq7000-regs.h>
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#include <malloc.h>
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enum zynq_clks {
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dummy, ps_clk, arm_pll, ddr_pll, io_pll, uart_clk, uart0, uart1,
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cpu_clk, cpu_6x4x, cpu_3x2x, cpu_2x, cpu_1x, clks_max
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};
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enum zynq_pll_type {
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ZYNQ_PLL_ARM,
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ZYNQ_PLL_DDR,
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ZYNQ_PLL_IO,
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};
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#define PLL_STATUS_ARM_PLL_LOCK (1 << 0)
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#define PLL_STATUS_DDR_PLL_LOCK (1 << 1)
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#define PLL_STATUS_IO_PLL_LOCK (1 << 2)
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#define PLL_STATUS_ARM_PLL_STABLE (1 << 0)
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#define PLL_STATUS_DDR_PLL_STABLE (1 << 1)
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#define PLL_STATUS_IO_PLL_STABLE (1 << 2)
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#define PLL_CTRL_BYPASS_FORCE (1 << 4)
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static struct clk *clks[clks_max];
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struct zynq_pll_clk {
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struct clk clk;
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u32 pll_lock;
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void __iomem *pll_ctrl;
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};
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#define to_zynq_pll_clk(c) container_of(c, struct zynq_pll_clk, clk)
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#define PLL_CTRL_FDIV(x) (((x) >> 12) & 0x7F)
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static unsigned long zynq_pll_recalc_rate(struct clk *clk,
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unsigned long parent_rate)
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{
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struct zynq_pll_clk *pll = to_zynq_pll_clk(clk);
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return parent_rate * PLL_CTRL_FDIV(readl(pll->pll_ctrl));
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}
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static int zynq_pll_enable(struct clk *clk)
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{
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struct zynq_pll_clk *pll = to_zynq_pll_clk(clk);
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u32 val;
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int timeout = 10000;
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val = readl(pll->pll_ctrl);
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val &= ~PLL_CTRL_BYPASS_FORCE;
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writel(val, pll->pll_ctrl);
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while (timeout--) {
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if (readl(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_PLL_STATUS) & pll->pll_lock)
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break;
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}
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if (!timeout)
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return -ETIMEDOUT;
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return 0;
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}
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static struct clk_ops zynq_pll_clk_ops = {
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.recalc_rate = zynq_pll_recalc_rate,
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.enable = zynq_pll_enable,
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};
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static inline struct clk *zynq_pll_clk(enum zynq_pll_type type,
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const char *name,
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void __iomem *pll_ctrl)
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{
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static const char *pll_parent = "ps_clk";
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struct zynq_pll_clk *pll;
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int ret;
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pll = xzalloc(sizeof(*pll));
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pll->pll_ctrl = pll_ctrl;
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pll->clk.ops = &zynq_pll_clk_ops;
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pll->clk.name = name;
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pll->clk.parent_names = &pll_parent;
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pll->clk.num_parents = 1;
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switch(type) {
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case ZYNQ_PLL_ARM:
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pll->pll_lock = PLL_STATUS_ARM_PLL_LOCK;
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break;
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case ZYNQ_PLL_DDR:
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pll->pll_lock = PLL_STATUS_DDR_PLL_LOCK;
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break;
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case ZYNQ_PLL_IO:
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pll->pll_lock = PLL_STATUS_IO_PLL_LOCK;
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break;
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}
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ret = clk_register(&pll->clk);
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if (ret) {
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free(pll);
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return ERR_PTR(ret);
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}
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return &pll->clk;
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}
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struct zynq_periph_clk {
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struct clk clk;
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void __iomem *clk_ctrl;
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};
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#define to_zynq_periph_clk(c) container_of(c, struct zynq_periph_clk, c)
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static const u8 periph_clk_parent_map[] = {
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0, 0, 1, 2
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};
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#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x) & 0x30) >> 4])
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#define PERIPH_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8)
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static unsigned long zynq_periph_recalc_rate(struct clk *clk,
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unsigned long parent_rate)
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{
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struct zynq_periph_clk *periph = to_zynq_periph_clk(clk);
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return parent_rate / PERIPH_CLK_CTRL_DIV(readl(periph->clk_ctrl));
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}
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static int zynq_periph_get_parent(struct clk *clk)
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{
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struct zynq_periph_clk *periph = to_zynq_periph_clk(clk);
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return PERIPH_CLK_CTRL_SRC(readl(periph->clk_ctrl));
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}
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static const struct clk_ops zynq_periph_clk_ops = {
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.recalc_rate = zynq_periph_recalc_rate,
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.get_parent = zynq_periph_get_parent,
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};
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static struct clk *zynq_periph_clk(const char *name, void __iomem *clk_ctrl)
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{
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static const char *peripheral_parents[] = {
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"io_pll",
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"arm_pll",
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"ddr_pll",
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};
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struct zynq_periph_clk *periph;
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int ret;
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periph = xzalloc(sizeof(*periph));
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periph->clk_ctrl = clk_ctrl;
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periph->clk.name = name;
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periph->clk.ops = &zynq_periph_clk_ops;
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periph->clk.parent_names = peripheral_parents;
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periph->clk.num_parents = ARRAY_SIZE(peripheral_parents);
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ret = clk_register(&periph->clk);
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if (ret) {
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free(periph);
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return ERR_PTR(ret);
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}
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return &periph->clk;
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}
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/* CPU Clock domain is modelled as a mux with 4 children subclks, whose
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* derivative rates depend on CLK_621_TRUE
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*/
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struct zynq_cpu_clk {
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struct clk clk;
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void __iomem *clk_ctrl;
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};
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#define to_zynq_cpu_clk(c) container_of(c, struct zynq_cpu_clk, c)
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static const u8 zynq_cpu_clk_parent_map[] = {
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1, 1, 2, 0
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};
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#define CPU_CLK_SRCSEL(x) (zynq_cpu_clk_parent_map[(((x) & 0x30) >> 4)])
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#define CPU_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8)
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static unsigned long zynq_cpu_clk_recalc_rate(struct clk *clk,
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unsigned long parent_rate)
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{
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struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(clk);
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return parent_rate / CPU_CLK_CTRL_DIV(readl(cpuclk->clk_ctrl));
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}
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static int zynq_cpu_clk_get_parent(struct clk *clk)
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{
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struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(clk);
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return CPU_CLK_SRCSEL(readl(cpuclk->clk_ctrl));
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}
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static const struct clk_ops zynq_cpu_clk_ops = {
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.get_parent = zynq_cpu_clk_get_parent,
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.recalc_rate = zynq_cpu_clk_recalc_rate,
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};
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static struct clk *zynq_cpu_clk(const char *name, void __iomem *clk_ctrl)
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{
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static const char *cpu_parents[] = {
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"io_pll",
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"arm_pll",
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"ddr_pll",
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};
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struct zynq_cpu_clk *cpu;
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int ret;
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cpu = xzalloc(sizeof(*cpu));
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cpu->clk_ctrl = clk_ctrl;
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cpu->clk.ops = &zynq_cpu_clk_ops;
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cpu->clk.name = name;
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cpu->clk.parent_names = cpu_parents;
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cpu->clk.num_parents = ARRAY_SIZE(cpu_parents);
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ret = clk_register(&cpu->clk);
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if (ret) {
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free(cpu);
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return ERR_PTR(ret);
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}
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return &cpu->clk;
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}
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enum zynq_cpu_subclk_which {
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CPU_SUBCLK_6X4X,
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CPU_SUBCLK_3X2X,
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CPU_SUBCLK_2X,
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CPU_SUBCLK_1X,
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};
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struct zynq_cpu_subclk {
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struct clk clk;
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void __iomem *clk_ctrl;
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void __iomem *clk_621;
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enum zynq_cpu_subclk_which which;
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};
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#define CLK_621_TRUE(x) ((x) & 1)
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#define to_zynq_cpu_subclk(c) container_of(c, struct zynq_cpu_subclk, c);
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static unsigned long zynq_cpu_subclk_recalc_rate(struct clk *clk,
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unsigned long parent_rate)
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{
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unsigned long uninitialized_var(rate);
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struct zynq_cpu_subclk *subclk;
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bool is_621;
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subclk = to_zynq_cpu_subclk(clk);
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is_621 = CLK_621_TRUE(readl(subclk->clk_621));
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switch (subclk->which) {
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case CPU_SUBCLK_6X4X:
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rate = parent_rate;
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break;
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case CPU_SUBCLK_3X2X:
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rate = parent_rate / 2;
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break;
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case CPU_SUBCLK_2X:
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rate = parent_rate / (is_621 ? 3 : 2);
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break;
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case CPU_SUBCLK_1X:
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rate = parent_rate / (is_621 ? 6 : 4);
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break;
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};
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return rate;
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}
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static int zynq_cpu_subclk_enable(struct clk *clk)
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{
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struct zynq_cpu_subclk *subclk;
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u32 tmp;
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subclk = to_zynq_cpu_subclk(clk);
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tmp = readl(subclk->clk_ctrl);
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tmp |= 1 << (24 + subclk->which);
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writel(tmp, subclk->clk_ctrl);
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return 0;
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}
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static void zynq_cpu_subclk_disable(struct clk *clk)
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{
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struct zynq_cpu_subclk *subclk;
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u32 tmp;
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subclk = to_zynq_cpu_subclk(clk);
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tmp = readl(subclk->clk_ctrl);
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tmp &= ~(1 << (24 + subclk->which));
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writel(tmp, subclk->clk_ctrl);
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}
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static const struct clk_ops zynq_cpu_subclk_ops = {
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.enable = zynq_cpu_subclk_enable,
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.disable = zynq_cpu_subclk_disable,
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.recalc_rate = zynq_cpu_subclk_recalc_rate,
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};
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static struct clk *zynq_cpu_subclk(const char *name,
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enum zynq_cpu_subclk_which which,
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void __iomem *clk_ctrl,
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void __iomem *clk_621)
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{
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static const char *subclk_parent = "cpu_clk";
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struct zynq_cpu_subclk *subclk;
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int ret;
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subclk = xzalloc(sizeof(*subclk));
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subclk->clk_ctrl = clk_ctrl;
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subclk->clk_621 = clk_621;
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subclk->which = which;
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subclk->clk.name = name;
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subclk->clk.ops = &zynq_cpu_subclk_ops;
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subclk->clk.parent_names = &subclk_parent;
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subclk->clk.num_parents = 1;
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ret = clk_register(&subclk->clk);
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if (ret) {
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free(subclk);
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return ERR_PTR(ret);
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}
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return &subclk->clk;
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}
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static int zynq_clock_probe(struct device_d *dev)
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{
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void __iomem *slcr_base;
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unsigned long ps_clk_rate = 33333330;
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slcr_base = dev_request_mem_region(dev, 0);
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if (!slcr_base)
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return -EBUSY;
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clks[ps_clk] = clk_fixed("ps_clk", ps_clk_rate);
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clks[arm_pll] = zynq_pll_clk(ZYNQ_PLL_ARM, "arm_pll", slcr_base + 0x100);
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clks[ddr_pll] = zynq_pll_clk(ZYNQ_PLL_DDR, "ddr_pll", slcr_base + 0x104);
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clks[io_pll] = zynq_pll_clk(ZYNQ_PLL_IO, "io_pll", slcr_base + 0x108);
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clks[uart_clk] = zynq_periph_clk("uart_clk", slcr_base + 0x154);
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clks[uart0] = clk_gate("uart0", "uart_clk", slcr_base + 0x154, 0);
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clks[uart1] = clk_gate("uart1", "uart_clk", slcr_base + 0x154, 1);
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clks[cpu_clk] = zynq_cpu_clk("cpu_clk", slcr_base + 0x120);
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clks[cpu_6x4x] = zynq_cpu_subclk("cpu_6x4x", CPU_SUBCLK_6X4X,
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slcr_base + 0x120, slcr_base + 0x1C4);
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clks[cpu_3x2x] = zynq_cpu_subclk("cpu_3x2x", CPU_SUBCLK_3X2X,
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slcr_base + 0x120, slcr_base + 0x1C4);
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clks[cpu_2x] = zynq_cpu_subclk("cpu_2x", CPU_SUBCLK_2X,
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slcr_base + 0x120, slcr_base + 0x1C4);
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clks[cpu_1x] = zynq_cpu_subclk("cpu_1x", CPU_SUBCLK_1X,
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slcr_base + 0x120, slcr_base + 0x1C4);
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clk_register_clkdev(clks[cpu_3x2x], NULL, "arm_smp_twd");
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clk_register_clkdev(clks[uart0], NULL, "zynq_serial0");
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clk_register_clkdev(clks[uart1], NULL, "zynq_serial1");
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clkdev_add_physbase(clks[cpu_3x2x], CORTEXA9_SCU_TIMER_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[uart1], ZYNQ_UART1_BASE_ADDR, NULL);
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return 0;
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}
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static __maybe_unused struct of_device_id zynq_clock_dt_ids[] = {
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{
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.compatible = "xlnx,zynq-clock",
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}, {
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/* sentinel */
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}
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};
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static struct driver_d zynq_clock_driver = {
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.probe = zynq_clock_probe,
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.name = "zynq-clock",
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.of_compatible = DRV_OF_COMPAT(zynq_clock_dt_ids),
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};
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static int zynq_clock_init(void)
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{
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return platform_driver_register(&zynq_clock_driver);
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}
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postcore_initcall(zynq_clock_init);
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#ifndef __ASM_MACH_CLKDEV_H
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#define __ASM_MACH_CLKDEV_H
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#define __clk_get(clk) ({ 1; })
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#define __clk_put(clk) do { } while (0)
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#endif
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