imx: Add Phytec Phycore i.MX35 aka PCM043 support
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
9a252f1ac9
commit
0cb4c4e2a5
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@ -12,7 +12,8 @@ config ARCH_TEXT_BASE
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default 0x87f00000 if MACH_PCM037
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default 0x23f00000 if MACH_AT91SAM9260_EK
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default 0x23f00000 if MACH_PM9263
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default 0x80000000 if MACH_FREESCALE_MX35_3STACK
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default 0x87f00000 if MACH_FREESCALE_MX35_3STACK
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default 0x87f00000 if MACH_PCM043
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config BOARDINFO
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default "Synertronixx scb9328" if MACH_SCB9328
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@ -23,6 +24,7 @@ config BOARDINFO
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default "Atmel 91SAM9260-EK" if MACH_AT91SAM9260_EK
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default "Ronetix PM9263" if MACH_PM9263
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default "Freescale MX35 3Stack" if MACH_FREESCALE_MX35_3STACK
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default "Phytec phyCORE-i.MX35" if MACH_PCM043
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config BOARD_LINKER_SCRIPT
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bool
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@ -50,7 +52,7 @@ config ARM926EJS
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config ARMCORTEXA8
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bool
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# i.MX1, i.MXL, i.MX27 and i.MX31 are quite similar and thus
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# i.MX1, i.MXL, i.MX27, i.MX31 and i.MX35 are quite similar and thus
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# handled in one arch
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config ARCH_IMX
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bool
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@ -134,6 +136,15 @@ config MACH_IMX27ADS
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Say Y here if you are using the Freescale i.MX27ads board equipped
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with a Freescale i.MX27 Processor
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config MACH_PCM043
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bool "phyCORE-i.MX35"
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select HAS_CFI
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select ARCH_IMX35
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select MACH_HAS_LOWLEVEL_INIT
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help
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Say Y here if you are using Phytec's phyCORE-i.MX35 (pcm043) equipped
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with a Freescale i.MX35 Processor
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config MACH_FREESCALE_MX35_3STACK
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bool "Freescale MX35 3stack"
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select HAS_CFI
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@ -18,6 +18,7 @@ board-$(CONFIG_MACH_OMAP) := omap
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board-$(CONFIG_MACH_AT91SAM9260_EK):= at91sam9260ek
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board-$(CONFIG_MACH_PM9263) := pm9263
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board-$(CONFIG_MACH_FREESCALE_MX35_3STACK) := freescale-mx35-3-stack
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board-$(CONFIG_MACH_PCM043) := pcm043
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# FIXME "cpu-y" never used on ARM!
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cpu-$(CONFIG_ARM920T) := arm920t
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@ -0,0 +1,24 @@
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#
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# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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obj-y += lowlevel_init.o
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obj-y += pcm043.o
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@ -0,0 +1,31 @@
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/*
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* (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* Definitions related to passing arguments to kernel.
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*/
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#define CONFIG_MX35_HCLK_FREQ 24000000
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#endif
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/* nothing to do here yet */
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@ -0,0 +1,36 @@
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#!/bin/sh
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if [ -z "$part" -o -z "$image" ]; then
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echo "define \$part and \$image"
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exit 1
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fi
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if [ \! -e "$part" ]; then
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echo "Partition $part does not exist"
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exit 1
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fi
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if [ $# = 1 ]; then
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image=$1
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fi
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if [ x$ip = xdhcp ]; then
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dhcp
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fi
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ping $eth0.serverip
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if [ $? -ne 0 ] ; then
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echo "update aborted"
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exit 1
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fi
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unprotect $part
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echo
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echo "erasing partition $part"
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erase $part
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echo
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echo "flashing $image to $part"
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echo
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tftp $image $part
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@ -0,0 +1,47 @@
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#!/bin/sh
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. /env/config
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if [ x$1 = xnand ]; then
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root=nand
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kernel=nand
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fi
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if [ x$1 = xnet ]; then
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root=net
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kernel=net
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fi
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if [ x$1 = xnor ]; then
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root=nor
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kernel=nor
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fi
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if [ x$ip = xdhcp ]; then
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bootargs="$bootargs ip=dhcp"
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else
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bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
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fi
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if [ x$root = xnand ]; then
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bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
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elif [ x$root = xnor ]; then
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bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2"
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else
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bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
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fi
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bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;mxc_nand:$nand_parts"
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if [ $kernel = net ]; then
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if [ x$ip = xdhcp ]; then
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dhcp
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fi
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tftp $uimage uImage || exit 1
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bootm uImage
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elif [ $kernel = nor ]; then
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bootm /dev/nor0.kernel
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else
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bootm /dev/nand0.kernel.bb
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fi
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@ -0,0 +1 @@
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nand -a /dev/nand0.*
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@ -0,0 +1,37 @@
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#!/bin/sh
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PATH=/env/bin
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export PATH
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. /env/config
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if [ -e /dev/nor0 ]; then
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addpart /dev/nor0 $nor_parts
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fi
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if [ -e /dev/nand0 ]; then
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addpart /dev/nand0 $nand_parts
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# Uh, oh, hush first expands wildcards and then starts executing
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# commands. What a bug!
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source /env/bin/hush_hack
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fi
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if [ -z $eth0.ethaddr ]; then
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while [ -z $eth0.ethaddr ]; do
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readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
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done
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echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
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fi
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echo
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echo -n "Hit any key to stop autoboot: "
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timeout -a $autoboot_timeout
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if [ $? != 0 ]; then
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echo
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echo "type update_kernel nand|nor [<imagename>] to update kernel into flash"
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echo "type update_root nand|nor [<imagename>] to update rootfs into flash"
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echo
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exit
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fi
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boot
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@ -0,0 +1,15 @@
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#!/bin/sh
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. /env/config
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image=$uimage
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if [ x$1 = xnand ]; then
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part=/dev/nand0.kernel.bb
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elif [ x$1 = xnor ]; then
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part=/dev/nor0.kernel
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else
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echo "usage: $0 nor|nand [imagename]"
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exit 1
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fi
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. /env/bin/_update $2
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@ -0,0 +1,16 @@
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#!/bin/sh
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. /env/config
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image=$uimage
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if [ x$1 = xnand ]; then
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part=/dev/nand0.root.bb
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elif [ x$1 = xnor ]; then
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part=/dev/nor0.root
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else
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echo "usage: $0 nor|nand [imagename]"
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exit 1
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fi
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. /env/bin/_update $2
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@ -0,0 +1,29 @@
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#!/bin/sh
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# can be either 'net', 'nor' or 'nand''
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kernel=net
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root=net
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uimage=uImage-pcm043
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jffs2=root-pcm043.jffs2
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autoboot_timeout=3
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nfsroot="/ptx/work/octopus/rsc/svn/oselas/bsp/phytec/phyCORE-i.MX27/OSELAS.BSP-Phytec-phyCORE-i.MX27-trunk/root"
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bootargs="console=ttymxc0,115200"
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nor_parts="256k(uboot)ro,128k(ubootenv),2048k(kernel),-(root)"
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rootpart_nor="/dev/mtdblock3"
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nand_parts="256k(uboot)ro,128k(ubootenv),2048k(kernel),-(root)"
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rootpart_nand="/dev/mtdblock7"
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# use 'dhcp' to do dhcp in uboot and in kernel
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#ip=dhcp
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# or set your networking parameters here
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eth0.ipaddr=192.168.3.11
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eth0.netmask=255.255.255.0
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#eth0.gateway=a.b.c.d
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eth0.serverip=192.168.3.10
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eth0.ethaddr=00:50:c2:8c:e6:0e
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@ -0,0 +1,233 @@
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/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/imx-pll.h>
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#include <asm/arch/esdctl.h>
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#include <asm/cache-l2x0.h>
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#define writel(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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str r1, [r0];
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#define writeb(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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strb r1, [r0];
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/* Assuming 24MHz input clock */
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#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
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#define MPCTL_PARAM_532 (IMX_PLL_PD(1) | IMX_PLL_MFD(0) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
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#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1))
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ARM_PPMRR: .word 0x40000015
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L2CACHE_PARAM: .word 0x00030024
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CCM_CCMR_W: .word 0x003F4208
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CCM_PDR0_W: .word 0x00801000
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MPCTL_PARAM_399_W: .word MPCTL_PARAM_399
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MPCTL_PARAM_532_W: .word MPCTL_PARAM_532
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PPCTL_PARAM_W: .word PPCTL_PARAM_300
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CCM_BASE_ADDR_W: .word IMX_CCM_BASE
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.globl board_init_lowlevel
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board_init_lowlevel:
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mov r10, lr
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mrc 15, 0, r1, c1, c0, 0
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// bic r1, r1, #(0x3<<21)
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bic r1, r1, #(0x3<<11)
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// bic r1, r1, #0x5
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// bic r1, r1, #(1<<3)
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mrc 15, 0, r0, c1, c0, 1
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orr r0, r0, #7
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mcr 15, 0, r0, c1, c0, 1
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orr r1, r1, #(1<<11) /* Flow prediction (Z) */
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orr r1, r1, #(1<<22) /* unaligned accesses */
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orr r1, r1, #(1<<21)
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mcr 15, 0, r1, c1, c0, 0
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mov r0, #0
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mcr 15, 0, r0, c15, c2, 4
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mov r0, #0
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mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
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mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
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mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
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/* Also setup the Peripheral Port Remap register inside the core */
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ldr r0, ARM_PPMRR /* start from AIPS 2GB region */
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mcr p15, 0, r0, c15, c2, 4
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/* L2 Cache setup / invalidation / disable
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*/
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#ifdef L2_INVAL
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/* Disable L2 cache first */
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mov r0, #IMX_L2CC_BASE
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ldr r2, [r0, #L2X0_CTRL]
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bic r2, r2, #0x1
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str r2, [r0, #L2X0_CTRL]
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/*
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* Configure L2 Cache:
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* - 128k size(16k way)
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* - 8-way associativity
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* - 0 ws TAG/VALID/DIRTY
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* - 4 ws DATA R/W
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*/
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ldr r1, [r0, #L2X0_AUX_CTRL]
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and r1, r1, #0xFE000000
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ldr r2, L2CACHE_PARAM
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orr r1, r1, r2
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str r1, [r0, #L2X0_AUX_CTRL]
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/* Workaround for DDR issue:WT*/
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ldr r1, [r0, #L2X0_DEBUG_CTRL]
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orr r1, r1, #2
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str r1, [r0, #L2X0_DEBUG_CTRL]
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/* Invalidate L2 */
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mov r1, #0x000000FF
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str r1, [r0, #L2X0_CLEAN_INV_WAY]
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L2_loop:
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/* Poll Invalidate By Way register */
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ldr r2, [r0, #L2X0_CLEAN_INV_WAY]
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cmp r2, #0
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bne L2_loop
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#endif
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/*
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* End of ARM1136 init
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*/
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ldr r0, CCM_BASE_ADDR_W
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/* default CLKO to 1/32 of the ARM core*/
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ldr r1, [r0, #CCM_COSR]
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bic r1, r1, #0x00000FF00
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bic r1, r1, #0x0000000FF
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mov r2, #0x00006C00
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add r2, r2, #0x67
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orr r1, r1, r2
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str r1, [r0, #CCM_COSR]
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ldr r2, CCM_CCMR_W
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str r2, [r0, #CCM_CCMR]
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/* check clock path */
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ldr r2, [r0, #CCM_PDR0]
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tst r2, #0x1
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ldrne r3, MPCTL_PARAM_532_W /* consumer path*/
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ldreq r3, MPCTL_PARAM_399_W /* auto path*/
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/*Set MPLL , arm clock and ahb clock*/
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str r3, [r0, #CCM_MPCTL]
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ldr r1, PPCTL_PARAM_W
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str r1, [r0, #CCM_PPCTL]
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ldr r1, [r0, #CCM_PDR0]
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orr r1, r1, #0x800000
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str r1, [r0, #CCM_PDR0]
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ldr r1, CCM_PDR0_W
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str r1, [r0, #CCM_PDR0]
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ldr r1, [r0, #CCM_CGR0]
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orr r1, r1, #0x00300000
|
||||
str r1, [r0, #CCM_CGR0]
|
||||
|
||||
ldr r1, [r0, #CCM_CGR1]
|
||||
orr r1, r1, #0x00000C00
|
||||
orr r1, r1, #0x00000003
|
||||
str r1, [r0, #CCM_CGR1]
|
||||
|
||||
/* Skip SDRAM initialization if we run from RAM */
|
||||
cmp pc, #0x80000000
|
||||
bls 1f
|
||||
cmp pc, #0x90000000
|
||||
bhi 1f
|
||||
|
||||
mov pc, lr
|
||||
|
||||
1:
|
||||
/* MDDR init, enable mDDR*/
|
||||
writel(0x00000304, ESDMISC) /* was 0x00000004 */
|
||||
|
||||
/* set timing paramters */
|
||||
writel(0x007ffc2f, ESDCFG0) /* was 0x007ffc3f */
|
||||
/* select Prechare-All mode */
|
||||
writel(0x92220000, ESDCTL0)
|
||||
/* Prechare-All */
|
||||
writel(0x12345678, IMX_SDRAM_CS0 + 0x400)
|
||||
|
||||
/* select Load-Mode-Register mode */
|
||||
writel(0xB8001000, ESDCTL0)
|
||||
/* Load reg EMR2 */
|
||||
writeb(0xda, 0x84000000)
|
||||
/* Load reg EMR3 */
|
||||
writeb(0xda, 0x86000000)
|
||||
/* Load reg EMR1 -- enable DLL */
|
||||
writeb(0xda, 0x82000400)
|
||||
/* Load reg MR -- reset DLL */
|
||||
writeb(0xda, 0x80000333)
|
||||
|
||||
/* select Prechare-All mode */
|
||||
writel(0x92220000, ESDCTL0)
|
||||
/* Prechare-All */
|
||||
writel(0x12345678, IMX_SDRAM_CS0 + 0x400)
|
||||
|
||||
/* select Manual-Refresh mode */
|
||||
writel(0xA2220000, ESDCTL0)
|
||||
/* Manual-Refresh 2 times */
|
||||
writel(0x87654321, IMX_SDRAM_CS0)
|
||||
writel(0x87654321, IMX_SDRAM_CS0)
|
||||
|
||||
/* select Load-Mode-Register mode */
|
||||
writel(0xB2220000, ESDCTL0)
|
||||
/* Load reg MR -- CL3, BL8, end DLL reset */
|
||||
writeb(0xda, 0x80000233)
|
||||
/* Load reg EMR1 -- OCD default */
|
||||
writeb(0xda, 0x82000780)
|
||||
/* Load reg EMR1 -- OCD exit */
|
||||
writeb(0xda, 0x82000400)
|
||||
|
||||
/* select normal-operation mode
|
||||
* DSIZ32-bit, BL8, COL10-bit, ROW13-bit
|
||||
* disable PWT & PRCT
|
||||
* disable Auto-Refresh */
|
||||
writel(0x82220080, ESDCTL0)
|
||||
|
||||
/* enable Auto-Refresh */
|
||||
writel(0x82228080, ESDCTL0)
|
||||
/* enable Auto-Refresh */
|
||||
writel(0x00002000, ESDCTL1)
|
||||
|
||||
mov r0, #IMX_L2CC_BASE
|
||||
ldr r1, [r0, #L2X0_AUX_CTRL]
|
||||
orr r1, r1, #0x1000
|
||||
str r1, [r0, #L2X0_AUX_CTRL]
|
||||
|
||||
mov pc, lr
|
||||
|
||||
|
|
@ -0,0 +1,157 @@
|
|||
/*
|
||||
* (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* Board support for Phytec's, i.MX35 based CPU card, called: PCM043
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <driver.h>
|
||||
#include <environment.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/armlinux.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/io.h>
|
||||
#include <partition.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/arch/imx-nand.h>
|
||||
#include <fec.h>
|
||||
|
||||
/*
|
||||
* Up to 32MiB NOR type flash, connected to
|
||||
* CS line 0, data width is 16 bit
|
||||
*/
|
||||
static struct device_d cfi_dev = {
|
||||
.name = "cfi_flash",
|
||||
.id = "nor0",
|
||||
.map_base = IMX_CS0_BASE,
|
||||
.size = 32 * 1024 * 1024, /* area size */
|
||||
};
|
||||
|
||||
static struct fec_platform_data fec_info = {
|
||||
.xcv_type = MII100,
|
||||
};
|
||||
|
||||
static struct device_d fec_dev = {
|
||||
.name = "fec_imx27",
|
||||
.id = "eth0",
|
||||
.map_base = 0x50038000,
|
||||
.platform_data = &fec_info,
|
||||
.type = DEVICE_TYPE_ETHER,
|
||||
};
|
||||
|
||||
static struct device_d sdram0_dev = {
|
||||
.name = "ram",
|
||||
.id = "ram0",
|
||||
|
||||
.map_base = IMX_SDRAM_CS0,
|
||||
.size = 128 * 1024 * 1024,
|
||||
|
||||
.type = DEVICE_TYPE_DRAM,
|
||||
};
|
||||
|
||||
struct imx_nand_platform_data nand_info = {
|
||||
.width = 1,
|
||||
.hw_ecc = 1,
|
||||
};
|
||||
|
||||
static struct device_d nand_dev = {
|
||||
.name = "imx_nand",
|
||||
.map_base = IMX_NAND_BASE,
|
||||
.platform_data = &nand_info,
|
||||
};
|
||||
|
||||
static int imx35_devices_init(void)
|
||||
{
|
||||
__REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash from pcm037*/
|
||||
__REG(CSCR_L(0)) = 0x10000d03;
|
||||
__REG(CSCR_A(0)) = 0x00720900;
|
||||
|
||||
/* setup pins for I2C1 (for EEPROM, RTC) */
|
||||
imx_gpio_mode(MUX_I2C1_CLK_I2C1_SLC);
|
||||
imx_gpio_mode(MUX_I2C1_DAT_I2C1_SDA);
|
||||
|
||||
register_device(&cfi_dev);
|
||||
|
||||
/*
|
||||
* Create partitions that should be
|
||||
* not touched by any regular user
|
||||
*/
|
||||
#ifdef CONFIG_PARTITION
|
||||
dev_add_partition(&cfi_dev, 0x00000, 0x40000, PARTITION_FIXED, "self"); /* ourself */
|
||||
dev_add_partition(&cfi_dev, 0x40000, 0x20000, PARTITION_FIXED, "env"); /* environment */
|
||||
#endif
|
||||
dev_protect(&cfi_dev, 0x20000, 0, 1);
|
||||
|
||||
register_device(&nand_dev);
|
||||
|
||||
imx_gpio_mode(MUX_FEC_TX_CLK_FEC_TX_CLK);
|
||||
imx_gpio_mode(MUX_FEC_RX_CLK_FEC_RX_CLK);
|
||||
imx_gpio_mode(MUX_FEC_RX_DV_FEC_RX_DV);
|
||||
imx_gpio_mode(MUX_FEC_COL_FEC_COL);
|
||||
imx_gpio_mode(MUX_FEC_TX_EN_FEC_TX_EN);
|
||||
imx_gpio_mode(MUX_FEC_MDC_FEC_MDC);
|
||||
imx_gpio_mode(MUX_FEC_MDIO_FEC_MDIO);
|
||||
imx_gpio_mode(MUX_FEC_TX_ERR_FEC_TX_ERR);
|
||||
imx_gpio_mode(MUX_FEC_RX_ERR_FEC_RX_ERR);
|
||||
imx_gpio_mode(MUX_FEC_CRS_FEC_CRS);
|
||||
imx_gpio_mode(MUX_FEC_RDATA0_FEC_RDATA0);
|
||||
imx_gpio_mode(MUX_FEC_TDATA0_FEC_TDATA0);
|
||||
imx_gpio_mode(MUX_FEC_RDATA1_FEC_RDATA1);
|
||||
imx_gpio_mode(MUX_FEC_TDATA1_FEC_TDATA1);
|
||||
imx_gpio_mode(MUX_FEC_RDATA2_FEC_RDATA2);
|
||||
imx_gpio_mode(MUX_FEC_TDATA2_FEC_TDATA2);
|
||||
imx_gpio_mode(MUX_FEC_RDATA3_FEC_RDATA3);
|
||||
imx_gpio_mode(MUX_FEC_TDATA3_FEC_TDATA3);
|
||||
|
||||
register_device(&fec_dev);
|
||||
|
||||
register_device(&sdram0_dev);
|
||||
|
||||
armlinux_set_bootparams((void *)0x80000100);
|
||||
armlinux_set_architecture(MACH_TYPE_PCM043);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
device_initcall(imx35_devices_init);
|
||||
|
||||
static struct device_d imx35_serial_device = {
|
||||
.name = "imx_serial",
|
||||
.id = "cs0",
|
||||
.map_base = IMX_UART1_BASE,
|
||||
.size = 16 * 1024,
|
||||
.type = DEVICE_TYPE_CONSOLE,
|
||||
};
|
||||
|
||||
static int imx35_console_init(void)
|
||||
{
|
||||
/* init gpios for serial port */
|
||||
imx_gpio_mode(MUX_RXD1_UART1_RXD_MUX);
|
||||
imx_gpio_mode(MUX_TXD1_UART1_TXD_MUX);
|
||||
imx_gpio_mode(MUX_RTS1_UART1_RTS_B);
|
||||
imx_gpio_mode(MUX_RTS1_UART1_CTS_B);
|
||||
|
||||
register_device(&imx35_serial_device);
|
||||
return 0;
|
||||
}
|
||||
|
||||
console_initcall(imx35_console_init);
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
/** @page pcm043 Phytec's phyCORE-i.MX35
|
||||
|
||||
This CPU card is based on a Freescale i.MX35 CPU. The card is shipped with:
|
||||
|
||||
|
||||
FIXME:
|
||||
- up to 64MiB NOR type Flash Memory
|
||||
- up to 2MiB static RAM
|
||||
- 64MiB NAND type Flash Memory
|
||||
- 128MiB synchronous dynamic RAM
|
||||
|
||||
|
||||
*/
|
||||
Loading…
Reference in New Issue