sysmo-bts
/
barebox
9
0
Fork 0
Code Releases Activity

video i.MX: Use regular clk_[en|dis]able functions 

This controller has no enable bit. It is always on once the
pixel clock is provided. This patch switches the driver to use
regular clk functions instead of SoC specific register hacking.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer 2012-09-29 00:49:50 +02:00
parent beda98485c
commit 0ea2ee7866
1 changed files with 5 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
drivers/video/imx.c
View File

@ -252,19 +252,9 @@ static void imxfb_enable_controller(struct fb_info *info)
struct imxfb_info *fbi = info->priv;
writel(RMCR_LCDC_EN, fbi->regs + LCDC_RMCR);
#ifdef CONFIG_ARCH_IMX21
PCCR0 |= PCCR0_PERCLK3_EN | PCCR0_HCLK_LCDC_EN;
#endif
#ifdef CONFIG_ARCH_IMX27
PCCR0 |= PCCR0_LCDC_EN;
PCCR1 |= PCCR1_HCLK_LCDC;
#endif
#ifdef CONFIG_ARCH_IMX25
writel(readl(IMX_CCM_BASE + CCM_CGCR0) | (1 << 24) | (1 << 7),
IMX_CCM_BASE + CCM_CGCR0);
writel(readl(IMX_CCM_BASE + CCM_CGCR1) | (1 << 29),
IMX_CCM_BASE + CCM_CGCR1);
#endif
clk_enable(fbi->clk);
if (fbi->enable)
fbi->enable(1);
}
@ -277,19 +267,8 @@ static void imxfb_disable_controller(struct fb_info *info)
fbi->enable(0);
writel(0, fbi->regs + LCDC_RMCR);
#ifdef CONFIG_ARCH_IMX21
PCCR0 &= ~(PCCR0_PERCLK3_EN | PCCR0_HCLK_LCDC_EN);
#endif
#ifdef CONFIG_ARCH_IMX27
PCCR0 &= ~PCCR0_LCDC_EN;
PCCR1 &= ~PCCR1_HCLK_LCDC;
#endif
#ifdef CONFIG_ARCH_IMX25
writel(readl(IMX_CCM_BASE + CCM_CGCR0) & ~((1 << 24) | (1 << 7)),
IMX_CCM_BASE + CCM_CGCR0);
writel(readl(IMX_CCM_BASE + CCM_CGCR1) & ~(1 << 29),
IMX_CCM_BASE + CCM_CGCR1);
#endif
clk_disable(fbi->clk);
}
/*
@ -541,19 +520,6 @@ static int imxfb_probe(struct device_d *dev)
if (!pdata)
return -ENODEV;
#ifdef CONFIG_ARCH_IMX21
PCCR0 &= ~(PCCR0_PERCLK3_EN | PCCR0_HCLK_LCDC_EN);
#endif
#ifdef CONFIG_ARCH_IMX27
PCCR0 &= ~PCCR0_LCDC_EN;
PCCR1 &= ~PCCR1_HCLK_LCDC;
#endif
#ifdef CONFIG_ARCH_IMX25
writel(readl(IMX_CCM_BASE + CCM_CGCR0) & ~((1 << 24) | (1 << 7)),
IMX_CCM_BASE + CCM_CGCR0);
writel(readl(IMX_CCM_BASE + CCM_CGCR1) & ~(1 << 29),
IMX_CCM_BASE + CCM_CGCR1);
#endif
if (!pdata->num_modes) {
dev_err(dev, "no modes. bailing out\n");
return -EINVAL;