video i.MX: Use regular clk_[en|dis]able functions
This controller has no enable bit. It is always on once the pixel clock is provided. This patch switches the driver to use regular clk functions instead of SoC specific register hacking. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -252,19 +252,9 @@ static void imxfb_enable_controller(struct fb_info *info)
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struct imxfb_info *fbi = info->priv;
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writel(RMCR_LCDC_EN, fbi->regs + LCDC_RMCR);
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#ifdef CONFIG_ARCH_IMX21
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PCCR0 |= PCCR0_PERCLK3_EN | PCCR0_HCLK_LCDC_EN;
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#endif
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#ifdef CONFIG_ARCH_IMX27
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PCCR0 |= PCCR0_LCDC_EN;
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PCCR1 |= PCCR1_HCLK_LCDC;
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#endif
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#ifdef CONFIG_ARCH_IMX25
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writel(readl(IMX_CCM_BASE + CCM_CGCR0) | (1 << 24) | (1 << 7),
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IMX_CCM_BASE + CCM_CGCR0);
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writel(readl(IMX_CCM_BASE + CCM_CGCR1) | (1 << 29),
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IMX_CCM_BASE + CCM_CGCR1);
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#endif
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clk_enable(fbi->clk);
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if (fbi->enable)
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fbi->enable(1);
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}
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@ -277,19 +267,8 @@ static void imxfb_disable_controller(struct fb_info *info)
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fbi->enable(0);
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writel(0, fbi->regs + LCDC_RMCR);
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#ifdef CONFIG_ARCH_IMX21
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PCCR0 &= ~(PCCR0_PERCLK3_EN | PCCR0_HCLK_LCDC_EN);
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#endif
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#ifdef CONFIG_ARCH_IMX27
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PCCR0 &= ~PCCR0_LCDC_EN;
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PCCR1 &= ~PCCR1_HCLK_LCDC;
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#endif
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#ifdef CONFIG_ARCH_IMX25
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writel(readl(IMX_CCM_BASE + CCM_CGCR0) & ~((1 << 24) | (1 << 7)),
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IMX_CCM_BASE + CCM_CGCR0);
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writel(readl(IMX_CCM_BASE + CCM_CGCR1) & ~(1 << 29),
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IMX_CCM_BASE + CCM_CGCR1);
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#endif
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clk_disable(fbi->clk);
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}
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/*
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@ -541,19 +520,6 @@ static int imxfb_probe(struct device_d *dev)
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if (!pdata)
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return -ENODEV;
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#ifdef CONFIG_ARCH_IMX21
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PCCR0 &= ~(PCCR0_PERCLK3_EN | PCCR0_HCLK_LCDC_EN);
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#endif
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#ifdef CONFIG_ARCH_IMX27
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PCCR0 &= ~PCCR0_LCDC_EN;
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PCCR1 &= ~PCCR1_HCLK_LCDC;
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#endif
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#ifdef CONFIG_ARCH_IMX25
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writel(readl(IMX_CCM_BASE + CCM_CGCR0) & ~((1 << 24) | (1 << 7)),
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IMX_CCM_BASE + CCM_CGCR0);
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writel(readl(IMX_CCM_BASE + CCM_CGCR1) & ~(1 << 29),
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IMX_CCM_BASE + CCM_CGCR1);
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#endif
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if (!pdata->num_modes) {
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dev_err(dev, "no modes. bailing out\n");
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return -EINVAL;
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