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mtd: nand: add mrvl-nand driver

The driver is taken from the Linux kernel, with the following changes :
 - all DMA removed
 - all asynchronous handling removed, including the interrupt handler,
   and the asynchronous state handling
 - pxa armada support removed

Most the kernel structure was kept, to ease up future fixes integration
from the kernel driver.

The driver is tested on a pxa3xx system development
board (aka. zylonite), and reading, writing, erasing, and bad block
management were tested.

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Robert Jarzmik 2015-01-10 23:04:09 +01:00 committed by Sascha Hauer
parent 9b847df7a1
commit 0ebe45422a
4 changed files with 1107 additions and 0 deletions

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@ -97,6 +97,13 @@ config NAND_ORION
help
Support for the Orion NAND controller, present in Kirkwood SoCs.
config NAND_MRVL_NFC
bool
prompt "Marvell NAND driver"
depends on ARCH_PXA3XX
help
Support for the PXA3xx NAND controller, present in pxa3xx SoCs.
config NAND_ATMEL
bool
prompt "Atmel (AT91SAM9xxx) NAND driver"

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@ -11,6 +11,7 @@ obj-$(CONFIG_NAND_IMX) += nand_imx.o
obj-$(CONFIG_NAND_IMX_BBM) += nand_imx_bbm.o
obj-$(CONFIG_NAND_OMAP_GPMC) += nand_omap_gpmc.o nand_omap_bch_decoder.o
obj-$(CONFIG_NAND_ORION) += nand_orion.o
obj-$(CONFIG_NAND_MRVL_NFC) += nand_mrvl_nfc.o
obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
obj-$(CONFIG_NAND_S3C24XX) += nand_s3c24xx.o
pbl-$(CONFIG_NAND_S3C24XX) += nand_s3c24xx.o

File diff suppressed because it is too large Load Diff

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@ -0,0 +1,79 @@
/*
* Copyright (C) 2014 Robert Jarzmik
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Taken from linux kernel mostly.
*/
#ifndef __MRVL_NAND_H
#define __MRVL_NAND_H
struct mrvl_nand_timing {
uint16_t id; /* NAND id code (READID) */
unsigned int tCH; /* Enable signal hold time */
unsigned int tCS; /* Enable signal setup time */
unsigned int tWH; /* ND_nWE high duration */
unsigned int tWP; /* ND_nWE pulse time */
unsigned int tRH; /* ND_nRE high duration */
unsigned int tRP; /* ND_nRE pulse width */
unsigned int tR; /* ND_nWE high to ND_nRE low for read */
unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */
unsigned int tAR; /* ND_ALE low to ND_nRE low delay */
};
struct mrvl_nand_flash {
char *name;
uint32_t chip_id;
unsigned int page_per_block; /* Pages per block (PG_PER_BLK) */
unsigned int page_size; /* Page size in bytes (PAGE_SZ) */
unsigned int flash_width; /* Flash memory width (DWIDTH_M) */
unsigned int dfc_width; /* Flash controller width (DWIDTH_C) */
unsigned int num_blocks; /* Number of physical blocks in Flash */
struct mrvl_nand_timing *timing; /* NAND Flash timing */
};
/*
* Current pxa3xx_nand controller has two chip select which
* both be workable.
*
* Notice should be taken that:
* When you want to use this feature, you should not enable the
* keep configuration feature, for two chip select could be
* attached with different nand chip. The different page size
* and timing requirement make the keep configuration impossible.
*/
/* The max num of chip select current support */
#define NUM_CHIP_SELECT (2)
struct mrvl_nand_platform_data {
/* the data flash bus is shared between the Static Memory
* Controller and the Data Flash Controller, the arbiter
* controls the ownership of the bus
*/
int dwidth_c;
int dwidth_m;
/* allow platform code to keep OBM/bootloader defined NFC config */
int keep_config;
/* indicate how many chip selects will be used */
int num_cs;
/* use an flash-based bad block table */
bool flash_bbt;
/* requested ECC strength and ECC step size */
int ecc_strength, ecc_step_size;
const struct mtd_partition *parts[NUM_CHIP_SELECT];
unsigned int nr_parts[NUM_CHIP_SELECT];
const struct mrvl_nand_flash *flash;
size_t num_flash;
};
extern void mrvl_set_nand_info(struct mrvl_nand_platform_data *info);
#endif /* __MRVL_NAND_H */