mtd: nand: add mrvl-nand driver
The driver is taken from the Linux kernel, with the following changes : - all DMA removed - all asynchronous handling removed, including the interrupt handler, and the asynchronous state handling - pxa armada support removed Most the kernel structure was kept, to ease up future fixes integration from the kernel driver. The driver is tested on a pxa3xx system development board (aka. zylonite), and reading, writing, erasing, and bad block management were tested. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -97,6 +97,13 @@ config NAND_ORION
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help
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Support for the Orion NAND controller, present in Kirkwood SoCs.
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config NAND_MRVL_NFC
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bool
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prompt "Marvell NAND driver"
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depends on ARCH_PXA3XX
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help
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Support for the PXA3xx NAND controller, present in pxa3xx SoCs.
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config NAND_ATMEL
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bool
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prompt "Atmel (AT91SAM9xxx) NAND driver"
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@ -11,6 +11,7 @@ obj-$(CONFIG_NAND_IMX) += nand_imx.o
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obj-$(CONFIG_NAND_IMX_BBM) += nand_imx_bbm.o
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obj-$(CONFIG_NAND_OMAP_GPMC) += nand_omap_gpmc.o nand_omap_bch_decoder.o
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obj-$(CONFIG_NAND_ORION) += nand_orion.o
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obj-$(CONFIG_NAND_MRVL_NFC) += nand_mrvl_nfc.o
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obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
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obj-$(CONFIG_NAND_S3C24XX) += nand_s3c24xx.o
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pbl-$(CONFIG_NAND_S3C24XX) += nand_s3c24xx.o
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,79 @@
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/*
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* Copyright (C) 2014 Robert Jarzmik
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Taken from linux kernel mostly.
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*/
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#ifndef __MRVL_NAND_H
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#define __MRVL_NAND_H
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struct mrvl_nand_timing {
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uint16_t id; /* NAND id code (READID) */
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unsigned int tCH; /* Enable signal hold time */
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unsigned int tCS; /* Enable signal setup time */
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unsigned int tWH; /* ND_nWE high duration */
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unsigned int tWP; /* ND_nWE pulse time */
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unsigned int tRH; /* ND_nRE high duration */
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unsigned int tRP; /* ND_nRE pulse width */
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unsigned int tR; /* ND_nWE high to ND_nRE low for read */
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unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */
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unsigned int tAR; /* ND_ALE low to ND_nRE low delay */
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};
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struct mrvl_nand_flash {
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char *name;
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uint32_t chip_id;
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unsigned int page_per_block; /* Pages per block (PG_PER_BLK) */
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unsigned int page_size; /* Page size in bytes (PAGE_SZ) */
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unsigned int flash_width; /* Flash memory width (DWIDTH_M) */
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unsigned int dfc_width; /* Flash controller width (DWIDTH_C) */
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unsigned int num_blocks; /* Number of physical blocks in Flash */
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struct mrvl_nand_timing *timing; /* NAND Flash timing */
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};
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/*
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* Current pxa3xx_nand controller has two chip select which
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* both be workable.
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*
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* Notice should be taken that:
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* When you want to use this feature, you should not enable the
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* keep configuration feature, for two chip select could be
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* attached with different nand chip. The different page size
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* and timing requirement make the keep configuration impossible.
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*/
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/* The max num of chip select current support */
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#define NUM_CHIP_SELECT (2)
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struct mrvl_nand_platform_data {
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/* the data flash bus is shared between the Static Memory
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* Controller and the Data Flash Controller, the arbiter
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* controls the ownership of the bus
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*/
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int dwidth_c;
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int dwidth_m;
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/* allow platform code to keep OBM/bootloader defined NFC config */
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int keep_config;
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/* indicate how many chip selects will be used */
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int num_cs;
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/* use an flash-based bad block table */
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bool flash_bbt;
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/* requested ECC strength and ECC step size */
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int ecc_strength, ecc_step_size;
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const struct mtd_partition *parts[NUM_CHIP_SELECT];
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unsigned int nr_parts[NUM_CHIP_SELECT];
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const struct mrvl_nand_flash *flash;
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size_t num_flash;
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};
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extern void mrvl_set_nand_info(struct mrvl_nand_platform_data *info);
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#endif /* __MRVL_NAND_H */
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