Merge branch 'for-next/iim'
This commit is contained in:
Sascha Hauer
commit
1022dfecfb
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@ -26,34 +26,52 @@
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#include <malloc.h>
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#include <of.h>
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#include <io.h>
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#include <regulator.h>
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#include <linux/err.h>
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#include <mach/iim.h>
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#include <mach/imx51-regs.h>
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#include <mach/imx53-regs.h>
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#include <mach/clock-imx51_53.h>
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#define DRIVERNAME "imx_iim"
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#define IIM_NUM_BANKS 8
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static int iim_write_enable;
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static int iim_sense_enable;
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struct iim_priv;
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struct iim_bank {
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struct cdev cdev;
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void __iomem *bankbase;
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int bank;
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struct iim_priv *iim;
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};
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struct iim_priv {
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struct cdev cdev;
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struct device_d dev;
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void __iomem *base;
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void __iomem *bankbase;
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int bank;
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int banksize;
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struct iim_bank *bank[IIM_NUM_BANKS];
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int write_enable;
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int sense_enable;
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void (*supply)(int enable);
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struct regulator *fuse_supply;
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};
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static int do_fuse_sense(void __iomem *reg_base, unsigned int bank,
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unsigned int row)
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struct imx_iim_drvdata {
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void (*supply)(int enable);
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};
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static struct iim_priv *imx_iim;
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static int imx_iim_fuse_sense(struct iim_bank *bank, unsigned int row)
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{
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struct iim_priv *iim = bank->iim;
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void __iomem *reg_base = iim->base;
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u8 err, stat;
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if (bank > 7) {
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printf("%s: invalid bank number\n", __func__);
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return -EINVAL;
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}
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if (row > 255) {
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printf("%s: invalid row index\n", __func__);
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dev_err(&iim->dev, "%s: invalid row index\n", __func__);
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return -EINVAL;
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}
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@ -62,7 +80,7 @@ static int do_fuse_sense(void __iomem *reg_base, unsigned int bank,
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writeb(0xfe, reg_base + IIM_ERR);
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/* upper and lower address halves */
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writeb((bank << 3) | (row >> 5), reg_base + IIM_UA);
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writeb((bank->bank << 3) | (row >> 5), reg_base + IIM_UA);
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writeb((row << 3) & 0xf8, reg_base + IIM_LA);
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/* start fuse sensing */
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@ -77,7 +95,7 @@ static int do_fuse_sense(void __iomem *reg_base, unsigned int bank,
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err = readb(reg_base + IIM_ERR);
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if (err) {
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printf("%s: sense error (0x%02x)\n", __func__, err);
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dev_err(&iim->dev, "sense error (0x%02x)\n", err);
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return -EIO;
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}
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@ -88,40 +106,51 @@ static ssize_t imx_iim_cdev_read(struct cdev *cdev, void *buf, size_t count,
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loff_t offset, ulong flags)
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{
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ulong size, i;
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struct iim_priv *priv = cdev->priv;
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struct iim_bank *bank = container_of(cdev, struct iim_bank, cdev);
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size = min((loff_t)count, priv->banksize - offset);
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if (iim_sense_enable) {
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size = min((loff_t)count, 32 - offset);
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if (bank->iim->sense_enable) {
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for (i = 0; i < size; i++) {
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int row_val;
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row_val = do_fuse_sense(priv->base,
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priv->bank, offset + i);
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row_val = imx_iim_fuse_sense(bank, offset + i);
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if (row_val < 0)
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return row_val;
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((u8 *)buf)[i] = (u8)row_val;
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}
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} else {
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for (i = 0; i < size; i++)
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((u8 *)buf)[i] = ((u8 *)priv->bankbase)[(offset+i)*4];
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((u8 *)buf)[i] = ((u8 *)bank->bankbase)[(offset+i)*4];
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}
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return size;
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}
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static int do_fuse_blow(void __iomem *reg_base, unsigned int bank,
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unsigned int row, u8 value)
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int imx_iim_read(unsigned int banknum, int offset, void *buf, int count)
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{
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struct iim_priv *iim = imx_iim;
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struct iim_bank *bank;
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if (!imx_iim)
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return -ENODEV;
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if (banknum > IIM_NUM_BANKS)
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return -EINVAL;
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bank = iim->bank[banknum];
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return imx_iim_cdev_read(&bank->cdev, buf, count, offset, 0);
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}
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static int imx_iim_fuse_blow_one(struct iim_bank *bank, unsigned int row, u8 value)
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{
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struct iim_priv *iim = bank->iim;
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void __iomem *reg_base = iim->base;
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int bit, ret = 0;
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u8 err, stat;
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if (bank > 7) {
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printf("%s: invalid bank number\n", __func__);
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return -EINVAL;
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}
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if (row > 255) {
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printf("%s: invalid row index\n", __func__);
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dev_err(&iim->dev, "%s: invalid row index\n", __func__);
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return -EINVAL;
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}
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@ -133,7 +162,7 @@ static int do_fuse_blow(void __iomem *reg_base, unsigned int bank,
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writeb(0xaa, reg_base + IIM_PREG_P);
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/* upper half address register */
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writeb((bank << 3) | (row >> 5), reg_base + IIM_UA);
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writeb((bank->bank << 3) | (row >> 5), reg_base + IIM_UA);
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for (bit = 0; bit < 8; bit++) {
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if (((value >> bit) & 1) == 0)
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@ -155,8 +184,8 @@ static int do_fuse_blow(void __iomem *reg_base, unsigned int bank,
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err = readb(reg_base + IIM_ERR);
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if (err) {
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printf("%s: bank %u, row %u, bit %d program error "
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"(0x%02x)\n", __func__, bank, row, bit,
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dev_err(&iim->dev, "bank %u, row %u, bit %d program error "
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"(0x%02x)\n", bank->bank, row, bit,
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err);
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ret = -EIO;
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goto out;
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@ -169,26 +198,56 @@ out:
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return ret;
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}
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static int imx_iim_fuse_blow(struct iim_bank *bank, unsigned offset, const void *buf,
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unsigned size)
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{
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struct iim_priv *iim = bank->iim;
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int ret, i;
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if (IS_ERR(iim->fuse_supply)) {
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iim->fuse_supply = regulator_get(iim->dev.parent, "vdd-fuse");
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dev_info(iim->dev.parent, "regul: %p\n", iim->fuse_supply);
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if (IS_ERR(iim->fuse_supply))
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return PTR_ERR(iim->fuse_supply);
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}
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ret = regulator_enable(iim->fuse_supply);
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if (ret < 0)
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return ret;
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if (iim->supply)
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iim->supply(1);
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for (i = 0; i < size; i++) {
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ret = imx_iim_fuse_blow_one(bank, offset + i, ((u8 *)buf)[i]);
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if (ret < 0)
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goto err_out;
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}
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if (iim->supply)
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iim->supply(0);
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ret = 0;
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err_out:
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regulator_disable(iim->fuse_supply);
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return ret;
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}
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static ssize_t imx_iim_cdev_write(struct cdev *cdev, const void *buf, size_t count,
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loff_t offset, ulong flags)
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{
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ulong size, i;
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struct iim_priv *priv = cdev->priv;
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struct iim_bank *bank = container_of(cdev, struct iim_bank, cdev);
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size = min((loff_t)count, priv->banksize - offset);
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size = min((loff_t)count, 32 - offset);
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if (IS_ENABLED(CONFIG_IMX_IIM_FUSE_BLOW) && iim_write_enable) {
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for (i = 0; i < size; i++) {
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int ret;
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ret = do_fuse_blow(priv->base, priv->bank,
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offset + i, ((u8 *)buf)[i]);
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if (ret < 0)
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return ret;
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}
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if (IS_ENABLED(CONFIG_IMX_IIM_FUSE_BLOW) && bank->iim->write_enable) {
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return imx_iim_fuse_blow(bank, offset, buf, size);
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} else {
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for (i = 0; i < size; i++)
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((u8 *)priv->bankbase)[(offset+i)*4] = ((u8 *)buf)[i];
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((u8 *)bank->bankbase)[(offset+i)*4] = ((u8 *)buf)[i];
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}
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return size;
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@ -200,43 +259,93 @@ static struct file_operations imx_iim_ops = {
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.lseek = dev_lseek_default,
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};
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static int imx_iim_add_bank(struct device_d *dev, void __iomem *base, int num)
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static int imx_iim_add_bank(struct iim_priv *iim, int num)
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{
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struct iim_priv *priv;
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struct iim_bank *bank;
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struct cdev *cdev;
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priv = xzalloc(sizeof (*priv));
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bank = xzalloc(sizeof (*bank));
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priv->base = base;
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priv->bankbase = priv->base + 0x800 + 0x400 * num;
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priv->bank = num;
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priv->banksize = 32;
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cdev = &priv->cdev;
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cdev->dev = dev;
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bank->bankbase = iim->base + 0x800 + 0x400 * num;
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bank->bank = num;
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bank->iim = iim;
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cdev = &bank->cdev;
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cdev->ops = &imx_iim_ops;
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cdev->priv = priv;
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cdev->size = 32;
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cdev->name = asprintf(DRIVERNAME "_bank%d", num);
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if (cdev->name == NULL)
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return -ENOMEM;
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iim->bank[num] = bank;
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return devfs_create(cdev);
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}
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#if IS_ENABLED(CONFIG_OFDEVICE)
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#define MAC_BYTES 6
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struct imx_iim_mac {
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struct iim_bank *bank;
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int offset;
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u8 ethaddr[MAC_BYTES];
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};
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static int imx_iim_get_mac(struct param_d *param, void *priv)
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{
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struct imx_iim_mac *iimmac = priv;
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struct iim_bank *bank = iimmac->bank;
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int ret;
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ret = imx_iim_cdev_read(&bank->cdev, iimmac->ethaddr, MAC_BYTES, iimmac->offset, 0);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int imx_iim_set_mac(struct param_d *param, void *priv)
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{
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struct imx_iim_mac *iimmac = priv;
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struct iim_bank *bank = iimmac->bank;
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int ret;
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ret = imx_iim_cdev_write(&bank->cdev, iimmac->ethaddr, MAC_BYTES, iimmac->offset, 0);
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if (ret < 0)
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return ret;
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return 0;
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}
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static void imx_iim_add_mac_param(struct iim_priv *iim, int macnum, int bank, int offset)
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{
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struct imx_iim_mac *iimmac;
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char *name;
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iimmac = xzalloc(sizeof(*iimmac));
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iimmac->offset = offset;
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iimmac->bank = iim->bank[bank];
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name = asprintf("ethaddr%d", macnum);
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dev_add_param_mac(&iim->dev, name, imx_iim_set_mac,
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imx_iim_get_mac, iimmac->ethaddr, iimmac);
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free(name);
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}
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/*
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* a single MAC address reference has the form
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* <&phandle iim-bank-no offset>, so three cells
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*/
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#define MAC_ADDRESS_PROPLEN (3 * sizeof(__be32))
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static void imx_iim_init_dt(struct device_d *dev)
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static void imx_iim_init_dt(struct device_d *dev, struct iim_priv *iim)
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{
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char mac[6];
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const __be32 *prop;
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struct device_node *node = dev->device_node;
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int len, ret;
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int len, ret, macnum = 0;
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if (!node)
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return;
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@ -262,41 +371,112 @@ static void imx_iim_init_dt(struct device_d *dev)
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dev_err(dev, "cannot read: %s\n", strerror(-ret));
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}
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imx_iim_add_mac_param(iim, macnum, bank, offset);
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macnum++;
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|
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len -= MAC_ADDRESS_PROPLEN;
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}
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}
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#else
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static inline void imx_iim_init_dt(struct device_d *dev)
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static inline void imx_iim_init_dt(struct device_d *dev, struct iim_priv *iim)
|
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{
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}
|
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#endif
|
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|
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static int imx_iim_probe(struct device_d *dev)
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{
|
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int i;
|
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void __iomem *base;
|
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struct iim_priv *iim;
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int i, ret;
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struct imx_iim_drvdata *drvdata = NULL;
|
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|
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base = dev_request_mem_region(dev, 0);
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if (imx_iim)
|
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return -EBUSY;
|
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|
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for (i = 0; i < 8; i++) {
|
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imx_iim_add_bank(dev, base, i);
|
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iim = xzalloc(sizeof(*iim));
|
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|
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dev_get_drvdata(dev, (unsigned long *)&drvdata);
|
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|
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if (drvdata && drvdata->supply)
|
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iim->supply = drvdata->supply;
|
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|
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imx_iim = iim;
|
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|
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strcpy(iim->dev.name, "iim");
|
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iim->dev.parent = dev;
|
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iim->dev.id = DEVICE_ID_SINGLE;
|
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ret = register_device(&iim->dev);
|
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if (ret)
|
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return ret;
|
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|
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iim->fuse_supply = ERR_PTR(-ENODEV);
|
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|
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iim->base = dev_request_mem_region(dev, 0);
|
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if (!iim->base)
|
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return -EBUSY;
|
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|
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for (i = 0; i < IIM_NUM_BANKS; i++) {
|
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ret = imx_iim_add_bank(iim, i);
|
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if (ret)
|
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return ret;
|
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}
|
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|
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imx_iim_init_dt(dev);
|
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imx_iim_init_dt(dev, iim);
|
||||
|
||||
if (IS_ENABLED(CONFIG_IMX_IIM_FUSE_BLOW))
|
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dev_add_param_bool(dev, "permanent_write_enable",
|
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NULL, NULL, &iim_write_enable, NULL);
|
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dev_add_param_bool(&iim->dev, "permanent_write_enable",
|
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NULL, NULL, &iim->write_enable, NULL);
|
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|
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dev_add_param_bool(dev, "explicit_sense_enable",
|
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NULL, NULL, &iim_sense_enable, NULL);
|
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dev_add_param_bool(&iim->dev, "explicit_sense_enable",
|
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NULL, NULL, &iim->sense_enable, NULL);
|
||||
|
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return 0;
|
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}
|
||||
|
||||
static void imx5_iim_supply(void __iomem *ccm_base, int enable)
|
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{
|
||||
uint32_t val;
|
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|
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val = readl(ccm_base + MX5_CCM_CGPR);
|
||||
|
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if (enable)
|
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val |= 1 << 4;
|
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else
|
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val &= ~(1 << 4);
|
||||
|
||||
writel(val, ccm_base + MX5_CCM_CGPR);
|
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}
|
||||
|
||||
static void imx51_iim_supply(int enable)
|
||||
{
|
||||
imx5_iim_supply((void __iomem *)MX51_CCM_BASE_ADDR, enable);
|
||||
}
|
||||
|
||||
static void imx53_iim_supply(int enable)
|
||||
{
|
||||
imx5_iim_supply((void __iomem *)MX53_CCM_BASE_ADDR, enable);
|
||||
}
|
||||
|
||||
static struct imx_iim_drvdata imx27_drvdata = {
|
||||
};
|
||||
|
||||
static struct imx_iim_drvdata imx51_drvdata = {
|
||||
.supply = imx51_iim_supply,
|
||||
};
|
||||
|
||||
static struct imx_iim_drvdata imx53_drvdata = {
|
||||
.supply = imx53_iim_supply,
|
||||
};
|
||||
|
||||
static __maybe_unused struct of_device_id imx_iim_dt_ids[] = {
|
||||
{
|
||||
.compatible = "fsl,imx53-iim",
|
||||
.data = (unsigned long)&imx53_drvdata,
|
||||
}, {
|
||||
.compatible = "fsl,imx51-iim",
|
||||
.data = (unsigned long)&imx51_drvdata,
|
||||
}, {
|
||||
.compatible = "fsl,imx27-iim",
|
||||
.data = (unsigned long)&imx27_drvdata,
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
|
|
@ -315,21 +495,3 @@ static int imx_iim_init(void)
|
|||
return 0;
|
||||
}
|
||||
coredevice_initcall(imx_iim_init);
|
||||
|
||||
int imx_iim_read(unsigned int bank, int offset, void *buf, int count)
|
||||
{
|
||||
struct cdev *cdev;
|
||||
char *name = asprintf(DRIVERNAME "_bank%d", bank);
|
||||
int ret;
|
||||
|
||||
cdev = cdev_open(name, O_RDONLY);
|
||||
if (!cdev)
|
||||
return -ENODEV;
|
||||
|
||||
ret = cdev_read(cdev, buf, count, offset, 0);
|
||||
|
||||
cdev_close(cdev);
|
||||
free(name);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue