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ARM: dts: imx: share pad macro names between imx6q and imx6dl 

Based on the same commit in the Kernel:

| commit 828b1716459d00b3d57d4309d25a8d1ea241116a
| Author: Shawn Guo <shawn.guo@linaro.org>
| Date:   Thu Jul 11 13:58:36 2013 +0800
|
| ARM: dts: imx: share pad macro names between imx6q and imx6dl
|
| The imx6q and imx6dl are two pin-to-pin compatible SoCs.  The same board
| design can work with either chip plugged into the socket, e.g. sabresd
| and sabreauto boards.
|
| We currently define pin groups in imx6q.dtsi and imx6dl.dtsi
| respectively because the pad macro names are different between two
| chips.  This brings a maintenance burden on having the same label point
| to the same pin group defined in two places.
|
| The patch replaces prefix MX6Q_ and MX6DL_ with MX6QDL_ for both SoCs
| pad macro names.  Then the pin groups becomes completely common between
| imx6q and imx6dl and can just be moved into imx6qdl.dtsi, so that the
| long term maintenance of imx6q/dt pin settings becomes easier.
|
| Unfortunately, the change brings some dramatic diff stat, but it's all
| about DTS file, and the ultimate net diff stat is good.
|
| Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer 2013-08-06 11:43:38 +02:00
parent 15ee30138f
commit 11dcfd13b9
15 changed files with 2597 additions and 2939 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
arch/arm/dts/imx6dl-mba6x.dts
View File

@ -33,9 +33,9 @@
gpiobuttons {
pinctrl_gpiobuttons_1: gpiogrp-1 {
fsl,pins = <
MX6DL_PAD_GPIO_17__GPIO7_IO12 0x80000000
MX6DL_PAD_GPIO_18__GPIO7_IO13 0x80000000
MX6DL_PAD_GPIO_8__GPIO1_IO08 0x80000000
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000
>;
};
};
@ -43,18 +43,18 @@
hog {
pinctrl_hog: hoggrp-1 {
fsl,pins = <
MX6DL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 /* FEC phy reset */
MX6DL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* usdhc2 CD */
MX6DL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* usdhc2 WP */
MX6DL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* eCSPI1 SS1 */
MX6DL_PAD_NANDF_RB0__GPIO6_IO10 0x80000000 /* PMIC irq */
MX6DL_PAD_EIM_D22__GPIO3_IO22 0x80000000
MX6DL_PAD_SD1_DAT3__PWM1_OUT 0x80000000
MX6DL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* beeper (1 = on) */
MX6DL_PAD_GPIO_16__GPIO7_IO11 0x80000000 /* LCD.PWR_EN */
MX6DL_PAD_GPIO_7__GPIO1_IO07 0x80000000 /* LCD.RESET */
MX6DL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* LCD.BLT_EN */
MX6DL_PAD_DI0_PIN4__GPIO4_IO20 0x80000000 /* LCD.CONTRAST */
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 /* FEC phy reset */
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* usdhc2 CD */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* usdhc2 WP */
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* eCSPI1 SS1 */
MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x80000000 /* PMIC irq */
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x80000000
MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* beeper (1 = on) */
MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x80000000 /* LCD.PWR_EN */
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x80000000 /* LCD.RESET */
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* LCD.BLT_EN */
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x80000000 /* LCD.CONTRAST */
>;
};
};

2138
arch/arm/dts/imx6dl-pinfunc.h
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File diff suppressed because it is too large Load Diff

84
arch/arm/dts/imx6dl-tqma6s.dtsi
View File

@ -16,8 +16,8 @@
can1 {
pinctrl_can1_1: can1grp-1 {
fsl,pins = <
MX6DL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
>;
};
};
@ -25,8 +25,8 @@
can2 {
pinctrl_can2_1: can2grp-1 {
fsl,pins = <
MX6DL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
MX6DL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
>;
};
};
@ -34,34 +34,34 @@
disp0 {
pinctrl_disp0_ipu1: disp0grp-1 {
fsl,pins = <
MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x80000000
MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x80000000
MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x80000000
MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x80000000
MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x80000000
MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x80000000
MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x80000000
MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x80000000
MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x80000000
MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x80000000
MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x80000000
MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x80000000
MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x80000000
MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x80000000
MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x80000000
MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x80000000
MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x80000000
MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x80000000
MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x80000000
MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x80000000
MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x80000000
MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x80000000
MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x80000000
MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x80000000
MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x80000000
MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x80000000
MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x80000000
MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x80000000
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x80000000
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x80000000
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x80000000
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x80000000
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x80000000
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x80000000
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x80000000
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x80000000
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x80000000
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x80000000
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x80000000
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x80000000
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x80000000
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x80000000
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x80000000
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x80000000
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x80000000
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x80000000
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x80000000
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x80000000
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x80000000
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x80000000
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x80000000
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x80000000
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x80000000
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x80000000
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x80000000
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x80000000
>;
};
};
@ -69,8 +69,8 @@
i2c3 {
pinctrl_i2c3_2: i2c3grp-2 {
fsl,pins = <
MX6DL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6DL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
};
@ -78,8 +78,8 @@
uart2 {
pinctrl_uart2_2: uart2grp-2 {
fsl,pins = <
MX6DL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
MX6DL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
>;
};
};
@ -87,12 +87,12 @@
usdhc2 {
pinctrl_usdhc2_tqma6x: usdhc2grp-tqma6x {
fsl,pins = <
MX6DL_PAD_SD2_CMD__SD2_CMD 0x000070f0
MX6DL_PAD_SD2_CLK__SD2_CLK 0x000070f0
MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x000070f0
MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x000070f0
MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x000070f0
MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x000070f0
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x000070f0
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x000070f0
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x000070f0
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x000070f0
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x000070f0
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x000070f0
>;
};
};

356
arch/arm/dts/imx6dl.dtsi
View File

@ -8,8 +8,8 @@
*
*/
#include "imx6qdl.dtsi"
#include "imx6dl-pinfunc.h"
#include "imx6qdl.dtsi"
/ {
cpus {
@ -35,360 +35,6 @@
aips1: aips-bus@02000000 {
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6dl-iomuxc";
reg = <0x020e0000 0x4000>;
audmux {
pinctrl_audmux_1: audmux-1 {
fsl,pins = <
MX6DL_PAD_SD2_DAT0__AUD4_RXD 0x80000000
MX6DL_PAD_SD2_DAT3__AUD4_TXC 0x80000000
MX6DL_PAD_SD2_DAT2__AUD4_TXD 0x80000000
MX6DL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
>;
};
pinctrl_audmux_2: audmux-2 {
fsl,pins = <
MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
>;
};
};
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
>;
};
pinctrl_ecspi1_2: ecspi1grp-2 {
fsl,pins = <
MX6DL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
MX6DL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
MX6DL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
>;
};
};
ecspi3 {
pinctrl_ecspi3_1: ecspi3grp-1 {
fsl,pins = <
MX6DL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
MX6DL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
MX6DL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
>;
};
};
enet {
pinctrl_enet_1: enetgrp-1 {
fsl,pins = <
MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
pinctrl_enet_2: enetgrp-2 {
fsl,pins = <
MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
>;
};
pinctrl_enet_3: enetgrp-3 {
fsl,pins = <
MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6DL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
>;
};
};
gpmi-nand {
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1
>;
};
};
i2c1 {
pinctrl_i2c1_1: i2c1grp-1 {
fsl,pins = <
MX6DL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6DL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c1_2: i2c1grp-2 {
fsl,pins = <
MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>;
};
};
i2c2 {
pinctrl_i2c2_1: i2c2grp-1 {
fsl,pins = <
MX6DL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
MX6DL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
>;
};
};
i2c3 {
pinctrl_i2c3_1: i2c3grp-1 {
fsl,pins = <
MX6DL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
MX6DL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
>;
};
};
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
};
uart2 {
pinctrl_uart2_1: uart2grp-1 {
fsl,pins = <
MX6DL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
MX6DL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
>;
};
};
uart4 {
pinctrl_uart4_1: uart4grp-1 {
fsl,pins = <
MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
};
usbotg {
pinctrl_usbotg_1: usbotggrp-1 {
fsl,pins = <
MX6DL_PAD_GPIO_1__USB_OTG_ID 0x17059
>;
};
pinctrl_usbotg_2: usbotggrp-2 {
fsl,pins = <
MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
>;
};
};
usdhc2 {
pinctrl_usdhc2_1: usdhc2grp-1 {
fsl,pins = <
MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
>;
};
pinctrl_usdhc2_2: usdhc2grp-2 {
fsl,pins = <
MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
};
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = <
MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
pinctrl_usdhc3_2: usdhc3grp-2 {
fsl,pins = <
MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
};
usdhc4 {
pinctrl_usdhc4_1: usdhc4grp-1 {
fsl,pins = <
MX6DL_PAD_SD4_CMD__SD4_CMD 0x17059
MX6DL_PAD_SD4_CLK__SD4_CLK 0x10059
MX6DL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6DL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6DL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6DL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6DL_PAD_SD4_DAT4__SD4_DATA4 0x17059
MX6DL_PAD_SD4_DAT5__SD4_DATA5 0x17059
MX6DL_PAD_SD4_DAT6__SD4_DATA6 0x17059
MX6DL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>;
};
pinctrl_usdhc4_2: usdhc4grp-2 {
fsl,pins = <
MX6DL_PAD_SD4_CMD__SD4_CMD 0x17059
MX6DL_PAD_SD4_CLK__SD4_CLK 0x10059
MX6DL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6DL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6DL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6DL_PAD_SD4_DAT3__SD4_DATA3 0x17059
>;
};
};
weim {
pinctrl_weim_cs0_1: weim_cs0grp-1 {
fsl,pins = <
MX6DL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
>;
};
pinctrl_weim_nor_1: weim_norgrp-1 {
fsl,pins = <
MX6DL_PAD_EIM_OE__EIM_OE_B 0xb0b1
MX6DL_PAD_EIM_RW__EIM_RW 0xb0b1
MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
/* data */
MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
/* address */
MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
MX6DL_PAD_EIM_DA15__EIM_AD15 0xb0b1
MX6DL_PAD_EIM_DA14__EIM_AD14 0xb0b1
MX6DL_PAD_EIM_DA13__EIM_AD13 0xb0b1
MX6DL_PAD_EIM_DA12__EIM_AD12 0xb0b1
MX6DL_PAD_EIM_DA11__EIM_AD11 0xb0b1
MX6DL_PAD_EIM_DA10__EIM_AD10 0xb0b1
MX6DL_PAD_EIM_DA9__EIM_AD09 0xb0b1
MX6DL_PAD_EIM_DA8__EIM_AD08 0xb0b1
MX6DL_PAD_EIM_DA7__EIM_AD07 0xb0b1
MX6DL_PAD_EIM_DA6__EIM_AD06 0xb0b1
MX6DL_PAD_EIM_DA5__EIM_AD05 0xb0b1
MX6DL_PAD_EIM_DA4__EIM_AD04 0xb0b1
MX6DL_PAD_EIM_DA3__EIM_AD03 0xb0b1
MX6DL_PAD_EIM_DA2__EIM_AD02 0xb0b1
MX6DL_PAD_EIM_DA1__EIM_AD01 0xb0b1
MX6DL_PAD_EIM_DA0__EIM_AD00 0xb0b1
>;
};
};
};
pxp: pxp@020f0000 {

24
arch/arm/dts/imx6q-dmo-realq7.dts
View File

@ -272,8 +272,8 @@
hog {
pinctrl_hog: hoggrp-1 {
fsl,pins = <
MX6Q_PAD_EIM_A16__GPIO2_IO22 0x80000000
MX6Q_PAD_EIM_A17__GPIO2_IO21 0x80000000
MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000
MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000
>;
};
};
@ -281,8 +281,8 @@
i2c2 {
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
MX6Q_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
};
@ -290,8 +290,8 @@
uart {
pinctrl_uart1_2: uart1grp-2 {
fsl,pins = <
MX6Q_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
MX6Q_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
>;
};
};
@ -299,7 +299,7 @@
pfuze {
pinctrl_pfuze_1: pfuze100grp1 {
fsl,pins = <
MX6Q_PAD_EIM_D20__GPIO3_IO20 0x198c0
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x198c0
>;
};
};
@ -307,7 +307,7 @@
stmpe_1 {
pinctrl_stmpe_1_1: stmpe1grp-1 {
fsl,pins = <
MX6Q_PAD_EIM_D30__GPIO3_IO30 0x80000000
MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000
>;
};
};
@ -315,7 +315,7 @@
stmpe_2 {
pinctrl_stmpe_2_1: stmpe2grp-1 {
fsl,pins = <
MX6Q_PAD_EIM_A25__GPIO5_IO02 0x80000000
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
>;
};
};
@ -323,9 +323,9 @@
ecspi5 {
pinctrl_ecspi_5_1: ecspi5rp-1 {
fsl,pins = <
MX6Q_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000
MX6Q_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000
MX6Q_PAD_SD2_DAT3__GPIO1_IO12 0x80000000 /* cs0: m25p80 */
MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000
MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000
MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x80000000 /* cs0: m25p80 */
>;
};
};

12
arch/arm/dts/imx6q-gk802.dts
View File

@ -75,9 +75,9 @@
pinctrl_hog: hoggrp {
fsl,pins = <
/* Recovery button, active-low */
MX6Q_PAD_EIM_D16__GPIO3_IO16 0x100b1
MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x100b1
/* RTL8192CU enable GPIO, active-low */
MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
>;
};
};
@ -85,8 +85,8 @@
i2c2 {
pinctrl_i2c2_gk802: i2c2grp-1 {
fsl,pins = <
MX6Q_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6Q_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
};
@ -94,8 +94,8 @@
i2c3 {
pinctrl_i2c3_gk802: i2c3grp-1 {
fsl,pins = <
MX6Q_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6Q_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
>;
};
};

28
arch/arm/dts/imx6q-mba6x.dts
View File

@ -33,9 +33,9 @@
gpiobuttons {
pinctrl_gpiobuttons_1: gpiogrp-1 {
fsl,pins = <
MX6Q_PAD_GPIO_17__GPIO7_IO12 0x80000000
MX6Q_PAD_GPIO_18__GPIO7_IO13 0x80000000
MX6Q_PAD_GPIO_8__GPIO1_IO08 0x80000000
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000
>;
};
};
@ -43,17 +43,17 @@
hog {
pinctrl_hog: hoggrp-1 {
fsl,pins = <
MX6Q_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 /* FEC phy reset */
MX6Q_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* usdhc2 CD */
MX6Q_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* usdhc2 WP */
MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* eCSPI1 SS1 */
MX6Q_PAD_NANDF_RB0__GPIO6_IO10 0x80000000 /* PMIC irq */
MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000
MX6Q_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* beeper (1 = on) */
MX6Q_PAD_GPIO_16__GPIO7_IO11 0x80000000 /* LCD.PWR_EN */
MX6Q_PAD_GPIO_7__GPIO1_IO07 0x80000000 /* LCD.RESET */
MX6Q_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* LCD.BLT_EN */
MX6Q_PAD_DI0_PIN4__GPIO4_IO20 0x80000000 /* LCD.CONTRAST */
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 /* FEC phy reset */
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* usdhc2 CD */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* usdhc2 WP */
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* eCSPI1 SS1 */
MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x80000000 /* PMIC irq */
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* beeper (1 = on) */
MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x80000000 /* LCD.PWR_EN */
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x80000000 /* LCD.RESET */
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* LCD.BLT_EN */
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x80000000 /* LCD.CONTRAST */
>;
};
};

8
arch/arm/dts/imx6q-phytec-pfla02.dtsi
View File

@ -41,8 +41,8 @@
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000
MX6Q_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
>;
};
};
@ -50,8 +50,8 @@
pfla02 {
pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 {
fsl,pins = <
MX6Q_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
>;
};
};

2050
arch/arm/dts/imx6q-pinfunc.h
View File

File diff suppressed because it is too large Load Diff

16
arch/arm/dts/imx6q-sabrelite.dts
View File

@ -95,14 +95,14 @@
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x80000000
MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x80000000
MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000
MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000
MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000
MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
MX6Q_PAD_GPIO_0__CCM_CLKO1 0x80000000
MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000
MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000
>;
};
};

12
arch/arm/dts/imx6q-sabresd.dts
View File

@ -31,12 +31,12 @@
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6Q_PAD_GPIO_4__GPIO1_IO04 0x80000000
MX6Q_PAD_GPIO_5__GPIO1_IO05 0x80000000
MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x80000000
MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000
MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000
MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
>;
};
};

140
arch/arm/dts/imx6q-tqma6q.dtsi
View File

@ -16,8 +16,8 @@
can1 {
pinctrl_can1_1: can1grp-1 {
fsl,pins = <
MX6Q_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
>;
};
};
@ -25,8 +25,8 @@
can2 {
pinctrl_can2_1: can2grp-1 {
fsl,pins = <
MX6Q_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
MX6Q_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
>;
};
};
@ -34,67 +34,67 @@
disp0 {
pinctrl_disp0_ipu1: disp0grp-1 {
fsl,pins = <
MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x80000000
MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x80000000
MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x80000000
MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x80000000
MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x80000000
MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x80000000
MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x80000000
MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x80000000
MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x80000000
MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x80000000
MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x80000000
MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x80000000
MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x80000000
MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x80000000
MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x80000000
MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x80000000
MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x80000000
MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x80000000
MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x80000000
MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x80000000
MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x80000000
MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x80000000
MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x80000000
MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x80000000
MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x80000000
MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x80000000
MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x80000000
MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x80000000
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x80000000
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x80000000
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x80000000
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x80000000
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x80000000
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x80000000
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x80000000
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x80000000
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x80000000
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x80000000
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x80000000
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x80000000
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x80000000
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x80000000
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x80000000
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x80000000
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x80000000
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x80000000
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x80000000
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x80000000
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x80000000
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x80000000
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x80000000
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x80000000
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x80000000
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x80000000
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x80000000
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x80000000
>;
};
pinctrl_disp0_ipu2: disp0grp-2 {
fsl,pins = <
MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x80000000
MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x80000000
MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x80000000
MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x80000000
MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x80000000
MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x80000000
MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x80000000
MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x80000000
MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x80000000
MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x80000000
MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x80000000
MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x80000000
MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x80000000
MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x80000000
MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x80000000
MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x80000000
MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x80000000
MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x80000000
MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x80000000
MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x80000000
MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x80000000
MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x80000000
MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x80000000
MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x80000000
MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x80000000
MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x80000000
MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x80000000
MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x80000000
MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x80000000
MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x80000000
MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x80000000
MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x80000000
MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x80000000
MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x80000000
MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x80000000
MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x80000000
MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x80000000
MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x80000000
MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x80000000
MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x80000000
MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x80000000
MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x80000000
MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x80000000
MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x80000000
MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x80000000
MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x80000000
MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x80000000
MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x80000000
MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x80000000
MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x80000000
MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x80000000
MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x80000000
MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x80000000
MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x80000000
MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x80000000
MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x80000000
>;
};
};
@ -102,8 +102,8 @@
i2c3 {
pinctrl_i2c3_2: i2c3grp-2 {
fsl,pins = <
MX6Q_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6Q_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
};
@ -111,8 +111,8 @@
uart2 {
pinctrl_uart2_2: uart2grp-2 {
fsl,pins = <
MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
>;
};
};
@ -120,12 +120,12 @@
usdhc2 {
pinctrl_usdhc2_tqma6x: usdhc2grp-tqma6x {
fsl,pins = <
MX6Q_PAD_SD2_CMD__SD2_CMD 0x000070f0
MX6Q_PAD_SD2_CLK__SD2_CLK 0x000070f0
MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x000070f0
MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x000070f0
MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x000070f0
MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x000070f0
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x000070f0
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x000070f0
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x000070f0
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x000070f0
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x000070f0
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x000070f0
>;
};
};

34
arch/arm/dts/imx6q-tqma6x.dts
View File

@ -218,8 +218,8 @@
can1 {
pinctrl_can1_1: can1grp-1 {
fsl,pins = <
MX6Q_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
>;
};
};
@ -227,8 +227,8 @@
can2 {
pinctrl_can2_1: can2grp-1 {
fsl,pins = <
MX6Q_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
MX6Q_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
>;
};
};
@ -236,12 +236,12 @@
hog {
pinctrl_hog: hoggrp-1 {
fsl,pins = <
MX6Q_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 /* FEC phy reset */
MX6Q_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* usdhc2 CD */
MX6Q_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* usdhc2 WP */
MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* eCSPI1 SS1 */
MX6Q_PAD_NANDF_RB0__GPIO6_IO10 0x80000000 /* PMIC irq */
MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 /* FEC phy reset */
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* usdhc2 CD */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* usdhc2 WP */
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* eCSPI1 SS1 */
MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x80000000 /* PMIC irq */
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
>;
};
};
@ -249,8 +249,8 @@
i2c3 {
pinctrl_i2c3_2: i2c3grp-2 {
fsl,pins = <
MX6Q_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6Q_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
};
@ -258,8 +258,8 @@
uart2 {
pinctrl_uart2_2: uart2grp-2 {
fsl,pins = <
MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
>;
};
};
@ -267,9 +267,9 @@
gpiobuttons {
pinctrl_gpiobuttons_1: gpiogrp-1 {
fsl,pins = <
MX6Q_PAD_GPIO_17__GPIO7_IO12 0x80000000
MX6Q_PAD_GPIO_18__GPIO7_IO13 0x80000000
MX6Q_PAD_GPIO_8__GPIO1_IO08 0x80000000
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000
>;
};
};

301
arch/arm/dts/imx6q.dtsi
View File

@ -8,8 +8,8 @@
*
*/
#include "imx6qdl.dtsi"
#include "imx6q-pinfunc.h"
#include "imx6qdl.dtsi"
/ {
cpus {
@ -73,305 +73,6 @@
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6q-iomuxc";
reg = <0x020e0000 0x4000>;
/* shared pinctrl settings */
audmux {
pinctrl_audmux_1: audmux-1 {
fsl,pins = <
MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x80000000
MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x80000000
MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x80000000
MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
>;
};
pinctrl_audmux_2: audmux-2 {
fsl,pins = <
MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
>;
};
};
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
>;
};
pinctrl_ecspi1_2: ecspi1grp-2 {
fsl,pins = <
MX6Q_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
>;
};
};
ecspi3 {
pinctrl_ecspi3_1: ecspi3grp-1 {
fsl,pins = <
MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
>;
};
};
enet {
pinctrl_enet_1: enetgrp-1 {
fsl,pins = <
MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
pinctrl_enet_2: enetgrp-2 {
fsl,pins = <
MX6Q_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
MX6Q_PAD_KEY_COL2__ENET_MDC 0x1b0b0
MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
>;
};
pinctrl_enet_3: enetgrp-3 {
fsl,pins = <
MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
>;
};
};
gpmi-nand {
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1
MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1
>;
};
};
i2c1 {
pinctrl_i2c1_1: i2c1grp-1 {
fsl,pins = <
MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c1_2: i2c1grp-2 {
fsl,pins = <
MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>;
};
};
i2c2 {
pinctrl_i2c2_1: i2c2grp-1 {
fsl,pins = <
MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
>;
};
};
i2c3 {
pinctrl_i2c3_1: i2c3grp-1 {
fsl,pins = <
MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
>;
};
};
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
};
uart2 {
pinctrl_uart2_1: uart2grp-1 {
fsl,pins = <
MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
>;
};
};
uart4 {
pinctrl_uart4_1: uart4grp-1 {
fsl,pins = <
MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
};
usbotg {
pinctrl_usbotg_1: usbotggrp-1 {
fsl,pins = <
MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059
>;
};
pinctrl_usbotg_2: usbotggrp-2 {
fsl,pins = <
MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
>;
};
};
usdhc2 {
pinctrl_usdhc2_1: usdhc2grp-1 {
fsl,pins = <
MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059
MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059
MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059
MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
>;
};
pinctrl_usdhc2_2: usdhc2grp-2 {
fsl,pins = <
MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
};
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = <
MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
pinctrl_usdhc3_2: usdhc3grp-2 {
fsl,pins = <
MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
};
usdhc4 {
pinctrl_usdhc4_1: usdhc4grp-1 {
fsl,pins = <
MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059
MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059
MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059
MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059
>;
};
pinctrl_usdhc4_2: usdhc4grp-2 {
fsl,pins = <
MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
>;
};
};
};
};

303
arch/arm/dts/imx6qdl.dtsi
View File

@ -548,6 +548,309 @@
reg = <0x020e0000 0x38>;
};
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
reg = <0x020e0000 0x4000>;
/* shared pinctrl settings */
audmux {
pinctrl_audmux_1: audmux-1 {
fsl,pins = <
MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000
MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
>;
};
pinctrl_audmux_2: audmux-2 {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
>;
};
};
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
>;
};
pinctrl_ecspi1_2: ecspi1grp-2 {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
>;
};
};
ecspi3 {
pinctrl_ecspi3_1: ecspi3grp-1 {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
>;
};
};
enet {
pinctrl_enet_1: enetgrp-1 {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
pinctrl_enet_2: enetgrp-2 {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
>;
};
pinctrl_enet_3: enetgrp-3 {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
>;
};
};
gpmi-nand {
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
>;
};
};
i2c1 {
pinctrl_i2c1_1: i2c1grp-1 {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c1_2: i2c1grp-2 {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>;
};
};
i2c2 {
pinctrl_i2c2_1: i2c2grp-1 {
fsl,pins = <
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
>;
};
};
i2c3 {
pinctrl_i2c3_1: i2c3grp-1 {
fsl,pins = <
MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
>;
};
};
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
};
uart2 {
pinctrl_uart2_1: uart2grp-1 {
fsl,pins = <
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
>;
};
};
uart4 {
pinctrl_uart4_1: uart4grp-1 {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
};
usbotg {
pinctrl_usbotg_1: usbotggrp-1 {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
>;
};
pinctrl_usbotg_2: usbotggrp-2 {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
>;
};
};
usdhc2 {
pinctrl_usdhc2_1: usdhc2grp-1 {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
>;
};
pinctrl_usdhc2_2: usdhc2grp-2 {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
};
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
pinctrl_usdhc3_2: usdhc3grp-2 {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
};
usdhc4 {
pinctrl_usdhc4_1: usdhc4grp-1 {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>;
};
pinctrl_usdhc4_2: usdhc4grp-2 {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
>;
};
};
};
ldb: ldb@020e0008 {
#address-cells = <1>;
#size-cells = <0>;