diff --git a/arch/arm/lib/u-boot.lds.S b/arch/arm/lib/u-boot.lds.S index fe844421d..a47828157 100644 --- a/arch/arm/lib/u-boot.lds.S +++ b/arch/arm/lib/u-boot.lds.S @@ -31,6 +31,8 @@ SECTIONS { . = TEXT_BASE; + PRE_IMAGE + . = ALIGN(4); .text : { diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 519c45b7e..40f9855a3 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -10,6 +10,12 @@ config ARCH_IMX1 select ARCH_IMX select ARM920T +config ARCH_IMX25 + bool + select ARCH_IMX + select ARM926EJS + select ARCH_HAS_FEC_IMX + config ARCH_IMX21 bool select ARCH_IMX diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index a4a2527d8..f6e03b171 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -1,5 +1,6 @@ obj-y += clocksource.o obj-$(CONFIG_ARCH_IMX1) += speed-imx1.o gpio.o +obj-$(CONFIG_ARCH_IMX25) += speed-imx25.o iomux-v3.o obj-$(CONFIG_ARCH_IMX21) += speed-imx21.o gpio.o imx21.o obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o gpio.o imx27.o obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o iomux-v2.o diff --git a/arch/arm/mach-imx/speed-imx25.c b/arch/arm/mach-imx/speed-imx25.c new file mode 100644 index 000000000..d17fe6ba3 --- /dev/null +++ b/arch/arm/mach-imx/speed-imx25.c @@ -0,0 +1,101 @@ +#include +#include +#include +#include +#include + +unsigned long imx_get_mpllclk(void) +{ + ulong mpctl = readl(IMX_CCM_BASE + CCM_MPCTL); + return imx_decode_pll(mpctl, CONFIG_MX35_HCLK_FREQ); +} + +unsigned long imx_get_upllclk(void) +{ + ulong ppctl = readl(IMX_CCM_BASE + CCM_UPCTL); + return imx_decode_pll(ppctl, CONFIG_MX35_HCLK_FREQ); +} + +unsigned long imx_get_armclk(void) +{ + unsigned long rate, cctl; + + cctl = readl(IMX_CCM_BASE + CCM_CCTL); + rate = imx_get_mpllclk(); + + if (cctl & (1 << 14)) { + rate *= 3; + rate >>= 2; + } + + return rate / ((cctl >> 30) + 1); +} + +unsigned long imx_get_ahbclk(void) +{ + ulong cctl = readl(IMX_CCM_BASE + CCM_CCTL); + return imx_get_armclk() / (((cctl >> 28) & 0x3) + 1); +} + +unsigned long imx_get_ipgclk(void) +{ + return imx_get_ahbclk() / 2; +} + +unsigned long imx_get_gptclk(void) +{ + return imx_get_ipgclk(); +} + +unsigned long imx_get_perclk(int per) +{ + ulong ofs = (per & 0x3) * 8; + ulong reg = per & ~0x3; + ulong val = (readl(IMX_CCM_BASE + CCM_PCDR0 + reg) >> ofs) & 0x3f; + ulong fref; + + if (readl(IMX_CCM_BASE + 0x64) & (1 << per)) + fref = imx_get_upllclk(); + else + fref = imx_get_ipgclk(); + + return fref / (val + 1); +} + +unsigned long imx_get_perclk_(int per) +{ + ulong ofs = (per & 0x3) * 8; + ulong reg = per & ~0x3; + ulong val = (readl(IMX_CCM_BASE + CCM_PCDR0 + reg) >> ofs) & 0x3f; + ulong fref; + + if (readl(IMX_CCM_BASE + 0x64) & (1 << per)) + fref = imx_get_upllclk(); + else + fref = imx_get_ipgclk(); + + return fref / (val + 1); +} + +unsigned long imx_get_uartclk(void) +{ + return imx_get_perclk(15); +} + +unsigned long imx_get_fecclk(void) +{ + return imx_get_ipgclk(); +} + +int imx_dump_clocks(void) +{ + printf("mpll: %10d Hz\n", imx_get_mpllclk()); + printf("upll: %10d Hz\n", imx_get_upllclk()); + printf("arm: %10d Hz\n", imx_get_armclk()); + printf("ahb: %10d Hz\n", imx_get_ahbclk()); + printf("uart: %10d Hz\n", imx_get_perclk(0)); + printf("gpt: %10d Hz\n", imx_get_ipgclk()); + printf("nand: %10d Hz\n", imx_get_perclk_(8)); + return 0; +} + diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h index a4ba5ef6b..b7a83a4e2 100644 --- a/include/asm-arm/arch-imx/imx-regs.h +++ b/include/asm-arm/arch-imx/imx-regs.h @@ -49,6 +49,8 @@ # include #elif defined CONFIG_ARCH_IMX35 # include +#elif defined CONFIG_ARCH_IMX25 +# include #else # error "unknown i.MX soc type" #endif diff --git a/include/asm-arm/arch-imx/imx25-flash-header.h b/include/asm-arm/arch-imx/imx25-flash-header.h new file mode 100644 index 000000000..59860dbda --- /dev/null +++ b/include/asm-arm/arch-imx/imx25-flash-header.h @@ -0,0 +1,44 @@ + +#define __flash_header_start __section(.flash_header_start) +#define __flash_header __section(.flash_header) +#define __dcd_entry __section(.dcd_entry) +#define __image_len __section(.image_len) + +struct mx25_dcd_entry { + unsigned long ptr_type; + unsigned long addr; + unsigned long val; +}; + +#define DCD_BARKER 0xb17219e9 + +struct mx25_dcd_header { + unsigned long barker; + unsigned long block_len; +}; + +struct mx25_rsa_public_key { + unsigned char rsa_exponent[4]; + unsigned char *rsa_modululs; + unsigned short *exponent_size; + unsigned short modulus_size; + unsigned char init_flag; +}; + +#define APP_CODE_BARKER 0x000000b1 + +struct mx25_flash_header { + void *app_code_jump_vector; + unsigned long app_code_barker; + void *app_code_csf; + struct mx25_dcd_header **dcd_ptr_ptr; + struct mx25_rsa_public_key *super_root_key; + struct mx25_dcd_header *dcd; + void *app_dest; +}; + +struct mx25_nand_flash_header { + struct mx25_flash_header flash_header; + struct mx25_dcd_header dcd_header; +}; + diff --git a/include/asm-arm/arch-imx/imx25-regs.h b/include/asm-arm/arch-imx/imx25-regs.h new file mode 100644 index 000000000..efbdbaad9 --- /dev/null +++ b/include/asm-arm/arch-imx/imx25-regs.h @@ -0,0 +1,142 @@ +/* + * (c) 2009 Pengutronix, Sascha Hauer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MX25_REGS_H +#define __ASM_ARCH_MX35_REGS_H + +/* + * sanity check + */ +#ifndef _IMX_REGS_H +# error "Please do not include directly. Use imx-regs.h instead." +#endif + +#define IMX_L2CC_BASE 0x30000000 +#define IMX_UART1_BASE 0x43F90000 +#define IMX_UART2_BASE 0x43F94000 +#define IMX_TIM1_BASE 0x53F90000 +#define IMX_IOMUXC_BASE 0x43FAC000 +#define IMX_WDT_BASE 0x53FDC000 +#define IMX_MAX_BASE 0x43F04000 +#define IMX_ESD_BASE 0xb8001000 +#define IMX_AIPS1_BASE 0x43F00000 +#define IMX_AIPS2_BASE 0x53F00000 +#define IMX_CCM_BASE 0x53F80000 +#define IMX_IIM_BASE 0x53FF0000 +#define IMX_OTG_BASE 0x53FF4000 +#define IMX_M3IF_BASE 0xB8003000 +#define IMX_NAND_BASE 0xBB000000 + +/* + * Clock Controller Module (CCM) + */ +#define CCM_MPCTL 0x00 +#define CCM_UPCTL 0x04 +#define CCM_CCTL 0x08 +#define CCM_CGCR0 0x0C +#define CCM_CGCR1 0x10 +#define CCM_CGCR2 0x14 +#define CCM_PCDR0 0x18 +#define CCM_PCDR1 0x1C +#define CCM_PCDR2 0x20 +#define CCM_PCDR3 0x24 +#define CCM_RCSR 0x28 +#define CCM_CRDR 0x2C +#define CCM_DCVR0 0x30 +#define CCM_DCVR1 0x34 +#define CCM_DCVR2 0x38 +#define CCM_DCVR3 0x3c +#define CCM_LTR0 0x40 +#define CCM_LTR1 0x44 +#define CCM_LTR2 0x48 +#define CCM_LTR3 0x4c + +#define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9) +#define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12) +#define PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16) +#define PDR0_HSP_PODF(x) (((x) & 0x3) << 20) +#define PDR0_AUTO_CON (1 << 0) +#define PDR0_PER_SEL (1 << 26) + +/* + * Adresses and ranges of the external chip select lines + */ +#define IMX_CS0_BASE 0xA0000000 +#define IMX_CS0_RANGE (128 * 1024 * 1024) +#define IMX_CS1_BASE 0xA8000000 +#define IMX_CS1_RANGE (128 * 1024 * 1024) +#define IMX_CS2_BASE 0xB0000000 +#define IMX_CS2_RANGE (32 * 1024 * 1024) +#define IMX_CS3_BASE 0xB2000000 +#define IMX_CS3_RANGE (32 * 1024 * 1024) +#define IMX_CS4_BASE 0xB4000000 +#define IMX_CS4_RANGE (32 * 1024 * 1024) +#define IMX_CS5_BASE 0xB6000000 +#define IMX_CS5_RANGE (32 * 1024 * 1024) + +#define IMX_SDRAM_CS0 0x80000000 +#define IMX_SDRAM_CS1 0x90000000 + +#define WEIM_BASE 0xb8002000 +#define CSCR_U(x) (WEIM_BASE + (x) * 0x10) +#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) +#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) + +/* + * Definitions for the clocksource driver + * + * These defines are using the i.MX1/27 notation + * to reuse the clocksource code for these CPUs + * on the i.MX35 + */ +/* Part 1: Registers */ +#define GPT_TCTL 0x00 +#define GPT_TPRER 0x04 +#define GPT_TCMP 0x10 +#define GPT_TCR 0x1c +#define GPT_TCN 0x24 +#define GPT_TSTAT 0x08 + +/* Part 2: Bitfields */ +#define TCTL_SWR (1<<15) /* Software reset */ +#define TCTL_FRR (1<<9) /* Freerun / restart */ +#define TCTL_CAP (3<<6) /* Capture Edge */ +#define TCTL_OM (1<<5) /* output mode */ +#define TCTL_IRQEN (1<<4) /* interrupt enable */ +#define TCTL_CLKSOURCE (6) /* Clock source bit position */ +#define TCTL_TEN (1) /* Timer enable */ +#define TPRER_PRES (0xff) /* Prescale */ +#define TSTAT_CAPT (1<<1) /* Capture event */ +#define TSTAT_COMP (1) /* Compare event */ + +/* + * Watchdog Registers + */ +#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ +#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */ +#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */ + +/* important definition of some bits of WCR */ +#define WCR_WDE 0x04 + +#endif /* __ASM_ARCH_MX25_REGS_H */ + diff --git a/include/asm-arm/arch-imx/u-boot.lds.h b/include/asm-arm/arch-imx/u-boot.lds.h new file mode 100644 index 000000000..52eb458f0 --- /dev/null +++ b/include/asm-arm/arch-imx/u-boot.lds.h @@ -0,0 +1,9 @@ + +#define PRE_IMAGE .pre_image : { \ + KEEP(*(.flash_header_start*)) \ + . = ALIGN(0x400); \ + KEEP(*(.flash_header*)) \ + KEEP(*(.dcd_entry*)) \ + KEEP(*(.image_len*)) \ + } + diff --git a/include/asm-generic/u-boot.lds.h b/include/asm-generic/u-boot.lds.h index e32ea5715..4982ce03d 100644 --- a/include/asm-generic/u-boot.lds.h +++ b/include/asm-generic/u-boot.lds.h @@ -1,4 +1,12 @@ +#ifdef CONFIG_ARCH_IMX25 +#include +#endif + +#ifndef PRE_IMAGE +#define PRE_IMAGE +#endif + #define INITCALLS \ KEEP(*(.initcall.0)) \ KEEP(*(.initcall.1)) \