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barebox
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Merge branch 'resource' of git://uboot.jcrosoft.org/barebox into next

This commit is contained in:
Sascha Hauer 2011-07-25 11:24:15 +02:00
parent db0c472af8 d4d8705636
commit 152dbd5553
45 changed files with 333 additions and 1077 deletions
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17
arch/arm/boards/at91rm9200ek/init.c
View File

@ -34,20 +34,6 @@
#include <mach/gpio.h>
#include <mach/io.h>
static struct resource cfi_resources[] = {
[0] = {
.start = AT91_CHIPSELECT_0,
.flags = IORESOURCE_MEM,
},
};
static struct device_d cfi_dev = {
.id = 0,
.name = "cfi_flash",
.num_resources = ARRAY_SIZE(cfi_resources),
.resource = cfi_resources,
};
static struct at91_ether_platform_data ether_pdata = {
.flags = AT91SAM_ETHER_RMII,
.phy_addr = 0,
@ -63,7 +49,8 @@ static int at91rm9200ek_devices_init(void)
at91_add_device_sdram(64 * 1024 * 1024);
at91_add_device_eth(&ether_pdata);
register_device(&cfi_dev);
add_cfi_flash_device(0, AT91_CHIPSELECT_0, 0, 0);
#if defined(CONFIG_DRIVER_CFI) || defined(CONFIG_DRIVER_CFI_OLD)
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self");

17
arch/arm/boards/at91sam9263ek/init.c
View File

@ -87,21 +87,6 @@ static void ek_add_device_nand(void)
at91_add_device_nand(&nand_pdata);
}
static struct resource cfi_resources[] = {
[0] = {
.start = AT91_CHIPSELECT_0,
.size = 8 * 1024 * 1024,
.flags = IORESOURCE_MEM,
},
};
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.num_resources = ARRAY_SIZE(cfi_resources),
.resource = cfi_resources,
};
static struct at91_ether_platform_data macb_pdata = {
.flags = AT91SAM_ETHER_RMII,
.phy_addr = 0,
@ -135,7 +120,7 @@ static int at91sam9263ek_devices_init(void)
at91_add_device_sdram(64 * 1024 * 1024);
ek_add_device_nand();
at91_add_device_eth(&macb_pdata);
register_device(&cfi_dev);
add_cfi_flash_device(0, AT91_CHIPSELECT_0, 8 * 1024 * 1024, 0);
ek_add_device_mci();
#if defined(CONFIG_DRIVER_CFI) || defined(CONFIG_DRIVER_CFI_OLD)

9
arch/arm/boards/edb93xx/edb93xx.c
View File

@ -38,13 +38,6 @@
* Up to 32MiB NOR type flash, connected to
* CS line 6, data width is 16 bit
*/
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = 0x60000000,
.size = EDB93XX_CFI_FLASH_SIZE,
};
static struct device_d eth_dev = {
.id = -1,
.name = "ep93xx_eth",
@ -54,7 +47,7 @@ static int ep93xx_devices_init(void)
{
struct device_d *sdram_dev;
register_device(&cfi_dev);
add_cfi_flash_device(-1, 0x60000000, EDB93XX_CFI_FLASH_SIZE, 0);
/*
* Create partitions that should be

19
arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
View File

@ -48,21 +48,6 @@
#include <mach/iomux-mx27.h>
#include <mach/devices-imx27.h>
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = 0xC0000000,
.size = 32 * 1024 * 1024,
};
#ifdef CONFIG_EUKREA_CPUIMX27_NOR_64MB
static struct device_d cfi_dev1 = {
.id = -1,
.name = "cfi_flash",
.map_base = 0xC2000000,
.size = 32 * 1024 * 1024,
};
#endif
#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB
#define SDRAM0 256
#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB
@ -254,9 +239,9 @@ static int eukrea_cpuimx27_devices_init(void)
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
register_device(&cfi_dev);
add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
#ifdef CONFIG_EUKREA_CPUIMX27_NOR_64MB
register_device(&cfi_dev1);
add_cfi_flash_device(-1, 0xC2000000, 32 * 1024 * 1024, 0);
#endif
imx27_add_nand(&nand_info);
sdram_dev = add_mem_device("ram0", 0xa0000000, SDRAM0 * 1024 * 1024,

9
arch/arm/boards/freescale-mx35-3-stack/3stack.c
View File

@ -59,13 +59,6 @@
#define MX35PDK_BOARD_REV_1 0
#define MX35PDK_BOARD_REV_2 1
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = IMX_CS0_BASE,
.size = 64 * 1024 * 1024,
};
static struct fec_platform_data fec_info = {
.xcv_type = MII100,
.phy_addr = 0x1F,
@ -170,7 +163,7 @@ static int f3s_devices_init(void)
* This platform supports NOR and NAND
*/
imx35_add_nand(&nand_info);
register_device(&cfi_dev);
add_cfi_flash_device(-1, IMX_CS0_BASE, 64 * 1024 * 1024, 0);
switch ((reg >> 25) & 0x3) {
case 0x01: /* NAND is the source */

9
arch/arm/boards/imx21ads/imx21ads.c
View File

@ -41,13 +41,6 @@
#define MX21ADS_IO_REG 0xCC800000
#define MX21ADS_IO_LCDON (1 << 9)
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = 0xC8000000,
.size = 32 * 1024 * 1024,
};
struct imx_nand_platform_data nand_info = {
.width = 1,
.hw_ecc = 1,
@ -171,7 +164,7 @@ static int mx21ads_devices_init(void)
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
register_device(&cfi_dev);
add_cfi_flash_device(-1, 0xC8000000, 32 * 1024 * 1024, 0);
sdram_dev = add_mem_device("ram0", 0xc0000000, 64 * 1024 * 1024,
IORESOURCE_MEM_WRITEABLE);
armlinux_add_dram(sdram_dev);

9
arch/arm/boards/imx27ads/imx27ads.c
View File

@ -34,13 +34,6 @@
#include <mach/iomux-mx27.h>
#include <mach/devices-imx27.h>
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = 0xC0000000,
.size = 32 * 1024 * 1024,
};
static struct fec_platform_data fec_info = {
.xcv_type = MII100,
.phy_addr = 1,
@ -114,7 +107,7 @@ static int mx27ads_devices_init(void)
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
register_device(&cfi_dev);
add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
sdram_dev = add_mem_device("ram0", 0xa0000000, 128 * 1024 * 1024,
IORESOURCE_MEM_WRITEABLE);

16
arch/arm/boards/mmccpu/init.c
View File

@ -37,20 +37,6 @@
#include <mach/gpio.h>
#include <mach/io.h>
static struct resource cfi_resources[] = {
[0] = {
.start = AT91_CHIPSELECT_0,
.flags = IORESOURCE_MEM,
},
};
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.num_resources = ARRAY_SIZE(cfi_resources),
.resource = cfi_resources,
};
static struct at91_ether_platform_data macb_pdata = {
.flags = AT91SAM_ETHER_MII | AT91SAM_ETHER_FORCE_LINK,
.phy_addr = 4,
@ -68,7 +54,7 @@ static int mmccpu_devices_init(void)
at91_add_device_sdram(128 * 1024 * 1024);
at91_add_device_eth(&macb_pdata);
register_device(&cfi_dev);
add_cfi_flash_device(0, AT91_CHIPSELECT_0, 0, 0);
devfs_add_partition("nor0", 0x00000, 256 * 1024, PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 128 * 1024, PARTITION_FIXED, "env0");

9
arch/arm/boards/netx/netx.c
View File

@ -30,13 +30,6 @@
#include <generated/mach-types.h>
#include <mach/netx-eth.h>
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = 0xC0000000,
.size = 32 * 1024 * 1024,
};
struct netx_eth_platform_data eth0_data = {
.xcno = 0,
};
@ -60,7 +53,7 @@ static struct device_d netx_eth_dev1 = {
static int netx_devices_init(void) {
struct device_d *sdram_dev;
register_device(&cfi_dev);
add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
sdram_dev = add_mem_device("ram0", 0x80000000, 64 * 1024 * 1024,
IORESOURCE_MEM_WRITEABLE);

18
arch/arm/boards/nhk8815/setup.c
View File

@ -33,21 +33,6 @@
#include <mach/nand.h>
#include <mach/fsmc.h>
static struct resource nhk8815_network_resources[] = {
[0] = {
.start = 0x34000300,
.size = 16,
.flags = IORESOURCE_MEM,
},
};
static struct device_d nhk8815_network_dev = {
.id = -1,
.name = "smc91c111",
.num_resources = ARRAY_SIZE(nhk8815_network_resources),
.resource = nhk8815_network_resources,
};
static int nhk8815_nand_init(void)
{
/* FSMC setup for nand chip select (8-bit nand in 8815NHK) */
@ -104,7 +89,8 @@ static int nhk8815_devices_init(void)
writel(0x0000305b, FSMC_BCR(1));
writel(0x00033f33, FSMC_BTR(1));
register_device(&nhk8815_network_dev);
add_generic_device("smc91c111", -1, NULL, 0x34000300, 16,
IORESOURCE_MEM, NULL);
register_device(&nhk8815_nand_device);

17
arch/arm/boards/pcm037/pcm037.c
View File

@ -39,17 +39,6 @@
#include <mach/imx-nand.h>
#include <mach/devices-imx31.h>
/*
* Up to 32MiB NOR type flash, connected to
* CS line 0, data width is 16 bit
*/
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = IMX_CS0_BASE,
.size = 32 * 1024 * 1024, /* area size */
};
/*
* SMSC 9217 network controller
* connected to CS line 1 and interrupt line
@ -227,7 +216,11 @@ static int imx31_devices_init(void)
__REG(CSCR_L(5)) = 0x444A0301;
__REG(CSCR_A(5)) = 0x44443302;
register_device(&cfi_dev);
/*
* Up to 32MiB NOR type flash, connected to
* CS line 0, data width is 16 bit
*/
add_cfi_flash_device(-1, IMX_CS0_BASE, 32 * 1024 * 1024, 0);
/*
* Create partitions that should be

9
arch/arm/boards/pcm038/pcm038.c
View File

@ -47,13 +47,6 @@
#include "pll.h"
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = 0xC0000000,
.size = 32 * 1024 * 1024,
};
static struct fec_platform_data fec_info = {
.xcv_type = MII100,
.phy_addr = 1,
@ -267,7 +260,7 @@ static int pcm038_devices_init(void)
spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info));
imx27_add_spi0(&pcm038_spi_0_data);
register_device(&cfi_dev);
add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
imx27_add_nand(&nand_info);
sdram_dev = add_mem_device("ram0", 0xa0000000, 128 * 1024 * 1024,
IORESOURCE_MEM_WRITEABLE);

17
arch/arm/boards/pcm043/pcm043.c
View File

@ -46,17 +46,6 @@
#include <mach/iomux-mx35.h>
#include <mach/devices-imx35.h>
/*
* Up to 32MiB NOR type flash, connected to
* CS line 0, data width is 16 bit
*/
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = IMX_CS0_BASE,
.size = 32 * 1024 * 1024, /* area size */
};
static struct fec_platform_data fec_info = {
.xcv_type = MII100,
};
@ -158,7 +147,11 @@ static int imx35_devices_init(void)
* This platform supports NOR and NAND
*/
imx35_add_nand(&nand_info);
register_device(&cfi_dev);
/*
* Up to 32MiB NOR type flash, connected to
* CS line 0, data width is 16 bit
*/
add_cfi_flash_device(-1, IMX_CS0_BASE, 32 * 1024 * 1024, 0);
if ((reg & 0xc00) == 0x800) { /* reset mode: external boot */
switch ( (reg >> 25) & 0x3) {

10
arch/arm/boards/pm9261/init.c
View File

@ -147,19 +147,11 @@ static void __init pm_add_device_dm9000(void)
static void __init ek_add_device_dm9000(void) {}
#endif /* CONFIG_DRIVER_NET_DM9000 */
static struct device_d cfi_dev = {
.id = 0,
.name = "cfi_flash",
.map_base = AT91_CHIPSELECT_0,
.size = 4 * 1024 * 1024,
};
static int pm9261_devices_init(void)
{
at91_add_device_sdram(64 * 1024 * 1024);
pm_add_device_nand();
register_device(&cfi_dev);
pm_add_device_dm9000();
add_cfi_flash_device(0, AT91_CHIPSELECT_0, 4 * 1024 * 1024, 0);
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self");
devfs_add_partition("nor0", 0x40000, 0x10000, PARTITION_FIXED, "env0");

17
arch/arm/boards/pm9263/init.c
View File

@ -86,21 +86,6 @@ static void pm_add_device_nand(void)
at91_add_device_nand(&nand_pdata);
}
static struct resource cfi_resources[] = {
[0] = {
.start = AT91_CHIPSELECT_0,
.size = 4 * 1024 * 1024,
.flags = IORESOURCE_MEM,
},
};
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.num_resources = ARRAY_SIZE(cfi_resources),
.resource = cfi_resources,
};
static struct at91_ether_platform_data macb_pdata = {
.flags = AT91SAM_ETHER_RMII,
.phy_addr = 0,
@ -119,7 +104,7 @@ static int pm9263_devices_init(void)
at91_add_device_sdram(64 * 1024 * 1024);
pm_add_device_nand();
at91_add_device_eth(&macb_pdata);
register_device(&cfi_dev);
add_cfi_flash_device(0, AT91_CHIPSELECT_0, 4 * 1024 * 1024, 0);
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 0x10000, PARTITION_FIXED, "env0");

10
arch/arm/boards/scb9328/scb9328.c
View File

@ -33,14 +33,6 @@
#include <dm9000.h>
#include <led.h>
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = 0x10000000,
.size = 16 * 1024 * 1024,
};
static struct dm9000_platform_data dm9000_data = {
.buswidth = DM9000_WIDTH_16,
.srom = 1,
@ -110,7 +102,7 @@ static int scb9328_devices_init(void)
CS5U = 0x00008400;
CS5L = 0x00000D03;
register_device(&cfi_dev);
add_cfi_flash_device(-1, 0x10000000, 16 * 1024 * 1024, 0);
sdram_dev = add_mem_device("ram0", 0x08000000, 16 * 1024 * 1024,
IORESOURCE_MEM_WRITEABLE);
armlinux_add_dram(sdram_dev);

19
arch/arm/boards/versatile/versatilepb.c
View File

@ -33,13 +33,6 @@
#include <partition.h>
#include <sizes.h>
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = VERSATILE_FLASH_BASE,
.size = VERSATILE_FLASH_SIZE,
};
static int vpb_console_init(void)
{
versatile_register_uart(0);
@ -47,22 +40,16 @@ static int vpb_console_init(void)
}
console_initcall(vpb_console_init);
static struct device_d smc911x_dev = {
.id = -1,
.name = "smc91c111",
.map_base = VERSATILE_ETH_BASE,
.size = 64 * 1024,
};
static int vpb_devices_init(void)
{
versatile_add_sdram(64 * 1024 *1024);
register_device(&cfi_dev);
add_cfi_flash_device(-1, VERSATILE_FLASH_BASE, VERSATILE_FLASH_SIZE, 0);
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self");
devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
register_device(&smc911x_dev);
add_generic_device("smc91c111", -1, NULL, VERSATILE_ETH_BASE, 64 * 1024,
IORESOURCE_MEM, NULL);
armlinux_set_architecture(MACH_TYPE_VERSATILE_PB);
armlinux_set_bootparams((void *)(0x00000100));

144
arch/arm/mach-at91/at91rm9200_devices.c
View File

@ -34,21 +34,6 @@ void at91_add_device_sdram(u32 size)
* -------------------------------------------------------------------- */
#if defined(CONFIG_DRIVER_NET_AT91_ETHER)
static struct resource eth_resources[] = {
[0] = {
.start = AT91_VA_BASE_EMAC,
.size = 0x1000,
.flags = IORESOURCE_MEM,
},
};
static struct device_d at91rm9200_eth_device = {
.id = 0,
.name = "at91_ether",
.resource = eth_resources,
.num_resources = ARRAY_SIZE(eth_resources),
};
void __init at91_add_device_eth(struct at91_ether_platform_data *data)
{
if (!data)
@ -77,8 +62,8 @@ void __init at91_add_device_eth(struct at91_ether_platform_data *data)
at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */
}
at91rm9200_eth_device.platform_data = data;
register_device(&at91rm9200_eth_device);
add_generic_device("at91_ether", 0, NULL, AT91_VA_BASE_EMAC, 0x1000,
IORESOURCE_MEM, data);
}
#else
void __init at91_add_device_eth(struct at91_ether_platform_data *data) {}
@ -89,21 +74,6 @@ void __init at91_add_device_eth(struct at91_ether_platform_data *data) {}
* -------------------------------------------------------------------- */
#if defined(CONFIG_NAND_ATMEL)
static struct resource nand_resources[] = {
[0] = {
.start = AT91_CHIPSELECT_3,
.size = 0x10,
.flags = IORESOURCE_MEM,
},
};
static struct device_d at91rm9200_nand_device = {
.id = -1,
.name = "atmel_nand",
.resource = nand_resources,
.num_resources = ARRAY_SIZE(nand_resources),
};
void __init at91_add_device_nand(struct atmel_nand_data *data)
{
unsigned int csa;
@ -138,8 +108,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */
at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */
at91rm9200_nand_device.platform_data = data;
platform_device_register(&at91rm9200_nand_device);
add_generic_device("atmel_nand", 0, NULL, AT91_CHIPSELECT_3, 0x10,
IORESOURCE_MEM, data);
}
#else
void __init at91_add_device_nand(struct atmel_nand_data *data) {}
@ -149,42 +119,12 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) {}
* UART
* -------------------------------------------------------------------- */
static struct resource dbgu_resources[] = {
[0] = {
.start = AT91_BASE_SYS + AT91_DBGU,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d dbgu_serial_device = {
.id = 0,
.name = "atmel_serial",
.resource = dbgu_resources,
.num_resources = ARRAY_SIZE(dbgu_resources),
};
static inline void configure_dbgu_pins(void)
{
at91_set_A_periph(AT91_PIN_PA30, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PA31, 1); /* DTXD */
}
static struct resource uart0_resources[] = {
[0] = {
.start = AT91RM9200_BASE_US0,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart0_serial_device = {
.id = 1,
.name = "atmel_serial",
.resource = uart0_resources,
.num_resources = ARRAY_SIZE(uart0_resources),
};
static inline void configure_usart0_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PA17, 1); /* TXD0 */
@ -202,21 +142,6 @@ static inline void configure_usart0_pins(unsigned pins)
}
}
static struct resource uart1_resources[] = {
[0] = {
.start = AT91RM9200_BASE_US1,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart1_serial_device = {
.id = 2,
.name = "atmel_serial",
.resource = uart1_resources,
.num_resources = ARRAY_SIZE(uart1_resources),
};
static inline void configure_usart1_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PB20, 1); /* TXD1 */
@ -236,21 +161,6 @@ static inline void configure_usart1_pins(unsigned pins)
at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS1 */
}
static struct resource uart2_resources[] = {
[0] = {
.start = AT91RM9200_BASE_US2,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart2_serial_device = {
.id = 3,
.name = "atmel_serial",
.resource = uart2_resources,
.num_resources = ARRAY_SIZE(uart2_resources),
};
static inline void configure_usart2_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PA22, 0); /* RXD2 */
@ -262,21 +172,6 @@ static inline void configure_usart2_pins(unsigned pins)
at91_set_B_periph(AT91_PIN_PA31, 0); /* RTS2 */
}
static struct resource uart3_resources[] = {
[0] = {
.start = AT91RM9200_BASE_US3,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart3_serial_device = {
.id = 4,
.name = "atmel_serial",
.resource = uart3_resources,
.num_resources = ARRAY_SIZE(uart3_resources),
};
static inline void configure_usart3_pins(unsigned pins)
{
at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */
@ -290,33 +185,46 @@ static inline void configure_usart3_pins(unsigned pins)
void __init at91_register_uart(unsigned id, unsigned pins)
{
resource_size_t start;
struct device_d *dev;
char* clk_name;
switch (id) {
case 0: /* DBGU */
configure_dbgu_pins();
at91_clock_associate("mck", &dbgu_serial_device, "usart");
register_device(&dbgu_serial_device);
start = AT91_BASE_SYS + AT91_DBGU;
clk_name = "mck";
id = 0;
break;
case AT91RM9200_ID_US0:
configure_usart0_pins(pins);
at91_clock_associate("usart0_clk", &uart0_serial_device, "usart");
clk_name = "usart0_clk";
start = AT91RM9200_BASE_US0;
id = 1;
break;
case AT91RM9200_ID_US1:
configure_usart1_pins(pins);
at91_clock_associate("usart1_clk", &uart1_serial_device, "usart");
register_device(&uart1_serial_device);
clk_name = "usart1_clk";
start = AT91RM9200_BASE_US1;
id = 2;
break;
case AT91RM9200_ID_US2:
configure_usart2_pins(pins);
at91_clock_associate("usart2_clk", &uart2_serial_device, "usart");
register_device(&uart2_serial_device);
clk_name = "usart2_clk";
start = AT91RM9200_BASE_US2;
id = 3;
break;
case AT91RM9200_ID_US3:
configure_usart3_pins(pins);
at91_clock_associate("usart3_clk", &uart3_serial_device, "usart");
register_device(&uart3_serial_device);
clk_name = "usart3_clk";
start = AT91RM9200_BASE_US3;
id = 4;
break;
default:
return;
}
dev = add_generic_device("atmel_serial", id, NULL, start, 4096,
IORESOURCE_MEM, NULL);
at91_clock_associate(clk_name, dev, "usart");
}

209
arch/arm/mach-at91/at91sam9260_devices.c
View File

@ -31,21 +31,6 @@ void at91_add_device_sdram(u32 size)
}
#if defined(CONFIG_DRIVER_NET_MACB)
static struct resource eth_resources[] = {
[0] = {
.start = AT91SAM9260_BASE_EMAC,
.size = 0x1000,
.flags = IORESOURCE_MEM,
},
};
static struct device_d macb_dev = {
.id = -1,
.name = "macb",
.resource = eth_resources,
.num_resources = ARRAY_SIZE(eth_resources),
};
void at91_add_device_eth(struct at91_ether_platform_data *data)
{
if (!data)
@ -74,29 +59,14 @@ void at91_add_device_eth(struct at91_ether_platform_data *data)
at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
}
macb_dev.platform_data = data;
register_device(&macb_dev);
add_generic_device("macb", 0, NULL, AT91SAM9260_BASE_EMAC, 0x1000,
IORESOURCE_MEM, data);
}
#else
void at91_add_device_eth(struct at91_ether_platform_data *data) {}
#endif
#if defined(CONFIG_NAND_ATMEL)
static struct resource nand_resources[] = {
[0] = {
.start = AT91_CHIPSELECT_3,
.size = 0x10,
.flags = IORESOURCE_MEM,
},
};
static struct device_d nand_dev = {
.id = -1,
.name = "atmel_nand",
.resource = nand_resources,
.num_resources = ARRAY_SIZE(nand_resources),
};
void at91_add_device_nand(struct atmel_nand_data *data)
{
unsigned long csa;
@ -119,49 +89,19 @@ void at91_add_device_nand(struct atmel_nand_data *data)
if (data->det_pin)
at91_set_gpio_input(data->det_pin, 1);
nand_dev.platform_data = data;
register_device(&nand_dev);
add_generic_device("atmel_nand", 0, NULL, AT91_CHIPSELECT_3, 0x10,
IORESOURCE_MEM, data);
}
#else
void at91_add_device_nand(struct atmel_nand_data *data) {}
#endif
static struct resource dbgu_resources[] = {
[0] = {
.start = AT91_BASE_SYS + AT91_DBGU,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d dbgu_serial_device = {
.id = 0,
.name = "atmel_serial",
.resource = dbgu_resources,
.num_resources = ARRAY_SIZE(dbgu_resources),
};
static inline void configure_dbgu_pins(void)
{
at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
}
static struct resource uart0_resources[] = {
[0] = {
.start = AT91SAM9260_BASE_US0,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart0_serial_device = {
.id = 1,
.name = "atmel_serial",
.resource = uart0_resources,
.num_resources = ARRAY_SIZE(uart0_resources),
};
static inline void configure_usart0_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
@ -181,21 +121,6 @@ static inline void configure_usart0_pins(unsigned pins)
at91_set_A_periph(AT91_PIN_PB25, 0); /* RI0 */
}
static struct resource uart1_resources[] = {
[0] = {
.start = AT91SAM9260_BASE_US1,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart1_serial_device = {
.id = 2,
.name = "atmel_serial",
.resource = uart1_resources,
.num_resources = ARRAY_SIZE(uart1_resources),
};
static inline void configure_usart1_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
@ -207,21 +132,6 @@ static inline void configure_usart1_pins(unsigned pins)
at91_set_A_periph(AT91_PIN_PB29, 0); /* CTS1 */
}
static struct resource uart2_resources[] = {
[0] = {
.start = AT91SAM9260_BASE_US2,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart2_serial_device = {
.id = 3,
.name = "atmel_serial",
.resource = uart2_resources,
.num_resources = ARRAY_SIZE(uart2_resources),
};
static inline void configure_usart2_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
@ -233,21 +143,6 @@ static inline void configure_usart2_pins(unsigned pins)
at91_set_A_periph(AT91_PIN_PA5, 0); /* CTS2 */
}
static struct resource uart3_resources[] = {
[0] = {
.start = AT91SAM9260_BASE_US3,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart3_serial_device = {
.id = 4,
.name = "atmel_serial",
.resource = uart3_resources,
.num_resources = ARRAY_SIZE(uart3_resources),
};
static inline void configure_usart3_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PB10, 1); /* TXD3 */
@ -259,42 +154,12 @@ static inline void configure_usart3_pins(unsigned pins)
at91_set_B_periph(AT91_PIN_PC10, 0); /* CTS3 */
}
static struct resource uart4_resources[] = {
[0] = {
.start = AT91SAM9260_BASE_US4,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart4_serial_device = {
.id = 5,
.name = "atmel_serial",
.resource = uart4_resources,
.num_resources = ARRAY_SIZE(uart4_resources),
};
static inline void configure_usart4_pins(void)
{
at91_set_B_periph(AT91_PIN_PA31, 1); /* TXD4 */
at91_set_B_periph(AT91_PIN_PA30, 0); /* RXD4 */
}
static struct resource uart5_resources[] = {
[0] = {
.start = AT91SAM9260_BASE_US5,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart5_serial_device = {
.id = 6,
.name = "atmel_serial",
.resource = uart5_resources,
.num_resources = ARRAY_SIZE(uart5_resources),
};
static inline void configure_usart5_pins(void)
{
at91_set_A_periph(AT91_PIN_PB12, 1); /* TXD5 */
@ -303,66 +168,68 @@ static inline void configure_usart5_pins(void)
void at91_register_uart(unsigned id, unsigned pins)
{
resource_size_t start;
struct device_d *dev;
char* clk_name;
switch (id) {
case 0: /* DBGU */
configure_dbgu_pins();
at91_clock_associate("mck", &dbgu_serial_device, "usart");
register_device(&dbgu_serial_device);
start = AT91_BASE_SYS + AT91_DBGU;
clk_name = "mck";
id = 0;
break;
case AT91SAM9260_ID_US0:
configure_usart0_pins(pins);
at91_clock_associate("usart0_clk", &uart0_serial_device, "usart");
register_device(&uart0_serial_device);
clk_name = "usart0_clk";
start = AT91SAM9260_BASE_US0;
id = 1;
break;
case AT91SAM9260_ID_US1:
configure_usart1_pins(pins);
at91_clock_associate("usart1_clk", &uart1_serial_device, "usart");
register_device(&uart1_serial_device);
clk_name = "usart1_clk";
start = AT91SAM9260_BASE_US1;
id = 2;
break;
case AT91SAM9260_ID_US2:
configure_usart2_pins(pins);
at91_clock_associate("usart2_clk", &uart2_serial_device, "usart");
register_device(&uart2_serial_device);
clk_name = "usart2_clk";
start = AT91SAM9260_BASE_US2;
id = 3;
break;
case AT91SAM9260_ID_US3:
configure_usart3_pins(pins);
at91_clock_associate("usart3_clk", &uart3_serial_device, "usart");
register_device(&uart3_serial_device);
clk_name = "usart3_clk";
start = AT91SAM9260_BASE_US3;
id = 4;
break;
case AT91SAM9260_ID_US4:
configure_usart4_pins();
at91_clock_associate("usart4_clk", &uart4_serial_device, "usart");
register_device(&uart4_serial_device);
clk_name = "usart4_clk";
start = AT91SAM9260_BASE_US4;
id = 5;
break;
case AT91SAM9260_ID_US5:
configure_usart5_pins();
at91_clock_associate("usart5_clk", &uart5_serial_device, "usart");
register_device(&uart5_serial_device);
clk_name = "usart5_clk";
start = AT91SAM9260_BASE_US5;
id = 6;
break;
default:
return;
}
dev = add_generic_device("atmel_serial", id, NULL, start, 4096,
IORESOURCE_MEM, NULL);
at91_clock_associate(clk_name, dev, "usart");
}
#if defined(CONFIG_MCI_ATMEL)
static struct resource mci_resources[] = {
[0] = {
.start = AT91SAM9260_BASE_MCI,
.size = SZ_16K,
.flags = IORESOURCE_MEM,
},
};
static struct device_d mci_device = {
.id = -1,
.name = "atmel_mci",
.num_resources = ARRAY_SIZE(mci_resources),
.resource = mci_resources,
};
/* Consider only one slot : slot 0 */
void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
{
struct device_d *dev;
if (!data)
return;
@ -393,9 +260,9 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
at91_set_A_periph(AT91_PIN_PA11, 1);
}
mci_device.platform_data = data;
at91_clock_associate("mci_clk", &mci_device, "mci_clk");
register_device(&mci_device);
dev = add_generic_device("atmel_mci", 0, NULL, AT91SAM9260_BASE_MCI, SZ_16K,
IORESOURCE_MEM, data);
at91_clock_associate("mci_clk", dev, "mci_clk");
}
#else
void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) {}

130
arch/arm/mach-at91/at91sam9261_devices.c
View File

@ -31,21 +31,6 @@ void at91_add_device_sdram(u32 size)
}
#if defined(CONFIG_NAND_ATMEL)
static struct resource nand_resources[] = {
[0] = {
.start = AT91_CHIPSELECT_3,
.size = 0x10,
.flags = IORESOURCE_MEM,
},
};
static struct device_d nand_dev = {
.id = 0,
.name = "atmel_nand",
.resource = nand_resources,
.num_resources = ARRAY_SIZE(nand_resources),
};
void at91_add_device_nand(struct atmel_nand_data *data)
{
unsigned long csa;
@ -71,49 +56,19 @@ void at91_add_device_nand(struct atmel_nand_data *data)
at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
nand_dev.platform_data = data;
register_device(&nand_dev);
add_generic_device("atmel_nand", 0, NULL, AT91_CHIPSELECT_3, 0x10,
IORESOURCE_MEM, data);
}
#else
void at91_add_device_nand(struct atmel_nand_data *data) {}
#endif
static struct resource dbgu_resources[] = {
[0] = {
.start = (AT91_BASE_SYS + AT91_DBGU),
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d dbgu_serial_device = {
.id = 0,
.name = "atmel_serial",
.resource = dbgu_resources,
.num_resources = ARRAY_SIZE(dbgu_resources),
};
static inline void configure_dbgu_pins(void)
{
at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
}
static struct resource uart0_resources[] = {
[0] = {
.start = AT91SAM9261_BASE_US0,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart0_serial_device = {
.id = 1,
.name = "atmel_serial",
.resource = uart0_resources,
.num_resources = ARRAY_SIZE(uart0_resources),
};
static inline void configure_usart0_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
@ -125,21 +80,6 @@ static inline void configure_usart0_pins(unsigned pins)
at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */
}
static struct resource uart1_resources[] = {
[0] = {
.start = AT91SAM9261_BASE_US1,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart1_serial_device = {
.id = 2,
.name = "atmel_serial",
.resource = uart1_resources,
.num_resources = ARRAY_SIZE(uart1_resources),
};
static inline void configure_usart1_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
@ -151,21 +91,6 @@ static inline void configure_usart1_pins(unsigned pins)
at91_set_B_periph(AT91_PIN_PA13, 0); /* CTS1 */
}
static struct resource uart2_resources[] = {
[0] = {
.start = AT91SAM9261_BASE_US2,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart2_serial_device = {
.id = 3,
.name = "atmel_serial",
.resource = uart2_resources,
.num_resources = ARRAY_SIZE(uart2_resources),
};
static inline void configure_usart2_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
@ -179,51 +104,50 @@ static inline void configure_usart2_pins(unsigned pins)
void at91_register_uart(unsigned id, unsigned pins)
{
resource_size_t start;
struct device_d *dev;
char* clk_name;
switch (id) {
case 0: /* DBGU */
configure_dbgu_pins();
at91_clock_associate("mck", &dbgu_serial_device, "usart");
register_device(&dbgu_serial_device);
start = AT91_BASE_SYS + AT91_DBGU;
clk_name = "mck";
id = 0;
break;
case AT91SAM9261_ID_US0:
configure_usart0_pins(pins);
at91_clock_associate("usart0_clk", &uart0_serial_device, "usart");
register_device(&uart0_serial_device);
clk_name = "usart0_clk";
start = AT91SAM9261_BASE_US0;
id = 1;
break;
case AT91SAM9261_ID_US1:
configure_usart1_pins(pins);
at91_clock_associate("usart1_clk", &uart1_serial_device, "usart");
register_device(&uart1_serial_device);
clk_name = "usart1_clk";
start = AT91SAM9261_BASE_US1;
id = 2;
break;
case AT91SAM9261_ID_US2:
configure_usart2_pins(pins);
at91_clock_associate("usart2_clk", &uart2_serial_device, "usart");
register_device(&uart2_serial_device);
clk_name = "usart3_clk";
start = AT91SAM9261_BASE_US2;
id = 3;
break;
default:
return;
}
dev = add_generic_device("atmel_serial", id, NULL, start, 4096,
IORESOURCE_MEM, NULL);
at91_clock_associate(clk_name, dev, "usart");
}
#if defined(CONFIG_MCI_ATMEL)
static struct resource mci_resources[] = {
[0] = {
.start = AT91SAM9261_BASE_MCI,
.size = SZ_16K,
.flags = IORESOURCE_MEM,
},
};
static struct device_d mci_device = {
.id = -1,
.name = "atmel_mci",
.num_resources = ARRAY_SIZE(mci_resources),
.resource = mci_resources,
};
/* Consider only one slot : slot 0 */
void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
{
struct device_d *dev;
if (!data)
return;
@ -254,9 +178,9 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
at91_set_B_periph(AT91_PIN_PA6, 1);
}
mci_device.platform_data = data;
at91_clock_associate("mci_clk", &mci_device, "mci_clk");
register_device(&mci_device);
dev = add_generic_device("atmel_mci", 0, NULL, AT91SAM9261_BASE_MCI, SZ_16K,
IORESOURCE_MEM, data);
at91_clock_associate("mci_clk", dev, "mci_clk");
}
#else
void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) {}

177
arch/arm/mach-at91/at91sam9263_devices.c
View File

@ -31,21 +31,6 @@ void at91_add_device_sdram(u32 size)
}
#if defined(CONFIG_DRIVER_NET_MACB)
static struct resource eth_resources[] = {
[0] = {
.start = AT91SAM9263_BASE_EMAC,
.size = 0x1000,
.flags = IORESOURCE_MEM,
},
};
static struct device_d macb_dev = {
.id = -1,
.name = "macb",
.resource = eth_resources,
.num_resources = ARRAY_SIZE(eth_resources),
};
void at91_add_device_eth(struct at91_ether_platform_data *data)
{
if (!data)
@ -73,29 +58,14 @@ void at91_add_device_eth(struct at91_ether_platform_data *data)
at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
}
macb_dev.platform_data = data;
register_device(&macb_dev);
add_generic_device("macb", 0, NULL, AT91SAM9263_BASE_EMAC, 0x1000,
IORESOURCE_MEM, data);
}
#else
void at91_add_device_eth(struct at91_ether_platform_data *data) {}
#endif
#if defined(CONFIG_NAND_ATMEL)
static struct resource nand_resources[] = {
[0] = {
.start = AT91_CHIPSELECT_3,
.size = 0x10,
.flags = IORESOURCE_MEM,
},
};
static struct device_d nand_dev = {
.id = -1,
.name = "atmel_nand",
.resource = nand_resources,
.num_resources = ARRAY_SIZE(nand_resources),
};
void at91_add_device_nand(struct atmel_nand_data *data)
{
unsigned long csa;
@ -118,49 +88,19 @@ void at91_add_device_nand(struct atmel_nand_data *data)
if (data->det_pin)
at91_set_gpio_input(data->det_pin, 1);
nand_dev.platform_data = data;
register_device(&nand_dev);
add_generic_device("atmel_nand", -1, NULL, AT91_CHIPSELECT_3, 0x10,
IORESOURCE_MEM, data);
}
#else
void at91_add_device_nand(struct atmel_nand_data *data) {}
#endif
static struct resource dbgu_resources[] = {
[0] = {
.start = (AT91_BASE_SYS + AT91_DBGU),
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d dbgu_serial_device = {
.id = 0,
.name = "atmel_serial",
.resource = dbgu_resources,
.num_resources = ARRAY_SIZE(dbgu_resources),
};
static inline void configure_dbgu_pins(void)
{
at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
}
static struct resource uart0_resources[] = {
[0] = {
.start = AT91SAM9263_BASE_US0,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart0_serial_device = {
.id = 1,
.name = "atmel_serial",
.resource = uart0_resources,
.num_resources = ARRAY_SIZE(uart0_resources),
};
static inline void configure_usart0_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
@ -172,21 +112,6 @@ static inline void configure_usart0_pins(unsigned pins)
at91_set_A_periph(AT91_PIN_PA29, 0); /* CTS0 */
}
static struct resource uart1_resources[] = {
[0] = {
.start = AT91SAM9263_BASE_US1,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart1_serial_device = {
.id = 2,
.name = "atmel_serial",
.resource = uart1_resources,
.num_resources = ARRAY_SIZE(uart1_resources),
};
static inline void configure_usart1_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
@ -198,21 +123,6 @@ static inline void configure_usart1_pins(unsigned pins)
at91_set_B_periph(AT91_PIN_PD8, 0); /* CTS1 */
}
static struct resource uart2_resources[] = {
[0] = {
.start = AT91SAM9263_BASE_US2,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart2_serial_device = {
.id = 3,
.name = "atmel_serial",
.resource = uart2_resources,
.num_resources = ARRAY_SIZE(uart2_resources),
};
static inline void configure_usart2_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
@ -226,67 +136,53 @@ static inline void configure_usart2_pins(unsigned pins)
void at91_register_uart(unsigned id, unsigned pins)
{
resource_size_t start;
struct device_d *dev;
char* clk_name;
switch (id) {
case 0: /* DBGU */
configure_dbgu_pins();
at91_clock_associate("mck", &dbgu_serial_device, "usart");
register_device(&dbgu_serial_device);
start = AT91_BASE_SYS + AT91_DBGU;
clk_name = "mck";
id = 0;
break;
case AT91SAM9263_ID_US0:
configure_usart0_pins(pins);
at91_clock_associate("usart0_clk", &uart0_serial_device, "usart");
register_device(&uart0_serial_device);
clk_name = "usart0_clk";
start = AT91SAM9263_BASE_US0;
id = 1;
break;
case AT91SAM9263_ID_US1:
configure_usart1_pins(pins);
at91_clock_associate("usart1_clk", &uart1_serial_device, "usart");
register_device(&uart1_serial_device);
clk_name = "usart1_clk";
start = AT91SAM9263_BASE_US1;
id = 2;
break;
case AT91SAM9263_ID_US2:
configure_usart2_pins(pins);
at91_clock_associate("usart2_clk", &uart2_serial_device, "usart");
register_device(&uart2_serial_device);
clk_name = "usart2_clk";
start = AT91SAM9263_BASE_US2;
id = 3;
break;
default:
return;
}
dev = add_generic_device("atmel_serial", id, NULL, start, 4096,
IORESOURCE_MEM, NULL);
at91_clock_associate(clk_name, dev, "usart");
}
#if defined(CONFIG_MCI_ATMEL)
static struct resource mci0_resources[] = {
[0] = {
.start = AT91SAM9263_BASE_MCI0,
.size = SZ_16K,
.flags = IORESOURCE_MEM,
},
};
static struct device_d mci0_device = {
.id = 0,
.name = "atmel_mci",
.num_resources = ARRAY_SIZE(mci0_resources),
.resource = mci0_resources,
};
static struct resource mci1_resources[] = {
[0] = {
.start = AT91SAM9263_BASE_MCI1,
.size = SZ_16K,
.flags = IORESOURCE_MEM,
},
};
static struct device_d mci1_device = {
.id = 1,
.name = "atmel_mci",
.num_resources = ARRAY_SIZE(mci1_resources),
.resource = mci1_resources,
};
/* Consider only one slot : slot 0 */
void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
{
resource_size_t start;
struct device_d *dev;
char* clk_name;
if (!data)
return;
@ -304,6 +200,8 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
at91_set_gpio_input(data->wp_pin, 1);
if (mmc_id == 0) { /* MCI0 */
start = AT91SAM9263_BASE_MCI0;
clk_name = "mci0_clk";
/* CLK */
at91_set_A_periph(AT91_PIN_PA12, 0);
@ -317,12 +215,9 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
at91_set_A_periph(AT91_PIN_PA4, 1);
at91_set_A_periph(AT91_PIN_PA5, 1);
}
mci0_device.platform_data = data;
at91_clock_associate("mci0_clk", &mci0_device, "mci_clk");
register_device(&mci0_device);
} else { /* MCI1 */
start = AT91SAM9263_BASE_MCI1;
clk_name = "mci1_clk";
/* CLK */
at91_set_A_periph(AT91_PIN_PA6, 0);
@ -336,11 +231,11 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
at91_set_A_periph(AT91_PIN_PA10, 1);
at91_set_A_periph(AT91_PIN_PA11, 1);
}
mci1_device.platform_data = data;
at91_clock_associate("mci1_clk", &mci1_device, "mci_clk");
register_device(&mci1_device);
}
dev = add_generic_device("atmel_mci", mmc_id, NULL, start, 4096,
IORESOURCE_MEM, data);
at91_clock_associate(clk_name, dev, "mci_clk");
}
#else
void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) {}

197
arch/arm/mach-at91/at91sam9g45_devices.c
View File

@ -31,21 +31,6 @@ void at91_add_device_sdram(u32 size)
}
#if defined(CONFIG_DRIVER_NET_MACB)
static struct resource eth_resources[] = {
[0] = {
.start = AT91SAM9G45_BASE_EMAC,
.size = 0x1000,
.flags = IORESOURCE_MEM,
},
};
static struct device_d macb_dev = {
.id = 0,
.name = "macb",
.resource = eth_resources,
.num_resources = ARRAY_SIZE(eth_resources),
};
void at91_add_device_eth(struct at91_ether_platform_data *data)
{
if (!data)
@ -74,29 +59,14 @@ void at91_add_device_eth(struct at91_ether_platform_data *data)
at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
}
macb_dev.platform_data = data;
register_device(&macb_dev);
add_generic_device("macb", 0, NULL, AT91SAM9G45_BASE_EMAC, 0x1000,
IORESOURCE_MEM, data);
}
#else
void at91_add_device_eth(struct at91_ether_platform_data *data) {}
#endif
#if defined(CONFIG_NAND_ATMEL)
static struct resource nand_resources[] = {
[0] = {
.start = AT91_CHIPSELECT_3,
.size = 0x10,
.flags = IORESOURCE_MEM,
},
};
static struct device_d nand_dev = {
.id = -1,
.name = "atmel_nand",
.resource = nand_resources,
.num_resources = ARRAY_SIZE(nand_resources),
};
void at91_add_device_nand(struct atmel_nand_data *data)
{
unsigned long csa;
@ -122,49 +92,19 @@ void at91_add_device_nand(struct atmel_nand_data *data)
if (data->det_pin)
at91_set_gpio_input(data->det_pin, 1);
nand_dev.platform_data = data;
register_device(&nand_dev);
add_generic_device("atmel_nand", -1, NULL, AT91_CHIPSELECT_3, 0x10,
IORESOURCE_MEM, data);
}
#else
void at91_add_device_nand(struct atmel_nand_data *data) {}
#endif
static struct resource dbgu_resources[] = {
[0] = {
.start = (AT91_BASE_SYS + AT91_DBGU),
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d dbgu_serial_device = {
.id = -1,
.name = "atmel_serial",
.resource = dbgu_resources,
.num_resources = ARRAY_SIZE(dbgu_resources),
};
static inline void configure_dbgu_pins(void)
{
at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
}
static struct resource uart0_resources[] = {
[0] = {
.start = AT91SAM9G45_BASE_US0,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart0_serial_device = {
.id = -1,
.name = "atmel_serial",
.resource = uart0_resources,
.num_resources = ARRAY_SIZE(uart0_resources),
};
static inline void configure_usart0_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
@ -176,21 +116,6 @@ static inline void configure_usart0_pins(unsigned pins)
at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
}
static struct resource uart1_resources[] = {
[0] = {
.start = AT91SAM9G45_BASE_US1,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart1_serial_device = {
.id = -1,
.name = "atmel_serial",
.resource = uart1_resources,
.num_resources = ARRAY_SIZE(uart1_resources),
};
static inline void configure_usart1_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
@ -202,21 +127,6 @@ static inline void configure_usart1_pins(unsigned pins)
at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
}
static struct resource uart2_resources[] = {
[0] = {
.start = AT91SAM9G45_BASE_US2,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart2_serial_device = {
.id = -1,
.name = "atmel_serial",
.resource = uart2_resources,
.num_resources = ARRAY_SIZE(uart2_resources),
};
static inline void configure_usart2_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
@ -228,21 +138,6 @@ static inline void configure_usart2_pins(unsigned pins)
at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
}
static struct resource uart3_resources[] = {
[0] = {
.start = AT91SAM9G45_BASE_US3,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart3_serial_device = {
.id = -1,
.name = "atmel_serial",
.resource = uart3_resources,
.num_resources = ARRAY_SIZE(uart3_resources),
};
static inline void configure_usart3_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
@ -256,72 +151,59 @@ static inline void configure_usart3_pins(unsigned pins)
void at91_register_uart(unsigned id, unsigned pins)
{
resource_size_t start;
struct device_d *dev;
char* clk_name;
switch (id) {
case 0: /* DBGU */
configure_dbgu_pins();
at91_clock_associate("mck", &dbgu_serial_device, "usart");
register_device(&dbgu_serial_device);
start = AT91_BASE_SYS + AT91_DBGU;
clk_name = "mck";
id = 0;
break;
case AT91SAM9G45_ID_US0:
configure_usart0_pins(pins);
at91_clock_associate("usart0_clk", &uart0_serial_device, "usart");
register_device(&uart0_serial_device);
clk_name = "usart0_clk";
start = AT91SAM9G45_BASE_US0;
id = 1;
break;
case AT91SAM9G45_ID_US1:
configure_usart1_pins(pins);
at91_clock_associate("usart1_clk", &uart1_serial_device, "usart");
register_device(&uart1_serial_device);
clk_name = "usart1_clk";
start = AT91SAM9G45_BASE_US1;
id = 2;
break;
case AT91SAM9G45_ID_US2:
configure_usart2_pins(pins);
at91_clock_associate("usart2_clk", &uart2_serial_device, "usart");
register_device(&uart2_serial_device);
clk_name = "usart2_clk";
start = AT91SAM9G45_BASE_US2;
id = 3;
break;
case AT91SAM9G45_ID_US3:
configure_usart3_pins(pins);
at91_clock_associate("usart3_clk", &uart2_serial_device, "usart");
register_device(&uart3_serial_device);
clk_name = "usart3_clk";
start = AT91SAM9G45_BASE_US3;
id = 4;
break;
default:
return;
}
dev = add_generic_device("atmel_serial", id, NULL, start, 4096,
IORESOURCE_MEM, NULL);
at91_clock_associate(clk_name, dev, "usart");
}
#if defined(CONFIG_MCI_ATMEL)
static struct resource mci0_resources[] = {
[0] = {
.start = AT91SAM9G45_BASE_MCI0,
.size = SZ_16K,
.flags = IORESOURCE_MEM,
},
};
static struct device_d mci0_device = {
.id = 0,
.name = "atmel_mci",
.num_resources = ARRAY_SIZE(mci0_resources),
.resource = mci0_resources,
};
static struct resource mci1_resources[] = {
[0] = {
.start = AT91SAM9G45_BASE_MCI1,
.size = SZ_16K,
.flags = IORESOURCE_MEM,
},
};
static struct device_d mci1_device = {
.id = 1,
.name = "atmel_mci",
.num_resources = ARRAY_SIZE(mci1_resources),
.resource = mci1_resources,
};
/* Consider only one slot : slot 0 */
void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
{
resource_size_t start;
struct device_d *dev;
char* clk_name;
if (!data)
return;
@ -339,6 +221,8 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
at91_set_gpio_input(data->wp_pin, 1);
if (mmc_id == 0) { /* MCI0 */
start = AT91SAM9G45_BASE_MCI0;
clk_name = "mci0_clk";
/* CLK */
at91_set_A_periph(AT91_PIN_PA0, 0);
@ -358,12 +242,9 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
at91_set_A_periph(AT91_PIN_PA9, 1);
}
}
mci0_device.platform_data = data;
at91_clock_associate("mci0_clk", &mci0_device, "mci_clk");
register_device(&mci0_device);
} else { /* MCI1 */
start = AT91SAM9G45_BASE_MCI1;
clk_name = "mci1_clk";
/* CLK */
at91_set_A_periph(AT91_PIN_PA31, 0);
@ -383,11 +264,11 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
at91_set_A_periph(AT91_PIN_PA30, 1);
}
}
mci1_device.platform_data = data;
at91_clock_associate("mci1_clk", &mci1_device, "mci_clk");
register_device(&mci1_device);
}
dev = add_generic_device("atmel_mci", mmc_id, NULL, start, 4096,
IORESOURCE_MEM, data);
at91_clock_associate(clk_name, dev, "mci_clk");
}
#else
void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) {}

19
arch/arm/mach-imx/devices.c
View File

@ -2,23 +2,10 @@
#include <driver.h>
#include <mach/devices.h>
static struct device_d *imx_add_device(char *name, int id, void *base, int size, void *pdata)
static inline struct device_d *imx_add_device(char *name, int id, void *base, int size, void *pdata)
{
struct device_d *dev;
dev = xzalloc(sizeof(*dev));
strcpy(dev->name,name);
dev->id = id;
dev->resource = xzalloc(sizeof(struct resource));
dev->resource[0].start = (resource_size_t)base;
dev->resource[0].size = size;
dev->resource[0].flags = IORESOURCE_MEM;
dev->num_resources = 1;
dev->platform_data = pdata;
register_device(dev);
return 0;
return add_generic_device(name, id, NULL, (resource_size_t)base, size,
IORESOURCE_MEM, pdata);
}
struct device_d *imx_add_fec(void *base, struct fec_platform_data *pdata)

42
arch/arm/mach-nomadik/8815.c
View File

@ -40,46 +40,20 @@ void st8815_add_device_sdram(u32 size)
armlinux_add_dram(sdram_dev);
}
static struct resource uart0_serial_resources[] = {
[0] = {
.start = NOMADIK_UART0_BASE,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart0_serial_device = {
.id = 0,
.name = "uart-pl011",
.num_resources = ARRAY_SIZE(uart0_serial_resources),
.resource = uart0_serial_resources,
};
static struct resource uart1_serial_resources[] = {
[0] = {
.start = NOMADIK_UART1_BASE,
.size = 4096,
.flags = IORESOURCE_MEM,
},
};
static struct device_d uart1_serial_device = {
.id = 1,
.name = "uart-pl011",
.num_resources = ARRAY_SIZE(uart1_serial_resources),
.resource = uart1_serial_resources,
};
void st8815_register_uart(unsigned id)
{
resource_size_t start;
struct device_d *dev;
switch (id) {
case 0:
nmdk_clk_create(&st8815_clk_48, dev_name(&uart0_serial_device));
register_device(&uart0_serial_device);
start = NOMADIK_UART1_BASE;
break;
case 1:
nmdk_clk_create(&st8815_clk_48, dev_name(&uart1_serial_device));
register_device(&uart1_serial_device);
start = NOMADIK_UART1_BASE;
break;
}
dev = add_generic_device("uart-pl011", id, NULL, start, 4096,
IORESOURCE_MEM, NULL);
nmdk_clk_create(&st8815_clk_48, dev_name(dev));
}

48
arch/arm/mach-versatile/core.c
View File

@ -51,34 +51,6 @@ void versatile_add_sdram(u32 size)
armlinux_add_dram(sdram_dev);
}
static struct device_d uart0_serial_device = {
.id = 0,
.name = "uart-pl011",
.map_base = VERSATILE_UART0_BASE,
.size = 4096,
};
static struct device_d uart1_serial_device = {
.id = 1,
.name = "uart-pl011",
.map_base = VERSATILE_UART1_BASE,
.size = 4096,
};
static struct device_d uart2_serial_device = {
.id = 2,
.name = "uart-pl011",
.map_base = VERSATILE_UART2_BASE,
.size = 4096,
};
static struct device_d uart3_serial_device = {
.id = 3,
.name = "uart-pl011",
.map_base = VERSATILE_UART3_BASE,
.size = 4096,
};
struct clk {
unsigned long rate;
};
@ -178,24 +150,28 @@ core_initcall(vpb_clocksource_init);
void versatile_register_uart(unsigned id)
{
resource_size_t start;
struct device_d *dev;
switch (id) {
case 0:
vpb_clk_create(&ref_clk_24, dev_name(&uart0_serial_device));
register_device(&uart0_serial_device);
start = VERSATILE_UART0_BASE;
break;
case 1:
vpb_clk_create(&ref_clk_24, dev_name(&uart1_serial_device));
register_device(&uart1_serial_device);
start = VERSATILE_UART1_BASE;
break;
case 2:
vpb_clk_create(&ref_clk_24, dev_name(&uart2_serial_device));
register_device(&uart2_serial_device);
start = VERSATILE_UART2_BASE;
break;
case 3:
vpb_clk_create(&ref_clk_24, dev_name(&uart3_serial_device));
register_device(&uart3_serial_device);
start = VERSATILE_UART3_BASE;
break;
default:
return;
}
dev = add_generic_device("uart-pl011", id, NULL, start, 4096,
IORESOURCE_MEM, NULL);
vpb_clk_create(&ref_clk_24, dev_name(dev));
}
void __noreturn reset_cpu (unsigned long ignored)

9
arch/blackfin/boards/ipe337/ipe337.c
View File

@ -5,13 +5,6 @@
#include <partition.h>
#include <fs.h>
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = 0x20000000,
.size = 32 * 1024 * 1024,
};
static struct device_d smc911x_dev = {
.id = -1,
.name = "smc911x",
@ -20,7 +13,7 @@ static struct device_d smc911x_dev = {
};
static int ipe337_devices_init(void) {
register_device(&cfi_dev);
add_cfi_flash_device(-1, 0x20000000, 32 * 1024 * 1024, 0);
add_mem_device("ram0", 0x0, 128 * 1024 * 1024,
IORESOURCE_MEM_WRITEABLE);

9
arch/nios2/boards/generic/generic.c
View File

@ -4,13 +4,6 @@
#include <partition.h>
#include <fs.h>
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = NIOS_SOPC_FLASH_BASE,
.size = NIOS_SOPC_FLASH_SIZE,
};
static int phy_address = 1;
static struct device_d mac_dev = {
@ -37,7 +30,7 @@ static struct device_d epcs_flash_device = {
static int generic_devices_init(void)
{
register_device(&cfi_dev);
add_cfi_flash_device(-1, NIOS_SOPC_FLASH_BASE, NIOS_SOPC_FLASH_SIZE, 0);
add_mem_device("ram0", NIOS_SOPC_MEMORY_BASE, NIOS_SOPC_MEMORY_SIZE,
IORESOURCE_MEM_WRITEABLE);
register_device(&mac_dev);

9
arch/ppc/boards/pcm030/pcm030.c
View File

@ -37,13 +37,6 @@
#include <mem_malloc.h>
#include <reloc.h>
struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = 0xff000000,
.size = 16 * 1024 * 1024,
};
static struct mpc5xxx_fec_platform_data fec_info = {
.xcv_type = MII100,
};
@ -57,7 +50,7 @@ struct device_d eth_dev = {
static int devices_init (void)
{
register_device(&cfi_dev);
add_cfi_flash_device(-1, 0xff000000, 16 * 1024 * 1024, 0);
add_mem_device("ram0", 0x0, 64 * 1024 * 1024,
IORESOURCE_MEM_WRITEABLE);
register_device(&eth_dev);

1
common/Makefile
View File

@ -9,7 +9,6 @@ obj-$(CONFIG_POLLER) += poller.o
obj-$(CONFIG_BLOCK) += block.o
obj-y += memory.o
obj-y += mem.o
obj-$(CONFIG_MALLOC_DLMALLOC) += dlmalloc.o
obj-$(CONFIG_MALLOC_DUMMY) += dummy_malloc.o
obj-y += clock.o

1
drivers/Makefile
View File

@ -1,3 +1,4 @@
obj-y += base/
obj-y += net/
obj-y += serial/
obj-y += mtd/

2
drivers/ata/bios.c
View File

@ -257,7 +257,7 @@ static int biosdisk_probe(struct device_d *dev)
strcpy(drive_dev->name, "biosdisk");
drive_dev->id = drive - 0x80;
drive_dev->map_base = 0;
drive_dev->resource[0].start = 0;
drive_dev->platform_data = p;
register_device(drive_dev);

3
drivers/base/Makefile Normal file
View File

@ -0,0 +1,3 @@
obj-y += driver.o
obj-y += platform.o
obj-y += resource.o

0
lib/driver.c → drivers/base/driver.c
View File

0
lib/bus.c → drivers/base/platform.c
View File

16
common/mem.c → drivers/base/resource.c
View File

@ -25,22 +25,26 @@
#include <driver.h>
#include <xfuncs.h>
struct device_d *add_mem_device(const char *name, resource_size_t start,
resource_size_t size, unsigned int flags)
struct device_d *add_generic_device(const char* devname, int id, const char *resname,
resource_size_t start, resource_size_t size, unsigned int flags,
void *pdata)
{
struct device_d *dev;
dev = xzalloc(sizeof(*dev));
strcpy(dev->name, "mem");
dev->id = -1;
strcpy(dev->name, devname);
dev->id = id;
dev->resource = xzalloc(sizeof(struct resource));
dev->num_resources = 1;
dev->resource[0].name = xstrdup(name);
if (resname)
dev->resource[0].name = xstrdup(resname);
dev->resource[0].start = start;
dev->resource[0].size = size;
dev->resource[0].flags = IORESOURCE_MEM | flags;
dev->resource[0].flags = flags;
dev->platform_data = pdata;
register_device(dev);
return dev;
}
EXPORT_SYMBOL(add_generic_device);

6
drivers/i2c/busses/i2c-imx.c
View File

@ -113,11 +113,11 @@ struct imx_i2c_struct {
#ifdef CONFIG_I2C_DEBUG
static void i2c_imx_dump_reg(struct i2c_adapter *adapter)
{
unsigned long base = adapter->dev->map_base;
struct imx_i2c_struct *i2c_imx = to_imx_i2c_struct(adapter);
u32 reg_cr, reg_sr;
reg_cr = readb(base + IMX_I2C_I2CR);
reg_sr = readb(base + IMX_I2C_I2SR);
reg_cr = readb(i2c_imx->base + IMX_I2C_I2CR);
reg_sr = readb(i2c_imx->base + IMX_I2C_I2SR);
dev_dbg(adapter->dev, "CONTROL:\t"
"IEN =%d, IIEN=%d, MSTA=%d, MTX =%d, TXAK=%d, RSTA=%d\n",

3
drivers/i2c/busses/i2c-omap.c
View File

@ -716,7 +716,6 @@ i2c_omap_probe(struct device_d *pdev)
{
struct omap_i2c_struct *i2c_omap;
/* struct i2c_platform_data *pdata; */
/* unsigned long base = pdev->map_base; */
int r;
u32 speed = 0;
@ -732,7 +731,7 @@ i2c_omap_probe(struct device_d *pdev)
speed = 100; /* Defualt speed */
i2c_omap->speed = speed;
i2c_omap->base = (void*)pdev->map_base;
i2c_omap->base = dev_request_mem_region(pdev, 0);
printf ("I2C probe\n");
omap_i2c_unidle(i2c_omap);

4
drivers/mci/mci-core.c
View File

@ -1231,8 +1231,8 @@ static int mci_card_probe(struct device_d *mci_dev)
p->priv = mci_dev;
strcpy(disk_dev->name, "disk");
disk_dev->size = mci->capacity;
disk_dev->map_base = 0;
disk_dev->resource[0].size = mci->capacity;
disk_dev->resource[0].start = 0;
disk_dev->platform_data = p;
register_device(disk_dev);

4
drivers/mci/mxs.c
View File

@ -702,7 +702,7 @@ static int mxs_mci_probe(struct device_d *hw_dev)
host->send_cmd = mxs_mci_request,
host->set_ios = mxs_mci_set_ios,
host->init = mxs_mci_initialize,
mxs_mci->regs = (void *)hw_dev->map_base;
mxs_mci->regs = dev_request_mem_region(dev, 0);
/* feed forward the platform specific values */
host->voltages = pd->voltages;
@ -713,7 +713,7 @@ static int mxs_mci_probe(struct device_d *hw_dev)
#endif
#ifdef CONFIG_ARCH_IMX28
/* one dedicated clock per unit */
switch (hw_dev->map_base) {
switch (hw_dev->resource[0].start) {
case IMX_SSP0_BASE:
mxs_mci->index = 0;
break;

2
drivers/mci/omap_hsmmc.c
View File

@ -558,7 +558,7 @@ static int omap_mmc_probe(struct device_d *dev)
hsmmc->mci.init = mmc_init_setup;
hsmmc->mci.host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
hsmmc->base = (struct hsmmc *)dev->map_base;
hsmmc->base = dev_request_mem_region(dev, 0);
hsmmc->mci.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;

105
drivers/mci/s3c.c
View File

@ -153,6 +153,7 @@
#define SDIDATA 0x40
struct s3c_mci_host {
void __iomem *base;
int bus_width:2; /* 0 = 1 bit, 1 = 4 bit, 2 = 8 bit */
unsigned clock; /* current clock in Hz */
unsigned data_size; /* data transfer in bytes */
@ -211,6 +212,7 @@ static unsigned s3c_setup_clock_speed(struct device_d *hw_dev, unsigned nc)
{
unsigned clock;
uint32_t mci_psc;
struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
if (nc == 0)
return 0;
@ -224,7 +226,7 @@ static unsigned s3c_setup_clock_speed(struct device_d *hw_dev, unsigned nc)
pr_warning("SD/MMC clock might be too high!\n");
}
writel(mci_psc - 1, hw_dev->map_base + SDIPRE);
writel(mci_psc - 1, host_data->base + SDIPRE);
return clock / mci_psc;
}
@ -237,10 +239,12 @@ static unsigned s3c_setup_clock_speed(struct device_d *hw_dev, unsigned nc)
*/
static void s3c_mci_reset(struct device_d *hw_dev)
{
struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
/* reset the hardware */
writel(SDICON_SDRESET, hw_dev->map_base + SDICON);
writel(SDICON_SDRESET, host_data->base + SDICON);
/* wait until reset it finished */
while (readl(hw_dev->map_base + SDICON) & SDICON_SDRESET)
while (readl(host_data->base + SDICON) & SDICON_SDRESET)
;
}
@ -257,9 +261,9 @@ static int s3c_mci_initialize(struct device_d *hw_dev, struct device_d *mci_dev)
/* restore last settings */
host_data->clock = s3c_setup_clock_speed(hw_dev, host_data->clock);
writel(0x007FFFFF, hw_dev->map_base + SDITIMER);
writel(SDICON_MMCCLOCK, hw_dev->map_base + SDICON);
writel(512, hw_dev->map_base + SDIBSIZE);
writel(0x007FFFFF, host_data->base + SDITIMER);
writel(SDICON_MMCCLOCK, host_data->base + SDICON);
writel(512, host_data->base + SDIBSIZE);
return 0;
}
@ -335,11 +339,12 @@ static uint32_t s3c_prepare_data_setup(struct device_d *hw_dev, unsigned data_fl
static int s3c_terminate_transfer(struct device_d *hw_dev)
{
unsigned stoptries = 3;
struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
while (readl(hw_dev->map_base + SDIDSTA) & (SDIDSTA_TXDATAON | SDIDSTA_RXDATAON)) {
while (readl(host_data->base + SDIDSTA) & (SDIDSTA_TXDATAON | SDIDSTA_RXDATAON)) {
pr_debug("Transfer still in progress.\n");
writel(SDIDCON_STOP, hw_dev->map_base + SDIDCON);
writel(SDIDCON_STOP, host_data->base + SDIDCON);
s3c_mci_initialize(hw_dev, NULL);
if ((stoptries--) == 0) {
@ -360,12 +365,13 @@ static int s3c_terminate_transfer(struct device_d *hw_dev)
static int s3c_prepare_data_transfer(struct device_d *hw_dev, struct mci_data *data)
{
uint32_t reg;
struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
writel(data->blocksize, hw_dev->map_base + SDIBSIZE);
writel(data->blocksize, host_data->base + SDIBSIZE);
reg = s3c_prepare_data_setup(hw_dev, data->flags);
reg |= data->blocks & SDIDCON_BLKNUM;
writel(reg, hw_dev->map_base + SDIDCON);
writel(0x007FFFFF, hw_dev->map_base + SDITIMER);
writel(reg, host_data->base + SDIDCON);
writel(0x007FFFFF, host_data->base + SDITIMER);
return 0;
}
@ -382,34 +388,35 @@ static int s3c_send_command(struct device_d *hw_dev, struct mci_cmd *cmd,
{
uint32_t reg, t1;
int rc;
struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
writel(0x007FFFFF, hw_dev->map_base + SDITIMER);
writel(0x007FFFFF, host_data->base + SDITIMER);
/* setup argument */
writel(cmd->cmdarg, hw_dev->map_base + SDICMDARG);
writel(cmd->cmdarg, host_data->base + SDICMDARG);
/* setup command and transfer characteristic */
reg = s3c_prepare_command_setup(cmd->resp_type, data != NULL ? data->flags : 0);
reg |= cmd->cmdidx & SDICMDCON_INDEX;
/* run the command right now */
writel(reg | SDICMDCON_CMDSTART, hw_dev->map_base + SDICMDCON);
t1 = readl(hw_dev->map_base + SDICMDSTAT);
writel(reg | SDICMDCON_CMDSTART, host_data->base + SDICMDCON);
t1 = readl(host_data->base + SDICMDSTAT);
/* wait until command is done */
while (1) {
reg = readl(hw_dev->map_base + SDICMDSTAT);
reg = readl(host_data->base + SDICMDSTAT);
/* done? */
if (cmd->resp_type & MMC_RSP_PRESENT) {
if (reg & SDICMDSTAT_RSPFIN) {
writel(SDICMDSTAT_RSPFIN,
hw_dev->map_base + SDICMDSTAT);
host_data->base + SDICMDSTAT);
rc = 0;
break;
}
} else {
if (reg & SDICMDSTAT_CMDSENT) {
writel(SDICMDSTAT_CMDSENT,
hw_dev->map_base + SDICMDSTAT);
host_data->base + SDICMDSTAT);
rc = 0;
break;
}
@ -417,17 +424,17 @@ static int s3c_send_command(struct device_d *hw_dev, struct mci_cmd *cmd,
/* timeout? */
if (reg & SDICMDSTAT_CMDTIMEOUT) {
writel(SDICMDSTAT_CMDTIMEOUT,
hw_dev->map_base + SDICMDSTAT);
host_data->base + SDICMDSTAT);
rc = -ETIMEDOUT;
break;
}
}
if ((rc == 0) && (cmd->resp_type & MMC_RSP_PRESENT)) {
cmd->response[0] = readl(hw_dev->map_base + SDIRSP0);
cmd->response[1] = readl(hw_dev->map_base + SDIRSP1);
cmd->response[2] = readl(hw_dev->map_base + SDIRSP2);
cmd->response[3] = readl(hw_dev->map_base + SDIRSP3);
cmd->response[0] = readl(host_data->base + SDIRSP0);
cmd->response[1] = readl(host_data->base + SDIRSP1);
cmd->response[2] = readl(host_data->base + SDIRSP2);
cmd->response[3] = readl(host_data->base + SDIRSP3);
}
/* do not disable the clock! */
return rc;
@ -443,14 +450,15 @@ static int s3c_send_command(struct device_d *hw_dev, struct mci_cmd *cmd,
static int s3c_prepare_engine(struct device_d *hw_dev)
{
int rc;
struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
rc = s3c_terminate_transfer(hw_dev);
if (rc != 0)
return rc;
writel(-1, hw_dev->map_base + SDICMDSTAT);
writel(-1, hw_dev->map_base + SDIDSTA);
writel(-1, hw_dev->map_base + SDIFSTA);
writel(-1, host_data->base + SDICMDSTAT);
writel(-1, host_data->base + SDIDSTA);
writel(-1, host_data->base + SDIFSTA);
return 0;
}
@ -487,6 +495,7 @@ static int s3c_mci_read_block(struct device_d *hw_dev, struct mci_data *data)
{
uint32_t *p;
unsigned cnt, data_size;
struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
#define READ_REASON_TO_FAIL (SDIDSTA_CRCFAIL | SDIDSTA_RXCRCFAIL | SDIDSTA_DATATIMEOUT)
@ -496,23 +505,23 @@ static int s3c_mci_read_block(struct device_d *hw_dev, struct mci_data *data)
while (data_size > 0) {
/* serious error? */
if (readl(hw_dev->map_base + SDIDSTA) & READ_REASON_TO_FAIL) {
if (readl(host_data->base + SDIDSTA) & READ_REASON_TO_FAIL) {
pr_err("Failed while reading data\n");
return -EIO;
}
/* now check the FIFO status */
if (readl(hw_dev->map_base + SDIFSTA) & SDIFSTA_FIFOFAIL) {
if (readl(host_data->base + SDIFSTA) & SDIFSTA_FIFOFAIL) {
pr_err("Data loss due to FIFO overflow when reading\n");
return -EIO;
}
/* we only want to read full words */
cnt = (readl(hw_dev->map_base + SDIFSTA) & SDIFSTA_COUNTMASK) >> 2;
cnt = (readl(host_data->base + SDIFSTA) & SDIFSTA_COUNTMASK) >> 2;
/* read one chunk of data from the FIFO */
while (cnt--) {
*p = readl(hw_dev->map_base + SDIDATA);
*p = readl(host_data->base + SDIDATA);
p++;
if (data_size >= 4)
data_size -= 4;
@ -542,6 +551,7 @@ static int s3c_mci_write_block(struct device_d *hw_dev, struct mci_cmd *cmd,
const uint32_t *p = (const uint32_t*)data->src;
unsigned cnt, data_size;
uint32_t reg;
struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
#define WRITE_REASON_TO_FAIL (SDIDSTA_CRCFAIL | SDIDSTA_DATATIMEOUT)
@ -553,7 +563,7 @@ static int s3c_mci_write_block(struct device_d *hw_dev, struct mci_cmd *cmd,
*/
cnt = 16;
while (cnt--) {
writel(*p, hw_dev->map_base + SDIDATA);
writel(*p, host_data->base + SDIDATA);
p++;
if (data_size >= 4)
data_size -= 4;
@ -566,7 +576,7 @@ static int s3c_mci_write_block(struct device_d *hw_dev, struct mci_cmd *cmd,
/* data is now in place and waits for transmitt. Start the command right now */
s3c_send_command(hw_dev, cmd, data);
if ((reg = readl(hw_dev->map_base + SDIFSTA)) & SDIFSTA_FIFOFAIL) {
if ((reg = readl(host_data->base + SDIFSTA)) & SDIFSTA_FIFOFAIL) {
pr_err("Command fails immediatly due to FIFO underrun when writing %08X\n",
reg);
return -EIO;
@ -574,24 +584,24 @@ static int s3c_mci_write_block(struct device_d *hw_dev, struct mci_cmd *cmd,
while (data_size > 0) {
if (readl(hw_dev->map_base + SDIDSTA) & WRITE_REASON_TO_FAIL) {
if (readl(host_data->base + SDIDSTA) & WRITE_REASON_TO_FAIL) {
pr_err("Failed writing data\n");
return -EIO;
}
/* now check the FIFO status */
if ((reg = readl(hw_dev->map_base + SDIFSTA)) & SDIFSTA_FIFOFAIL) {
if ((reg = readl(host_data->base + SDIFSTA)) & SDIFSTA_FIFOFAIL) {
pr_err("Data loss due to FIFO underrun when writing %08X\n",
reg);
return -EIO;
}
/* we only want to write full words */
cnt = 16 - (((readl(hw_dev->map_base + SDIFSTA) & SDIFSTA_COUNTMASK) + 3) >> 2);
cnt = 16 - (((readl(host_data->base + SDIFSTA) & SDIFSTA_COUNTMASK) + 3) >> 2);
/* fill the FIFO if it has free entries */
while (cnt--) {
writel(*p, hw_dev->map_base + SDIDATA);
writel(*p, host_data->base + SDIDATA);
p++;
if (data_size >= 4)
data_size -= 4;
@ -616,6 +626,7 @@ static int s3c_mci_adtc(struct device_d *hw_dev, struct mci_cmd *cmd,
struct mci_data *data)
{
int rc;
struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
rc = s3c_prepare_engine(hw_dev);
if (rc != 0)
@ -629,7 +640,7 @@ static int s3c_mci_adtc(struct device_d *hw_dev, struct mci_cmd *cmd,
s3c_send_command(hw_dev, cmd, data);
rc = s3c_mci_read_block(hw_dev, data);
if (rc == 0) {
while (!(readl(hw_dev->map_base + SDIDSTA) & SDIDSTA_XFERFINISH))
while (!(readl(host_data->base + SDIDSTA) & SDIDSTA_XFERFINISH))
;
} else
s3c_terminate_transfer(hw_dev);
@ -638,12 +649,12 @@ static int s3c_mci_adtc(struct device_d *hw_dev, struct mci_cmd *cmd,
if (data->flags & MMC_DATA_WRITE) {
rc = s3c_mci_write_block(hw_dev, cmd, data);
if (rc == 0) {
while (!(readl(hw_dev->map_base + SDIDSTA) & SDIDSTA_XFERFINISH))
while (!(readl(host_data->base + SDIDSTA) & SDIDSTA_XFERFINISH))
;
} else
s3c_terminate_transfer(hw_dev);
}
writel(0, hw_dev->map_base + SDIDCON);
writel(0, host_data->base + SDIDCON);
return rc;
}
@ -674,11 +685,12 @@ static int mci_request(struct mci_host *mci_pdata, struct mci_cmd *cmd,
struct mci_data *data)
{
struct device_d *hw_dev = mci_pdata->hw_dev;
struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
int rc;
/* enable clock */
writel(readl(hw_dev->map_base + SDICON) | SDICON_CLKEN,
hw_dev->map_base + SDICON);
writel(readl(host_data->base + SDICON) | SDICON_CLKEN,
host_data->base + SDICON);
if ((cmd->resp_type == 0) || (data == NULL))
rc = s3c_mci_std_cmds(hw_dev, cmd);
@ -688,8 +700,8 @@ static int mci_request(struct mci_host *mci_pdata, struct mci_cmd *cmd,
s3c_finish_request(hw_dev);
/* disable clock */
writel(readl(hw_dev->map_base + SDICON) & ~SDICON_CLKEN,
hw_dev->map_base + SDICON);
writel(readl(host_data->base + SDICON) & ~SDICON_CLKEN,
host_data->base + SDICON);
return rc;
}
@ -720,7 +732,7 @@ static void mci_set_ios(struct mci_host *mci_pdata, struct device_d *mci_dev,
break;
}
reg = readl(hw_dev->map_base + SDICON);
reg = readl(host_data->base + SDICON);
if (clock) {
/* setup the IO clock frequency and enable it */
host->clock = host_data->clock = s3c_setup_clock_speed(hw_dev, clock);
@ -729,7 +741,7 @@ static void mci_set_ios(struct mci_host *mci_pdata, struct device_d *mci_dev,
reg &= ~SDICON_CLKEN; /* disable the clock */
host->clock = host_data->clock = 0;
}
writel(reg, hw_dev->map_base + SDICON);
writel(reg, host_data->base + SDICON);
pr_debug("IO settings: bus width=%d, frequency=%u Hz\n",
host->bus_width, host->clock);
@ -783,6 +795,7 @@ static int s3c_mci_probe(struct device_d *hw_dev)
}
hw_dev->priv = &host_data;
host_data.base = dev_request_mem_region(hw_dev, 0);
mci_pdata.hw_dev = hw_dev;
/* feed forward the platform specific values */
@ -795,7 +808,7 @@ static int s3c_mci_probe(struct device_d *hw_dev)
* Start the clock to let the engine and the card finishes its startup
*/
host_data.clock = s3c_setup_clock_speed(hw_dev, mci_pdata.f_min);
writel(SDICON_FIFORESET | SDICON_MMCCLOCK, hw_dev->map_base + SDICON);
writel(SDICON_FIFORESET | SDICON_MMCCLOCK, host_data.base + SDICON);
return mci_register(&mci_pdata);
}

10
drivers/mtd/nand/nand_omap_gpmc.c
View File

@ -14,8 +14,8 @@
* static struct device_d my_nand_device = {
* .name = "gpmc_nand",
* .id = some identifier you need to show.. e.g. "gpmc_nand0"
* .map_base = GPMC base address
* .size = GPMC address map size.
* .resource[0].start = GPMC base address
* .resource[0].size = GPMC address map size.
* .platform_data = platform data - required - explained below
* };
* platform data required:
@ -97,7 +97,7 @@ struct gpmc_nand_info {
void *gpmc_command;
void *gpmc_address;
void *gpmc_data;
unsigned long gpmc_base;
void __iomem *gpmc_base;
unsigned char wait_mon_mask;
uint64_t timeout;
unsigned inuse:1;
@ -672,7 +672,7 @@ static int gpmc_nand_probe(struct device_d *pdev)
struct gpmc_nand_platform_data *pdata;
struct nand_chip *nand;
struct mtd_info *minfo;
unsigned long cs_base;
void __iomem *cs_base;
int err;
struct nand_ecclayout *layout, *lsp, *llp;
@ -703,7 +703,7 @@ static int gpmc_nand_probe(struct device_d *pdev)
}
/* Setup register specific data */
oinfo->gpmc_cs = pdata->cs;
oinfo->gpmc_base = pdev->map_base;
oinfo->gpmc_base = dev_request_mem_region(pdev, 0);
cs_base = oinfo->gpmc_base + GPMC_CONFIG1_0 +
(pdata->cs * GPMC_CONFIG_CS_SIZE);
oinfo->gpmc_command = (void *)(cs_base + GPMC_CS_NAND_COMMAND);

4
drivers/mtd/nand/nand_s3c2410.c
View File

@ -422,7 +422,7 @@ static int s3c24x0_nand_probe(struct device_d *dev)
return -ENOMEM;
host->dev = dev;
host->base = IOMEM(dev->map_base);
host->base = dev_request_mem_region(dev, 0);
/* structures must be linked */
chip = &host->nand;
@ -435,7 +435,7 @@ static int s3c24x0_nand_probe(struct device_d *dev)
chip->chip_delay = 50;
chip->priv = host;
chip->IO_ADDR_R = chip->IO_ADDR_W = IOMEM(dev->map_base + NFDATA);
chip->IO_ADDR_R = chip->IO_ADDR_W = host->base + NFDATA;
#ifdef CONFIG_CPU_S3C2440
chip->read_buf = s3c2440_nand_read_buf;

23
include/driver.h
View File

@ -202,11 +202,30 @@ static inline void __iomem *dev_request_mem_region(struct device_d *dev, int num
return dev_get_mem_region(dev, num);
}
/*
* register a generic device
* with only one resource
*/
struct device_d *add_generic_device(const char* devname, int id, const char *resname,
resource_size_t start, resource_size_t size, unsigned int flags,
void *pdata);
/*
* register a memory device
*/
struct device_d *add_mem_device(const char *name, resource_size_t start,
resource_size_t size, unsigned int flags);
static inline struct device_d *add_mem_device(const char *name, resource_size_t start,
resource_size_t size, unsigned int flags)
{
return add_generic_device("mem", -1, name, start, size,
IORESOURCE_MEM | flags, NULL);
}
static inline struct device_d *add_cfi_flash_device(int id, resource_size_t start,
resource_size_t size, unsigned int flags)
{
return add_generic_device("cfi_flash", id, NULL, start, size,
IORESOURCE_MEM | flags, NULL);
}
/* linear list over all available devices
*/

2
lib/Makefile
View File

@ -5,8 +5,6 @@ obj-y += string.o
obj-y += vsprintf.o
obj-y += div64.o
obj-y += misc.o
obj-y += driver.o
obj-y += bus.o
obj-y += parameter.o
obj-y += xfuncs.o
obj-y += getopt.o