i2c-omap: cleanup cpu_is functions
cpu_is_omap2430() is set when CONFIG_ARCH_OMAP is enabled. This fits for all OMAP/AM33xx boards supported in barebox. Cleaned up all conditions that use the cpu_is_omap2430(). Also removed some unused defines. Signed-off-by: Teresa Gámez <t.gamez@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Teresa Gámez
Sascha Hauer
parent
d21e0c2762
commit
15f011138a
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@ -24,10 +24,6 @@
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* GNU General Public License for more details.
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*/
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/* #include <linux/delay.h> */
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#include <clock.h>
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#include <common.h>
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#include <driver.h>
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@ -44,12 +40,6 @@
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#include <mach/generic.h>
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#include <mach/omap3-clock.h>
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#define OMAP_I2C_SIZE 0x3f
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#define OMAP1_I2C_BASE 0xfffb3800
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#define OMAP2_I2C_BASE1 0x48070000
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#define OMAP2_I2C_BASE2 0x48072000
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#define OMAP2_I2C_BASE3 0x48060000
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/* This will be the driver name */
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#define DRIVER_NAME "i2c-omap"
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@ -141,7 +131,6 @@
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#define SYSC_IDLEMODE_SMART 0x2
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#define SYSC_CLOCKACTIVITY_FCLK 0x2
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struct omap_i2c_struct {
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void *base;
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u8 *regs;
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@ -352,63 +341,51 @@ static int omap_i2c_init(struct omap_i2c_struct *i2c_omap)
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}
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omap_i2c_write_reg(i2c_omap, OMAP_I2C_CON_REG, 0);
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/* omap1 handling is missing here */
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/*
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* HSI2C controller internal clk rate should be 19.2 Mhz for
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* HS and for all modes on 2430. On 34xx we can use lower rate
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* to get longer filter period for better noise suppression.
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* The filter is iclk (fclk for HS) period.
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*/
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if (i2c_omap->speed > 400)
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internal_clk = 19200;
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else if (i2c_omap->speed > 100)
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internal_clk = 9600;
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else
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internal_clk = 4000;
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fclk_rate = 96000000 / 1000;
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if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap4xxx()) {
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/* Compute prescaler divisor */
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psc = fclk_rate / internal_clk;
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psc = psc - 1;
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/*
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* HSI2C controller internal clk rate should be 19.2 Mhz for
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* HS and for all modes on 2430. On 34xx we can use lower rate
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* to get longer filter period for better noise suppression.
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* The filter is iclk (fclk for HS) period.
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*/
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if (i2c_omap->speed > 400 || cpu_is_omap2430())
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internal_clk = 19200;
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else if (i2c_omap->speed > 100)
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internal_clk = 9600;
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else
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internal_clk = 4000;
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fclk_rate = 96000000 / 1000;
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/* If configured for High Speed */
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if (i2c_omap->speed > 400) {
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unsigned long scl;
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/* Compute prescaler divisor */
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psc = fclk_rate / internal_clk;
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psc = psc - 1;
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/* For first phase of HS mode */
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scl = internal_clk / 400;
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fsscll = scl - (scl / 3) - 7;
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fssclh = (scl / 3) - 5;
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/* If configured for High Speed */
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if (i2c_omap->speed > 400) {
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unsigned long scl;
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/* For second phase of HS mode */
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scl = fclk_rate / i2c_omap->speed;
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hsscll = scl - (scl / 3) - 7;
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hssclh = (scl / 3) - 5;
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} else if (i2c_omap->speed > 100) {
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unsigned long scl;
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/* For first phase of HS mode */
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scl = internal_clk / 400;
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fsscll = scl - (scl / 3) - 7;
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fssclh = (scl / 3) - 5;
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/* For second phase of HS mode */
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scl = fclk_rate / i2c_omap->speed;
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hsscll = scl - (scl / 3) - 7;
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hssclh = (scl / 3) - 5;
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} else if (i2c_omap->speed > 100) {
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unsigned long scl;
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/* Fast mode */
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scl = internal_clk / i2c_omap->speed;
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fsscll = scl - (scl / 3) - 7;
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fssclh = (scl / 3) - 5;
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} else {
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/* Standard mode */
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fsscll = internal_clk / (i2c_omap->speed * 2) - 7;
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fssclh = internal_clk / (i2c_omap->speed * 2) - 5;
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}
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scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
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sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
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/* Fast mode */
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scl = internal_clk / i2c_omap->speed;
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fsscll = scl - (scl / 3) - 7;
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fssclh = (scl / 3) - 5;
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} else {
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/* Program desired operating rate */
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fclk_rate /= (psc + 1) * 1000;
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if (psc > 2)
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psc = 2;
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scll = fclk_rate / (i2c_omap->speed * 2) - 7 + psc;
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sclh = fclk_rate / (i2c_omap->speed * 2) - 7 + psc;
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/* Standard mode */
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fsscll = internal_clk / (i2c_omap->speed * 2) - 7;
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fssclh = internal_clk / (i2c_omap->speed * 2) - 5;
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}
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scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
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sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
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/* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
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omap_i2c_write_reg(i2c_omap, OMAP_I2C_PSC_REG, psc);
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@ -525,15 +502,6 @@ complete:
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if (dev->buf_len) {
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*dev->buf++ = w;
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dev->buf_len--;
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/* Data reg from 2430 is 8 bit wide */
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if (!cpu_is_omap2430() &&
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!cpu_is_omap34xx() &&
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!cpu_is_omap4xxx()) {
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if (dev->buf_len) {
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*dev->buf++ = w >> 8;
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dev->buf_len--;
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}
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}
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} else {
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if (stat & OMAP_I2C_STAT_RRDY)
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dev_err(&dev->adapter.dev,
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@ -566,15 +534,6 @@ complete:
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if (dev->buf_len) {
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w = *dev->buf++;
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dev->buf_len--;
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/* Data reg from 2430 is 8 bit wide */
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if (!cpu_is_omap2430() &&
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!cpu_is_omap34xx() &&
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!cpu_is_omap4xxx()) {
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if (dev->buf_len) {
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w |= *dev->buf++ << 8;
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dev->buf_len--;
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}
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}
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} else {
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if (stat & OMAP_I2C_STAT_XRDY)
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dev_err(&dev->adapter.dev,
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@ -776,6 +735,7 @@ i2c_omap_probe(struct device_d *pdev)
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/* struct i2c_platform_data *pdata; */
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int r;
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u32 speed = 0;
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u16 s;
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i2c_omap = kzalloc(sizeof(struct omap_i2c_struct), GFP_KERNEL);
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if (!i2c_omap) {
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@ -802,28 +762,23 @@ i2c_omap_probe(struct device_d *pdev)
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omap_i2c_unidle(i2c_omap);
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i2c_omap->rev = omap_i2c_read_reg(i2c_omap, OMAP_I2C_REV_REG) & 0xff;
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/* i2c_omap->base = OMAP2_I2C_BASE3; */
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if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap4xxx()) {
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u16 s;
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/* Set up the fifo size - Get total size */
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s = (omap_i2c_read_reg(i2c_omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
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i2c_omap->fifo_size = 0x8 << s;
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/* Set up the fifo size - Get total size */
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s = (omap_i2c_read_reg(i2c_omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
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i2c_omap->fifo_size = 0x8 << s;
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/*
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* Set up notification threshold as half the total available
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* size. This is to ensure that we can handle the status on int
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* call back latencies.
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*/
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/*
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* Set up notification threshold as half the total available
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* size. This is to ensure that we can handle the status on int
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* call back latencies.
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*/
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i2c_omap->fifo_size = (i2c_omap->fifo_size / 2);
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i2c_omap->fifo_size = (i2c_omap->fifo_size / 2);
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if (i2c_omap->rev >= OMAP_I2C_REV_ON_4430)
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i2c_omap->b_hw = 0; /* Disable hardware fixes */
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else
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i2c_omap->b_hw = 1; /* Enable hardware fixes */
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}
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if (i2c_omap->rev >= OMAP_I2C_REV_ON_4430)
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i2c_omap->b_hw = 0; /* Disable hardware fixes */
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else
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i2c_omap->b_hw = 1; /* Enable hardware fixes */
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/* reset ASAP, clearing any IRQs */
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omap_i2c_init(i2c_omap);
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