diff --git a/arch/arm/Makefile b/arch/arm/Makefile index a36adfb7e..fcb296966 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -69,6 +69,7 @@ machine-$(CONFIG_ARCH_TEGRA) := tegra # by CONFIG_* macro name. board-$(CONFIG_MACH_A9M2410) := a9m2410 board-$(CONFIG_MACH_A9M2440) := a9m2440 +board-$(CONFIG_MACH_ANIMEO_IP) := animeo_ip board-$(CONFIG_MACH_AT91RM9200EK) := at91rm9200ek board-$(CONFIG_MACH_AT91SAM9260EK) := at91sam9260ek board-$(CONFIG_MACH_AT91SAM9261EK) := at91sam9261ek @@ -77,7 +78,9 @@ board-$(CONFIG_MACH_AT91SAM9G10EK) := at91sam9261ek board-$(CONFIG_MACH_AT91SAM9G20EK) := at91sam9260ek board-$(CONFIG_MACH_AT91SAM9N12EK) := at91sam9n12ek board-$(CONFIG_MACH_AT91SAM9X5EK) := at91sam9x5ek +board-$(CONFIG_MACH_AT91SAM9M10IHD) := at91sam9m10ihd board-$(CONFIG_MACH_AT91SAM9M10G45EK) := at91sam9m10g45ek +board-$(CONFIG_MACH_SAMA5D3XEK) := sama5d3xek board-$(CONFIG_MACH_CLEP7212) := clep7212 board-$(CONFIG_MACH_DSS11) := dss11 board-$(CONFIG_MACH_EDB9301) := edb93xx @@ -94,6 +97,7 @@ board-$(CONFIG_MACH_EUKREA_CPUIMX35) := eukrea_cpuimx35 board-$(CONFIG_MACH_EUKREA_CPUIMX51SD) := eukrea_cpuimx51 board-$(CONFIG_MACH_FREESCALE_MX25_3STACK) := freescale-mx25-3-stack board-$(CONFIG_MACH_FREESCALE_MX35_3STACK) := freescale-mx35-3-stack +board-$(CONFIG_MACH_GE863) := telit-evk-pro3 board-$(CONFIG_MACH_IMX21ADS) := imx21ads board-$(CONFIG_MACH_IMX27ADS) := imx27ads board-$(CONFIG_MACH_IMX233_OLINUXINO) := imx233-olinuxino diff --git a/arch/arm/boards/animeo_ip/Makefile b/arch/arm/boards/animeo_ip/Makefile new file mode 100644 index 000000000..eb072c016 --- /dev/null +++ b/arch/arm/boards/animeo_ip/Makefile @@ -0,0 +1 @@ +obj-y += init.o diff --git a/arch/arm/boards/animeo_ip/config.h b/arch/arm/boards/animeo_ip/config.h new file mode 100644 index 000000000..006820cf2 --- /dev/null +++ b/arch/arm/boards/animeo_ip/config.h @@ -0,0 +1,6 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/animeo_ip/env/config b/arch/arm/boards/animeo_ip/env/config new file mode 100644 index 000000000..a0537b882 --- /dev/null +++ b/arch/arm/boards/animeo_ip/env/config @@ -0,0 +1,39 @@ +#!/bin/sh + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=dhcp-barebox +global.dhcp.vendor_id=barebox-animeo-ip + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d + +# can be either 'nfs', 'tftp', 'nor' or 'nand' +kernel_loc=nfs +# can be either 'net', 'nor', 'nand' or 'initrd' +rootfs_loc=net +# can be either 'nfs', 'tftp', 'nor', 'nand' or empty +oftree_loc=nfs + +# can be either 'jffs2' or 'ubifs' +rootfs_type=ubifs +rootfsimage=root.$rootfs_type + +kernelimage=zImage +#kernelimage=uImage +#kernelimage=Image +#kernelimage=Image.lzo + +nand_device=atmel_nand +nand_parts="32k(at91bootstrap),256k(barebox)ro,32k(bareboxenv),704k(user_block),1728k(kernel),-(root)" +rootfs_mtdblock_nand=5 + +autoboot_timeout=3 + +bootargs="console=ttyS1,38400n8 earlyprintk" + +# set a fancy prompt (if support is compiled in) +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m\n# " diff --git a/arch/arm/boards/animeo_ip/init.c b/arch/arm/boards/animeo_ip/init.c new file mode 100644 index 000000000..ada3bb044 --- /dev/null +++ b/arch/arm/boards/animeo_ip/init.c @@ -0,0 +1,251 @@ +/* + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + * + * Under GPLv2 only + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static bool animeo_ip_is_buco; +static bool animeo_ip_is_io; + +static int animeo_ip_get_pio_revision(int gpio, char *name) +{ + int ret; + + ret = gpio_request(gpio, name); + if (ret) { + pr_err("animeo_ip: can not request gpio %d as %s (%d)\n", + gpio, name, ret); + return ret; + } + + ret = gpio_direction_input(gpio); + + if (ret) { + pr_err("animeo_ip: can configure gpio %d (%s) as input (%d)\n", + gpio, name, ret); + return ret; + } + + return gpio_get_value(gpio); +} + +static void animeo_ip_detect_version(void) +{ + struct device_d *dev = NULL; + char *model, *version; + int val; + + animeo_ip_is_io = false; + animeo_ip_is_buco = false; + model = "SubCo"; + version = "SDN"; + + dev = add_generic_device_res("animeo_ip", DEVICE_ID_SINGLE, NULL, 0, NULL); + + val = animeo_ip_get_pio_revision(AT91_PIN_PC20, "is_buco"); + if (val < 0) { + pr_warn("Can not detect model use %s by default\n", model); + } else if (val) { + animeo_ip_is_buco = true; + model = "SubCo"; + } + + val = animeo_ip_get_pio_revision(AT91_PIN_PC21, "is_io"); + if (val < 0) { + pr_warn("Can not detect version use %s by default\n", model); + } else if (val) { + animeo_ip_is_io = true; + version = "IO"; + } + + dev_add_param_fixed(dev, "model", model); + dev_add_param_fixed(dev, "version", version); +} + +static struct atmel_nand_data nand_pdata = { + .ale = 21, + .cle = 22, + .det_pin = -EINVAL, + .rdy_pin = AT91_PIN_PC13, + .enable_pin = AT91_PIN_PC14, + .bus_width_16 = 0, + .on_flash_bbt = 1, +}; + +static struct sam9_smc_config animeo_ip_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 3, + .nrd_pulse = 3, + .ncs_write_pulse = 3, + .nwe_pulse = 3, + + .read_cycle = 5, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, + .tdf_cycles = 2, +}; + +static void animeo_ip_add_device_nand(void) +{ + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(0, 3, &animeo_ip_nand_smc_config); + + at91_add_device_nand(&nand_pdata); +} + +static struct at91_ether_platform_data macb_pdata = { + .phy_addr = 0, +}; + +/* + * MCI (SD/MMC) + */ +#if defined(CONFIG_MCI_ATMEL) +static struct atmel_mci_platform_data __initdata animeo_ip_mci_data = { + .bus_width = 4, + .slot_b = 1, + .detect_pin = -EINVAL, + .wp_pin = -EINVAL, +}; + +static void animeo_ip_add_device_mci(void) +{ + at91_add_device_mci(0, &animeo_ip_mci_data); +} +#else +static void animeo_ip_add_device_mci(void) {} +#endif + +struct gpio_bicolor_led leds[] = { + { + .gpio_c0 = AT91_PIN_PC17, + .gpio_c1 = AT91_PIN_PA2, + .led = { + .name = "power_red_green", + }, + }, { + .gpio_c0 = AT91_PIN_PC19, + .gpio_c1 = AT91_PIN_PC18, + .led = { + .name = "tx_greem_rx_yellow", + }, + }, +}; + +static void __init animeo_ip_add_device_led(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(leds); i++) { + at91_set_gpio_output(leds[i].gpio_c0, leds[i].active_low); + at91_set_gpio_output(leds[i].gpio_c1, leds[i].active_low); + led_gpio_bicolor_register(&leds[i]); + } + led_set_trigger(LED_TRIGGER_HEARTBEAT, &leds[0].led); +} + +static int animeo_ip_mem_init(void) +{ + at91_add_device_sdram(0); + + return 0; +} +mem_initcall(animeo_ip_mem_init); + +static void animeo_export_gpio_in(int gpio, const char *name) +{ + at91_set_gpio_input(gpio, 0); + at91_set_deglitch(gpio, 1); + export_env_ull(name, gpio); +} + +static void animeo_ip_add_device_buttons(void) +{ + animeo_export_gpio_in(AT91_PIN_PB1, "keyswitch_in"); + animeo_export_gpio_in(AT91_PIN_PB2, "error_in"); + animeo_export_gpio_in(AT91_PIN_PC22, "jumper"); + animeo_export_gpio_in(AT91_PIN_PC23, "btn"); +} + +static void animeo_export_gpio_out(int gpio, const char *name) +{ + at91_set_gpio_output(gpio, 0); + export_env_ull(name, gpio); +} + +static void animeo_ip_power_control(void) +{ + animeo_export_gpio_out(AT91_PIN_PB0, "power_radio"); + animeo_export_gpio_out(AT91_PIN_PB3, "error_out_relay"); + animeo_export_gpio_out(AT91_PIN_PC4, "power_save"); +} + +static int animeo_ip_devices_init(void) +{ + animeo_ip_detect_version(); + animeo_ip_power_control(); + animeo_ip_add_device_nand(); + at91_add_device_eth(0, &macb_pdata); + animeo_ip_add_device_mci(); + animeo_ip_add_device_buttons(); + animeo_ip_add_device_led(); + + armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100)); + /* + * in production the machine id used is the cpu module machine id + * PICOCOM1 + */ + armlinux_set_architecture(MACH_TYPE_PICOCOM1); + + devfs_add_partition("nand0", 0x00000, SZ_32K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw"); + dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap"); + devfs_add_partition("nand0", SZ_32K, SZ_256K, DEVFS_PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", SZ_256K + SZ_32K, SZ_32K, DEVFS_PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + + return 0; +} + +device_initcall(animeo_ip_devices_init); + +static int animeo_ip_console_init(void) +{ + /* + * disable the dbgu enable by the bootstrap + * so linux can detect that we only enable the uart2 + * and use it for decompress + */ +#define ATMEL_US_BRGR 0x0020 + at91_sys_write(AT91_DBGU + ATMEL_US_BRGR, 0); + at91_register_uart(3, 0); + return 0; +} +console_initcall(animeo_ip_console_init); diff --git a/arch/arm/boards/at91rm9200ek/init.c b/arch/arm/boards/at91rm9200ek/init.c index 0a360ae70..eec71bb07 100644 --- a/arch/arm/boards/at91rm9200ek/init.c +++ b/arch/arm/boards/at91rm9200ek/init.c @@ -33,13 +33,13 @@ #include static struct at91_ether_platform_data ether_pdata = { - .is_rmii = 1, + .phy_interface = PHY_INTERFACE_MODE_RMII, .phy_addr = 0, }; static int at91rm9200ek_mem_init(void) { - at91_add_device_sdram(32 * 1024 * 1024); + at91_add_device_sdram(0); return 0; } diff --git a/arch/arm/boards/at91sam9260ek/init.c b/arch/arm/boards/at91sam9260ek/init.c index 7bd02793b..2d52f5a3f 100644 --- a/arch/arm/boards/at91sam9260ek/init.c +++ b/arch/arm/boards/at91sam9260ek/init.c @@ -127,7 +127,7 @@ static void ek_add_device_nand(void) } static struct at91_ether_platform_data macb_pdata = { - .is_rmii = 1, + .phy_interface = PHY_INTERFACE_MODE_RMII, .phy_addr = 0, }; diff --git a/arch/arm/boards/at91sam9261ek/Makefile b/arch/arm/boards/at91sam9261ek/Makefile index eb072c016..b6460c398 100644 --- a/arch/arm/boards/at91sam9261ek/Makefile +++ b/arch/arm/boards/at91sam9261ek/Makefile @@ -1 +1,5 @@ obj-y += init.o + +obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o + +pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o diff --git a/arch/arm/boards/at91sam9261ek/env/bin/init_board b/arch/arm/boards/at91sam9261ek/env/bin/init_board index a76a660ab..8e849c6a6 100644 --- a/arch/arm/boards/at91sam9261ek/env/bin/init_board +++ b/arch/arm/boards/at91sam9261ek/env/bin/init_board @@ -1,5 +1,12 @@ #!/bin/sh +splash=/env/splash.png + +if [ -f ${splash} -a -e /dev/fb0 ]; then + splash -o ${splash} + fb0.enable=1 +fi + button_name="dfu_bp" button_wait=5 diff --git a/arch/arm/boards/at91sam9261ek/env/config b/arch/arm/boards/at91sam9261ek/env/config index 7d855779c..cb3e847f5 100644 --- a/arch/arm/boards/at91sam9261ek/env/config +++ b/arch/arm/boards/at91sam9261ek/env/config @@ -34,8 +34,14 @@ kernelimage=zImage #kernelimage=Image.lzo nand_device=atmel_nand -nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),128k(oftree),4M(kernel),120M(rootfs),-(data)" -rootfs_mtdblock_nand=6 +if [ x$borebox_first_stage = x1 ] +then + nand_parts="384k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),128k(oftree),4M(kernel),120M(rootfs),-(data)" + rootfs_mtdblock_nand=5 +else + nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),128k(oftree),4M(kernel),120M(rootfs),-(data)" + rootfs_mtdblock_nand=6 +fi autoboot_timeout=3 diff --git a/arch/arm/boards/at91sam9261ek/init.c b/arch/arm/boards/at91sam9261ek/init.c index 7c95435c8..177bb3427 100644 --- a/arch/arm/boards/at91sam9261ek/init.c +++ b/arch/arm/boards/at91sam9261ek/init.c @@ -30,13 +30,14 @@ #include #include #include -#include +#include #include #include #include #include #include #include +#include static struct atmel_nand_data nand_pdata = { .ale = 22, @@ -149,6 +150,86 @@ static void ek_add_device_udc(void) static void ek_add_device_udc(void) {} #endif +/* + * LCD Controller + */ +#if defined(CONFIG_DRIVER_VIDEO_ATMEL) +static int ek_gpio_request_output(int gpio, const char *name) +{ + int ret; + + ret = gpio_request(gpio, name); + if (ret) { + pr_err("%s: can not request gpio %d (%d)\n", name, gpio, ret); + return ret; + } + + ret = gpio_direction_output(gpio, 1); + if (ret) + pr_err("%s: can not configure gpio %d as output (%d)\n", name, gpio, ret); + return ret; +} + +/* TFT */ +static struct fb_videomode at91_tft_vga_modes[] = { + { + .name = "TX09D50VM1CCA @ 60", + .refresh = 60, + .xres = 240, .yres = 320, + .pixclock = KHZ2PICOS(4965), + + .left_margin = 1, .right_margin = 33, + .upper_margin = 1, .lower_margin = 0, + .hsync_len = 5, .vsync_len = 1, + + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +#define AT91SAM9261_DEFAULT_TFT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \ + | ATMEL_LCDC_DISTYPE_TFT \ + | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) + +static void at91_lcdc_tft_power_control(int on) +{ + if (on) + gpio_set_value(AT91_PIN_PA12, 0); /* power up */ + else + gpio_set_value(AT91_PIN_PA12, 1); /* power down */ +} + +static struct atmel_lcdfb_platform_data ek_lcdc_data = { + .lcdcon_is_backlight = true, + .default_bpp = 16, + .default_dmacon = ATMEL_LCDC_DMAEN, + .default_lcdcon2 = AT91SAM9261_DEFAULT_TFT_LCDCON2, + .guard_time = 1, + .atmel_lcdfb_power_control = at91_lcdc_tft_power_control, + .mode_list = at91_tft_vga_modes, + .num_modes = ARRAY_SIZE(at91_tft_vga_modes), +}; + +static int at91_lcdc_gpio(void) +{ + return ek_gpio_request_output(AT91_PIN_PA12, "lcdc_tft_power"); +} + +static void ek_add_device_lcdc(void) +{ + if (at91_lcdc_gpio()) + return; + + if (machine_is_at91sam9g10ek()) + ek_lcdc_data.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB; + + at91_add_device_lcdc(&ek_lcdc_data); +} + +#else +static void ek_add_device_lcdc(void) {} +#endif + #ifdef CONFIG_KEYBOARD_GPIO struct gpio_keys_button keys[] = { { @@ -229,6 +310,46 @@ static void ek_device_add_leds(void) static void ek_device_add_leds(void) {} #endif +/* + * SPI related devices + */ +#if defined(CONFIG_DRIVER_SPI_ATMEL) +/* + * SPI devices + */ +static struct spi_board_info ek_spi_devices[] = { + { /* DataFlash chip */ + .name = "mtd_dataflash", + .chip_select = 0, + .max_speed_hz = 15 * 1000 * 1000, + .bus_num = 0, + }, +#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD) + { /* DataFlash card - jumper (J12) configurable to CS3 or CS0 */ + .name = "mtd_dataflash", + .chip_select = 1, + .max_speed_hz = 15 * 1000 * 1000, + .bus_num = 0, + }, +#endif +}; + +static unsigned spi0_standard_cs[] = { AT91_PIN_PA3, AT91_PIN_PA6}; +static struct at91_spi_platform_data spi_pdata = { + .chipselect = spi0_standard_cs, + .num_chipselect = ARRAY_SIZE(spi0_standard_cs), +}; + +static void ek_add_device_spi(void) +{ + spi_register_board_info(ek_spi_devices, + ARRAY_SIZE(ek_spi_devices)); + at91_add_device_spi(0, &spi_pdata); +} +#else +static void ek_add_device_spi(void) {} +#endif + static int at91sam9261ek_mem_init(void) { at91_add_device_sdram(0); @@ -239,15 +360,28 @@ mem_initcall(at91sam9261ek_mem_init); static int at91sam9261ek_devices_init(void) { + u32 barebox_part_start; + u32 barebox_part_size; ek_add_device_nand(); ek_add_device_dm9000(); ek_add_device_udc(); ek_add_device_buttons(); ek_device_add_leds(); + ek_add_device_lcdc(); + ek_add_device_spi(); - devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw"); - devfs_add_partition("nand0", SZ_128K, SZ_256K, DEVFS_PARTITION_FIXED, "self_raw"); + if (IS_ENABLED(CONFIG_AT91_LOAD_BAREBOX_SRAM)) { + barebox_part_start = 0; + barebox_part_size = SZ_256K + SZ_128K; + export_env_ull("borebox_first_stage", 1); + } else { + devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw"); + barebox_part_start = SZ_128K; + barebox_part_size = SZ_256K; + } + devfs_add_partition("nand0", barebox_part_start, barebox_part_size, + DEVFS_PARTITION_FIXED, "self_raw"); dev_add_bb_dev("self_raw", "self0"); devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw"); dev_add_bb_dev("env_raw", "env0"); diff --git a/arch/arm/boards/at91sam9261ek/lowlevel_init.c b/arch/arm/boards/at91sam9261ek/lowlevel_init.c new file mode 100644 index 000000000..056584166 --- /dev/null +++ b/arch/arm/boards/at91sam9261ek/lowlevel_init.c @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD + * + * Under GPLv2 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MASTER_CLOCK 200 + +#if MASTER_CLOCK == 200 +#define MASTER_PLL_MUL 162 +#define MASTER_PLL_DIV 15 +#elif MASTER_CLOCK == 239 +#define MASTER_PLL_MUL 13 +#define MASTER_PLL_DIV 1 +#endif + +void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg) +{ + /* Disable Watchdog */ + cfg->wdt_mr = + AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | + AT91_WDT_WDV | + AT91_WDT_WDDIS | + AT91_WDT_WDD; + + /* define PDC[31:16] as DATA[31:16] */ + cfg->ebi_pio_pdr = 0xFFFF0000; + /* no pull-up for D[31:16] */ + cfg->ebi_pio_ppudr = 0xFFFF0000; + /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ + cfg->ebi_csa = + AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC; + + cfg->smc_cs = 3; + cfg->smc_mode = + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_DBW_8 | + AT91_SMC_EXNWMODE_DISABLE | + AT91_SMC_TDF_(2); + cfg->smc_cycle = + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5); + cfg->smc_pulse = + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3); + cfg->smc_setup = + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0); + + cfg->pmc_mor = + AT91_PMC_MOSCEN | + (255 << 8); /* Main Oscillator Start-up Time */ + cfg->pmc_pllar = + AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ + AT91_PMC_OUT | + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV); + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr1 = + AT91_PMC_CSS_SLOW | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr2 = + AT91_PMC_CSS_PLLA | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + + /* SDRAM */ + /* SDRAMC_TR - Refresh Timer register */ + cfg->sdrc_tr1 = 0x13C; + /* SDRAMC_CR - Configuration register*/ + cfg->sdrc_cr = + AT91_SDRAMC_NC_9 | + AT91_SDRAMC_NR_13 | + AT91_SDRAMC_NB_4 | + AT91_SDRAMC_CAS_2 | + AT91_SDRAMC_DBW_32 | + (2 << 8) | /* Write Recovery Delay */ + (7 << 12) | /* Row Cycle Delay */ + (2 << 16) | /* Row Precharge Delay */ + (2 << 20) | /* Row to Column Delay */ + (5 << 24) | /* Active to Precharge Delay */ + (8 << 28); /* Exit Self Refresh to Active Delay */ + + /* Memory Device Register -> SDRAM */ + cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM; + /* SDRAM_TR */ + cfg->sdrc_tr2 = (MASTER_CLOCK * 7); + + /* user reset enable */ + cfg->rstc_rmr = + AT91_RSTC_KEY | + AT91_RSTC_PROCRST | + AT91_RSTC_RSTTYP_WAKEUP | + AT91_RSTC_RSTTYP_WATCHDOG; +} diff --git a/arch/arm/boards/at91sam9263ek/Makefile b/arch/arm/boards/at91sam9263ek/Makefile index eb072c016..b6460c398 100644 --- a/arch/arm/boards/at91sam9263ek/Makefile +++ b/arch/arm/boards/at91sam9263ek/Makefile @@ -1 +1,5 @@ obj-y += init.o + +obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o + +pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o diff --git a/arch/arm/boards/at91sam9263ek/config.h b/arch/arm/boards/at91sam9263ek/config.h index 14eb4fe24..cc12040e8 100644 --- a/arch/arm/boards/at91sam9263ek/config.h +++ b/arch/arm/boards/at91sam9263ek/config.h @@ -3,91 +3,4 @@ #define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ -#define MASTER_PLL_MUL 171 -#define MASTER_PLL_DIV 14 - -/* clocks */ -#define CONFIG_SYS_MOR_VAL \ - (AT91_PMC_MOSCEN | \ - (255 << 8)) /* Main Oscillator Start-up Time */ -#define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ - AT91_PMC_OUT | \ - AT91_PMC_PLLCOUNT | /* PLL Counter */ \ - (2 << 28) | /* PLL Clock Frequency Range */ \ - ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) - -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_CSS_SLOW | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_CSS_PLLA | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) - -/* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 -/* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 -/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ -#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ - (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \ - AT91_MATRIX_EBI0_CS1A_SDRAMC) - -/* SDRAM */ -/* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x13C -/* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ - (AT91_SDRAMC_NC_9 | \ - AT91_SDRAMC_NR_13 | \ - AT91_SDRAMC_NB_4 | \ - AT91_SDRAMC_CAS_3 | \ - AT91_SDRAMC_DBW_32 | \ - (1 << 8) | /* Write Recovery Delay */ \ - (7 << 12) | /* Row Cycle Delay */ \ - (2 << 16) | /* Row Precharge Delay */ \ - (2 << 20) | /* Row to Column Delay */ \ - (5 << 24) | /* Active to Precharge Delay */ \ - (1 << 28)) /* Exit Self Refresh to Active Delay */ - -/* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ - -/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC_CS 0 -#define CONFIG_SYS_SMC_SETUP_VAL \ - (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ - AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) -#define CONFIG_SYS_SMC_PULSE_VAL \ - (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ - AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) -#define CONFIG_SYS_SMC_CYCLE_VAL \ - (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) -#define CONFIG_SYS_SMC_MODE_VAL \ - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ - AT91_SMC_DBW_16 | \ - AT91_SMC_TDFMODE | \ - AT91_SMC_TDF_(6)) - -/* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ - (AT91_RSTC_KEY | \ - AT91_RSTC_PROCRST | \ - AT91_RSTC_RSTTYP_WAKEUP | \ - AT91_RSTC_RSTTYP_WATCHDOG) - -/* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ - (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ - AT91_WDT_WDV | \ - AT91_WDT_WDDIS | \ - AT91_WDT_WDD) - #endif /* __CONFIG_H */ diff --git a/arch/arm/boards/at91sam9263ek/env/bin/init_board b/arch/arm/boards/at91sam9263ek/env/bin/init_board index ae2ac7d76..f2e629464 100644 --- a/arch/arm/boards/at91sam9263ek/env/bin/init_board +++ b/arch/arm/boards/at91sam9263ek/env/bin/init_board @@ -1,5 +1,12 @@ #!/bin/sh +splash=/env/splash.png + +if [ -f ${splash} -a -e /dev/fb0 ]; then + splash -o ${splash} + fb0.enable=1 +fi + button_name="dfu_bp" button_wait=5 diff --git a/arch/arm/boards/at91sam9263ek/init.c b/arch/arm/boards/at91sam9263ek/init.c index a86c0fd51..90fdbeca7 100644 --- a/arch/arm/boards/at91sam9263ek/init.c +++ b/arch/arm/boards/at91sam9263ek/init.c @@ -32,7 +32,7 @@ #include #include #include -#include +#include #include #include @@ -83,7 +83,7 @@ static void ek_add_device_nand(void) } static struct at91_ether_platform_data macb_pdata = { - .is_rmii = 1, + .phy_interface = PHY_INTERFACE_MODE_RMII, .phy_addr = 0, }; @@ -149,6 +149,75 @@ static void ek_add_device_udc(void) static void ek_add_device_udc(void) {} #endif +/* + * LCD Controller + */ +#if defined(CONFIG_DRIVER_VIDEO_ATMEL) +static int ek_gpio_request_output(int gpio, const char *name) +{ + int ret; + + ret = gpio_request(gpio, name); + if (ret) { + pr_err("%s: can not request gpio %d (%d)\n", name, gpio, ret); + return ret; + } + + ret = gpio_direction_output(gpio, 1); + if (ret) + pr_err("%s: can not configure gpio %d as output (%d)\n", name, gpio, ret); + return ret; +} + +static struct fb_videomode at91_tft_vga_modes[] = { + { + .name = "TX09D50VM1CCA @ 60", + .refresh = 60, + .xres = 240, .yres = 320, + .pixclock = KHZ2PICOS(4965), + + .left_margin = 1, .right_margin = 33, + .upper_margin = 1, .lower_margin = 0, + .hsync_len = 5, .vsync_len = 1, + + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +#define AT91SAM9263_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \ + | ATMEL_LCDC_DISTYPE_TFT \ + | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) + +static void at91_lcdc_power_control(int on) +{ + gpio_set_value(AT91_PIN_PA30, on); +} + +/* Driver datas */ +static struct atmel_lcdfb_platform_data ek_lcdc_data = { + .lcdcon_is_backlight = true, + .default_bpp = 16, + .default_dmacon = ATMEL_LCDC_DMAEN, + .default_lcdcon2 = AT91SAM9263_DEFAULT_LCDCON2, + .guard_time = 1, + .atmel_lcdfb_power_control = at91_lcdc_power_control, + .mode_list = at91_tft_vga_modes, + .num_modes = ARRAY_SIZE(at91_tft_vga_modes), +}; + +static void ek_add_device_lcdc(void) +{ + if (ek_gpio_request_output(AT91_PIN_PA30, "lcdc_power")) + return; + + at91_add_device_lcdc(&ek_lcdc_data); +} + +#else +static void ek_add_device_lcdc(void) {} +#endif + static void __init ek_add_device_buttons(void) { at91_set_gpio_input(AT91_PIN_PC5, 1); @@ -184,6 +253,7 @@ static int at91sam9263ek_devices_init(void) ek_device_add_leds(); ek_add_device_udc(); ek_add_device_buttons(); + ek_add_device_lcdc(); if (IS_ENABLED(CONFIG_DRIVER_CFI) && cdev_by_name("nor0")) { devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self"); diff --git a/arch/arm/boards/at91sam9263ek/lowlevel_init.c b/arch/arm/boards/at91sam9263ek/lowlevel_init.c new file mode 100644 index 000000000..2f8b312d3 --- /dev/null +++ b/arch/arm/boards/at91sam9263ek/lowlevel_init.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD + * + * Under GPLv2 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MASTER_PLL_MUL 171 +#define MASTER_PLL_DIV 14 + +void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg) +{ + /* Disable Watchdog */ + cfg->wdt_mr = + AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | + AT91_WDT_WDV | + AT91_WDT_WDDIS | + AT91_WDT_WDD; + + /* define PDC[31:16] as DATA[31:16] */ + cfg->ebi_pio_pdr = 0xFFFF0000; + /* no pull-up for D[31:16] */ + cfg->ebi_pio_ppudr = 0xFFFF0000; + /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ + cfg->ebi_csa = + AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | + AT91_MATRIX_EBI0_CS1A_SDRAMC; + + cfg->smc_cs = 0; + cfg->smc_mode = + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_DBW_16 | + AT91_SMC_TDFMODE | + AT91_SMC_TDF_(6); + cfg->smc_cycle = + AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22); + cfg->smc_pulse = + AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | + AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11); + cfg->smc_setup = + AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | + AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10); + + cfg->pmc_mor = + AT91_PMC_MOSCEN | + (255 << 8); /* Main Oscillator Start-up Time */ + cfg->pmc_pllar = + AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ + AT91_PMC_OUT | + AT91_PMC_PLLCOUNT | /* PLL Counter */ + (2 << 28) | /* PLL Clock Frequency Range */ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV); + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr1 = + AT91_PMC_CSS_SLOW | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr2 = + AT91_PMC_CSS_PLLA | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + + /* SDRAM */ + /* SDRAMC_TR - Refresh Timer register */ + cfg->sdrc_tr1 = 0x13C; + /* SDRAMC_CR - Configuration register*/ + cfg->sdrc_cr = + AT91_SDRAMC_NC_9 | + AT91_SDRAMC_NR_13 | + AT91_SDRAMC_NB_4 | + AT91_SDRAMC_CAS_3 | + AT91_SDRAMC_DBW_32 | + (1 << 8) | /* Write Recovery Delay */ + (7 << 12) | /* Row Cycle Delay */ + (2 << 16) | /* Row Precharge Delay */ + (2 << 20) | /* Row to Column Delay */ + (5 << 24) | /* Active to Precharge Delay */ + (1 << 28); /* Exit Self Refresh to Active Delay */ + + /* Memory Device Register -> SDRAM */ + cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM; + /* SDRAM_TR */ + cfg->sdrc_tr2 = 1200; + + /* user reset enable */ + cfg->rstc_rmr = + AT91_RSTC_KEY | + AT91_RSTC_PROCRST | + AT91_RSTC_RSTTYP_WAKEUP | + AT91_RSTC_RSTTYP_WATCHDOG; +} diff --git a/arch/arm/boards/at91sam9m10g45ek/env/bin/boot_board b/arch/arm/boards/at91sam9m10g45ek/env/bin/boot_board index 3d7426f52..73daecc00 100644 --- a/arch/arm/boards/at91sam9m10g45ek/env/bin/boot_board +++ b/arch/arm/boards/at91sam9m10g45ek/env/bin/boot_board @@ -5,6 +5,13 @@ export PATH . /env/config +splash=/env/splash.png + +if [ -f ${splash} -a -e /dev/fb0 ]; then + splash -o ${splash} + fb0.enable=1 +fi + menu -r -m boot menu -a -m boot -d "\e[1;36mWelcome on Barebox Boot Sequence\e[0m" menu -e -a -m boot -c 'menu_boot' -d "boot (default) " diff --git a/arch/arm/boards/at91sam9m10g45ek/init.c b/arch/arm/boards/at91sam9m10g45ek/init.c index 053c85b43..5b5e31b55 100644 --- a/arch/arm/boards/at91sam9m10g45ek/init.c +++ b/arch/arm/boards/at91sam9m10g45ek/init.c @@ -106,7 +106,7 @@ static void ek_add_device_nand(void) } static struct at91_ether_platform_data macb_pdata = { - .is_rmii = 1, + .phy_interface = PHY_INTERFACE_MODE_RMII, .phy_addr = 0, }; @@ -208,21 +208,84 @@ static void ek_device_add_keyboard(void) static void ek_device_add_keyboard(void) {} #endif +#if defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI) +/* + * USB HS Host port (common to OHCI & EHCI) + */ +static struct at91_usbh_data ek_usbh_hs_data = { + .ports = 2, + .vbus_pin = {AT91_PIN_PD1, AT91_PIN_PD3}, + .vbus_pin_active_low = {1, 1}, +}; + +static void ek_add_device_usb(void) +{ + at91_add_device_usbh_ohci(&ek_usbh_hs_data); + at91_add_device_usbh_ehci(&ek_usbh_hs_data); +} +#else +static void ek_add_device_usb(void) {} +#endif + static int at91sam9m10g45ek_mem_init(void) { - at91_add_device_sdram(128 * 1024 * 1024); + at91_add_device_sdram(0); return 0; } mem_initcall(at91sam9m10g45ek_mem_init); +#if defined(CONFIG_DRIVER_VIDEO_ATMEL) +static struct fb_videomode at91_tft_vga_modes[] = { + { + .name = "LG", + .refresh = 60, + .xres = 480, .yres = 272, + .pixclock = KHZ2PICOS(9000), + + .left_margin = 1, .right_margin = 1, + .upper_margin = 40, .lower_margin = 1, + .hsync_len = 45, .vsync_len = 1, + + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +#define AT91SAM9G45_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \ + | ATMEL_LCDC_DISTYPE_TFT \ + | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) + +/* Driver datas */ +static struct atmel_lcdfb_platform_data ek_lcdc_data = { + .lcdcon_is_backlight = true, + .default_bpp = 32, + .default_dmacon = ATMEL_LCDC_DMAEN, + .default_lcdcon2 = AT91SAM9G45_DEFAULT_LCDCON2, + .guard_time = 9, + .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, + .mode_list = at91_tft_vga_modes, + .num_modes = ARRAY_SIZE(at91_tft_vga_modes), +}; +static void ek_add_device_lcdc(void) +{ + at91_add_device_lcdc(&ek_lcdc_data); +} + +#else +static void ek_add_device_lcdc(void) {} +#endif + + static int at91sam9m10g45ek_devices_init(void) { ek_add_device_nand(); at91_add_device_eth(0, &macb_pdata); ek_add_device_mci(); + ek_add_device_usb(); ek_device_add_leds(); ek_device_add_keyboard(); + ek_add_device_lcdc(); devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw"); dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap"); diff --git a/arch/arm/boards/at91sam9m10ihd/Makefile b/arch/arm/boards/at91sam9m10ihd/Makefile new file mode 100644 index 000000000..f2acf201b --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/Makefile @@ -0,0 +1,2 @@ +obj-y += init.o +obj-y += hw_version.o diff --git a/arch/arm/boards/at91sam9m10ihd/config.h b/arch/arm/boards/at91sam9m10ihd/config.h new file mode 100644 index 000000000..ac3114d86 --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/config.h @@ -0,0 +1,6 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/at91sam9m10ihd/env/boot/android b/arch/arm/boards/at91sam9m10ihd/env/boot/android new file mode 100644 index 000000000..e440f1806 --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/boot/android @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "android (nand)" + exit +fi + +global.bootm.image="/dev/nand0.kernel.bb" +global.linux.bootargs.dyn.root="root=/dev/mtdblock1 rootfstype=jffs2 rw init=/init rootdelay=1" +# clean the mtdparts otherwise android does not boot +global -r linux.mtdparts. diff --git a/arch/arm/boards/at91sam9m10ihd/env/boot/mmc b/arch/arm/boards/at91sam9m10ihd/env/boot/mmc new file mode 100644 index 000000000..89c66ee8f --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/boot/mmc @@ -0,0 +1,19 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "MMC slot" + exit +fi + +path="/mnt/mmc" + +global.bootm.image="${path}/zimage" + +oftree=${path}/oftree +if [ -f $oftree ]; then + global.bootm.oftree="$oftree" +fi + +# The rootdevice may actually be mmcblk1p2 if a card +# is inserted to the back MMC slot +global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2" diff --git a/arch/arm/boards/at91sam9m10ihd/env/boot/net b/arch/arm/boards/at91sam9m10ihd/env/boot/net new file mode 100644 index 000000000..cdb2520d3 --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/boot/net @@ -0,0 +1,16 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "network (tftp, nfs) (macb)" + exit +fi + +ethact eth0 + +path="/mnt/tftp" + +global.bootm.image="${path}/${global.user}-linux-${global.hostname}" +#global.bootm.oftree="${path}/${global.user}-oftree-${global.hostname}" +nfsroot="/home/${global.user}/nfsroot/${global.hostname}" +bootargs-ip +global.linux.bootargs.dyn.root="root=/dev/nfs nfsroot=$nfsroot,v3,tcp" diff --git a/arch/arm/boards/at91sam9m10ihd/env/boot/net-usb b/arch/arm/boards/at91sam9m10ihd/env/boot/net-usb new file mode 100644 index 000000000..6e341a011 --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/boot/net-usb @@ -0,0 +1,22 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "network (tftp, nfs) (usb ethernet)" + exit +fi + +usb -f +ethact eth1 + +if [ $? -ne 0 ]; then + echo "ERROR: usb ethernet not found" + exit 1 +fi + +path="/mnt/tftp" + +global.bootm.image="${path}/${global.user}-linux-${global.hostname}" +#global.bootm.oftree="${path}/${global.user}-oftree-${global.hostname}" +nfsroot="/home/${global.user}/nfsroot/${global.hostname}" +bootargs-ip +global.linux.bootargs.dyn.root="root=/dev/nfs nfsroot=$nfsroot,v3,tcp" diff --git a/arch/arm/boards/at91sam9m10ihd/env/config b/arch/arm/boards/at91sam9m10ihd/env/config new file mode 100644 index 000000000..bc2119ee9 --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/config @@ -0,0 +1,21 @@ +#!/bin/sh + +# change network settings in /env/network/eth0 +# change mtd partition settings and automountpoints in /env/init/* + +#global.hostname= + +# set to false if you do not want to have colors +global.allow_color=true + +# user (used for network filenames) +global.user=none + +# timeout in seconds before the default boot entry is started +global.autoboot_timeout=3 + +# default boot entry (one of /env/boot/*) +global.boot.default=android + +# base bootargs +#global.linux.bootargs.base="console=ttyS0,115200" diff --git a/arch/arm/boards/at91sam9m10ihd/env/init/automount b/arch/arm/boards/at91sam9m10ihd/env/init/automount new file mode 100644 index 000000000..5bb63ccb9 --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/init/automount @@ -0,0 +1,17 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "Automountpoints" + exit +fi + +# automount tftp server based on $eth0.serverip + +mkdir -p /mnt/tftp +automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp' + +# automount nfs server example + +# SD card slot, first partition +mkdir -p /mnt/mmc +automount -d /mnt/mmc 'mount /dev/disk0.0 /mnt/mmc' diff --git a/arch/arm/boards/at91sam9m10ihd/env/init/config-board b/arch/arm/boards/at91sam9m10ihd/env/init/config-board new file mode 100644 index 000000000..32c107130 --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/init/config-board @@ -0,0 +1,8 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.hostname=at91sam9m10ihd +global.linux.bootargs.base="console=ttyS0,115200" +global.boot.default=android diff --git a/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-001-nand b/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-001-nand new file mode 100644 index 000000000..ac516d82d --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-001-nand @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "NAND partitions" + exit +fi + +mtdparts="128k(nand0.at91bootstrap),256k(nand0.barebox)ro,128k(nand0.bareboxenv),128k(nand0.bareboxenv2),128k(nand0.oftree),1280k(nand0.free),3M(nand0.kernel),195M(nand0.rootfs),300M(nand0.userdata),-(nand0.cache)" +kernelname="atmel_nand" + +mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-002-m25p80 b/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-002-m25p80 new file mode 100644 index 000000000..44198c820 --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-002-m25p80 @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "SPI NOR partitions" + exit +fi + +mtdparts="32k(m25p0.at91bootstrap)ro,256k(m25p0.barebox),128k(m25p0.bareboxenv),128k(m25p0.bareboxenv2),128k(m25p0.oftree),-(m25p0.kernel)" +kernelname="m25p0" + +mtdparts-add -d m25p0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/at91sam9m10ihd/env/init/ps1 b/arch/arm/boards/at91sam9m10ihd/env/init/ps1 new file mode 100644 index 000000000..a94acc14f --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/init/ps1 @@ -0,0 +1,9 @@ +#!/bin/sh + +/env/config + +if [ ${global.allow_color} = "true" ]; then + export PS1="\e[1;32mbarebox@\e[1;36m\h:\w\e[0m\n# " +else + export PS1="barebox@\h:\w\n# " +fi diff --git a/arch/arm/boards/at91sam9m10ihd/env/init/splash b/arch/arm/boards/at91sam9m10ihd/env/init/splash new file mode 100644 index 000000000..18e74dfcc --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/init/splash @@ -0,0 +1,8 @@ +#!/bin/sh + +splash=/env/splash.png + +if [ -f ${splash} -a -e /dev/fb0 ]; then + splash -o ${splash} + fb0.enable=1 +fi diff --git a/arch/arm/boards/at91sam9m10ihd/hw_version.c b/arch/arm/boards/at91sam9m10ihd/hw_version.c new file mode 100644 index 000000000..cd522f7b2 --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/hw_version.c @@ -0,0 +1,216 @@ +/* + * Copyright (C) 2012-2013 Jean-Christophe PLAGNIOL-VILLARD + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "hw_version.h" + +enum board_type { + BOARD_TYPE_DB, + BOARD_TYPE_CPU, +}; + +static struct board_info { + char *name; + enum board_type type; + unsigned char id; +} board_list[] = { + {"SAM9M10-CM", BOARD_TYPE_CPU, 0}, + {"IHD-DB-9M10", BOARD_TYPE_DB, 1}, +}; + +static struct board_info* get_board_info_by_name(const char *name) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(board_list); i++) + if (strcmp(name, board_list[i].name) == 0) + return &board_list[i]; + + return NULL; +} + +static struct vendor_info { + char *name; + enum vendor_id id; +} vendor_list[] = { + {"ATMEL_SH", VENDOR_ATMEL}, + {"FLEX", VENDOR_FLEX}, +}; + +static struct vendor_info* get_vendor_info_by_name(const char *name) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(vendor_list); i++) + if (strcmp(name, vendor_list[i].name) == 0) + return &vendor_list[i]; + + return NULL; +} + +#define BOARD_NAME_LEN 12 +#define VENDOR_NAME_LEN 10 +#define VENDOR_COUNTRY_LEN 2 + +struct one_wire_info { + u8 total_bytes; + u8 vendor_name[VENDOR_NAME_LEN]; + u8 vendor_country[VENDOR_COUNTRY_LEN]; + u8 board_name[BOARD_NAME_LEN]; + u8 year; + u8 week; + u8 revision_code; + u8 revision_id; + u8 reserved; + u8 checksum_l; + u8 checksum_h; +}__attribute__ ((packed)); + +static int at91sam9m10ihd_read_w1(const char *file, struct one_wire_info *info) +{ + int fd; + int ret; + + fd = open(file, O_RDONLY); + if (fd < 0) { + ret = fd; + goto err; + } + + ret = read_full(fd, info, sizeof(*info)); + if (ret < 0) + goto err_open; + + if (ret < sizeof(*info)) { + ret = -EINVAL; + goto err_open; + } + + pr_debug("total_bytes = %d\n", info->total_bytes); + pr_debug("vendor_name = %s\n", info->vendor_name); + pr_debug("vendor_country = %.2s\n", info->vendor_country); + pr_debug("board_name = %s\n", info->board_name); + pr_debug("year = %d\n", info->year); + pr_debug("week = %d\n", info->week); + pr_debug("revision_code = %x\n", info->revision_code); + pr_debug("revision_id = %x\n", info->revision_id); + pr_debug("reserved = %x\n", info->reserved); + pr_debug("checksum_l = %x\n", info->checksum_l); + pr_debug("checksum_h = %x\n", info->checksum_h); + + ret = 0; + +err_open: + close(fd); +err: + if (ret) + pr_err("can not read 1-wire %s (%s)\n", file, strerror(ret)); + return ret; +} + +static u32 sn = 0; +static u32 rev = 0; + +bool at91sam9m10ihd_cm_is_vendor(enum vendor_id vid) +{ + return ((sn >> 5) & 0x1f) == vid; +} + +bool at91sam9m10ihd_db_is_vendor(enum vendor_id vid) +{ + return ((sn >> 15) & 0x1f) == vid; +} + +static void at91sam9m10ihd_devices_detect_one(const char *name) +{ + struct one_wire_info info; + struct board_info* binfo; + struct vendor_info* vinfo; + struct device_d *dev = NULL; + char str[16]; + u8 vendor_id = 0; + + if (at91sam9m10ihd_read_w1(name, &info)) + return; + + binfo = get_board_info_by_name(info.board_name); + + if (!binfo) { + pr_err("board %s no supported\n", info.board_name); + return; + } + + vinfo = get_vendor_info_by_name(info.vendor_name); + if (vinfo) + vendor_id = vinfo->id; + + switch (binfo->type) { + case BOARD_TYPE_CPU: + dev = add_generic_device_res("at91sam9m10ihd", DEVICE_ID_SINGLE, NULL, 0, NULL); + if (!dev) + return; + sn |= (binfo->id & 0x1f); + sn |= ((vendor_id & 0x1f) << 5); + rev |= (info.revision_code - 'A'); + rev |= (((info.revision_id - '0') & 0x3) << 15); + pr_info("CM"); + break; + case BOARD_TYPE_DB: + dev = add_generic_device_res("at91sam9m10ihd-db", DEVICE_ID_SINGLE, NULL, 0, NULL); + if (!dev) + return; + sn |= ((binfo->id & 0x1f) << 20); + sn |= ((vendor_id & 0x1f) << 25); + rev |= ((info.revision_code - 'A') << 10); + rev |= (((info.revision_id - '0') & 0x3) << 21); + pr_info("DB"); + break; + } + + pr_info(": %s [%c%c] from %s\n", + info.board_name, info.revision_code, info.revision_id, + info.vendor_name); + + dev_add_param_fixed(dev, "vendor", info.vendor_name); + dev_add_param_fixed(dev, "board", info.board_name); + sprintf(str, "%.2s", info.vendor_country); + dev_add_param_fixed(dev, "country", str); + sprintf(str, "%d", info.year); + dev_add_param_fixed(dev, "year", str); + sprintf(str, "%d", info.week); + dev_add_param_fixed(dev, "week", str); + sprintf(str, "%c", info.revision_code); + dev_add_param_fixed(dev, "revision_code", str); + sprintf(str, "%c", info.revision_id); + dev_add_param_fixed(dev, "revision_id", str); +} + +void at91sam9m10ihd_devices_detect_hw(void) +{ + at91sam9m10ihd_devices_detect_one("/dev/ds24310"); + at91sam9m10ihd_devices_detect_one("/dev/ds24330"); + + pr_info("sn: 0x%x, rev: 0x%x\n", sn, rev); + armlinux_set_revision(rev); + armlinux_set_serial(sn); +} diff --git a/arch/arm/boards/at91sam9m10ihd/hw_version.h b/arch/arm/boards/at91sam9m10ihd/hw_version.h new file mode 100644 index 000000000..b9133440d --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/hw_version.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2012-2013 Jean-Christophe PLAGNIOL-VILLARD + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __HW_REVISION_H__ +#define __HW_REVISION_H__ + +enum vendor_id { + VENDOR_UNKNOWN = 0, + VENDOR_ATMEL = 1, + VENDOR_FLEX = 2, +}; + +void at91sam9m10ihd_devices_detect_hw(void); + +bool at91sam9m10ihd_cm_is_vendor(enum vendor_id vid); +bool at91sam9m10ihd_db_is_vendor(enum vendor_id vid); + +#endif /* __HW_REVISION_H__ */ diff --git a/arch/arm/boards/at91sam9m10ihd/init.c b/arch/arm/boards/at91sam9m10ihd/init.c new file mode 100644 index 000000000..f258caf2b --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/init.c @@ -0,0 +1,287 @@ +/* + * Copyright (C) 2009-2012 Jean-Christophe PLAGNIOL-VILLARD + * + * Under GPLv2 only + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hw_version.h" + +struct w1_gpio_platform_data w1_pdata = { + .pin = AT91_PIN_PB25, + .ext_pullup_enable_pin = -EINVAL, + .is_open_drain = 0, +}; + +static struct atmel_nand_data nand_pdata = { + .ale = 21, + .cle = 22, + .det_pin = -EINVAL, + .rdy_pin = AT91_PIN_PC15, + .enable_pin = AT91_PIN_PC14, + .bus_width_16 = 0, + .on_flash_bbt = 1, +}; + +static struct sam9_smc_config ek_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 2, + .ncs_write_setup = 0, + .nwe_setup = 2, + + .ncs_read_pulse = 4, + .nrd_pulse = 4, + .ncs_write_pulse = 4, + .nwe_pulse = 4, + + .read_cycle = 7, + .write_cycle = 7, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, + .tdf_cycles = 3, +}; + +static void ek_add_device_nand(void) +{ + /* setup bus-width (8 or 16) */ + if (nand_pdata.bus_width_16) + ek_nand_smc_config.mode |= AT91_SMC_DBW_16; + else + ek_nand_smc_config.mode |= AT91_SMC_DBW_8; + + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(0, 3, &ek_nand_smc_config); + + at91_add_device_nand(&nand_pdata); +} + +static struct at91_ether_platform_data macb_pdata = { + .phy_interface = PHY_INTERFACE_MODE_RMII, + .phy_addr = 0, +}; + +static void ek_add_device_eth(void) +{ + if (w1_local_mac_address_register(0, "tml", "w1-2d-0")) + w1_local_mac_address_register(0, "tml", "w1-23-0"); + + at91_add_device_eth(0, &macb_pdata); +} + +#if defined(CONFIG_MCI_ATMEL) +static struct atmel_mci_platform_data ek_mci0_data = { + .bus_width = 4, + .detect_pin = AT91_PIN_PC25, +}; + +static void ek_add_device_mci(void) +{ + at91_add_device_mci(0, &ek_mci0_data); +} +#else +static void ek_add_device_mci(void) {} +#endif + +struct qt1070_platform_data qt1070_pdata = { + .irq_pin = AT91_PIN_PB19, + .code = { KEY_ENTER, KEY_ENTER, KEY_UP, KEY_DOWN, }, + .nb_code = 4, +}; + +static struct i2c_board_info i2c_devices[] = { + { + .platform_data = &qt1070_pdata, + I2C_BOARD_INFO("qt1070", 0x1b), + }, { + I2C_BOARD_INFO("24c512", 0x51) + }, +}; + +static void ek_add_device_i2c(void) +{ + at91_set_gpio_input(qt1070_pdata.irq_pin, 0); + at91_set_deglitch(qt1070_pdata.irq_pin, 1); + at91_add_device_i2c(0, i2c_devices, ARRAY_SIZE(i2c_devices)); +} + +static const struct spi_board_info ek_spi_devices[] = { + { + .name = "m25p80", + .chip_select = 0, + .max_speed_hz = 15 * 1000 * 1000, + .bus_num = 0, + } +}; + +static unsigned spi0_standard_cs[] = { AT91_PIN_PB3 }; +static struct at91_spi_platform_data spi_pdata = { + .chipselect = spi0_standard_cs, + .num_chipselect = ARRAY_SIZE(spi0_standard_cs), +}; + +static void ek_add_device_spi(void) +{ + spi_register_board_info(ek_spi_devices, + ARRAY_SIZE(ek_spi_devices)); + at91_add_device_spi(0, &spi_pdata); +} + +/* + * USB HS Host port (common to OHCI & EHCI) + */ +static struct at91_usbh_data ek_usbh_hs_data = { + .ports = 1, + .vbus_pin = {AT91_PIN_PC30, -EINVAL}, + .vbus_pin_active_low = {1, 0}, +}; + +static void ek_add_device_usb(void) +{ + at91_add_device_usbh_ohci(&ek_usbh_hs_data); + at91_add_device_usbh_ehci(&ek_usbh_hs_data); +} + +static int at91sam9m10g45ek_mem_init(void) +{ + at91_add_device_sdram(0); + + return 0; +} +mem_initcall(at91sam9m10g45ek_mem_init); + +#if defined(CONFIG_DRIVER_VIDEO_ATMEL) +static int ek_gpio_request_output(int gpio, const char *name) +{ + int ret; + + ret = gpio_request(gpio, name); + if (ret) { + pr_err("%s: can not request gpio %d (%d)\n", name, gpio, ret); + return ret; + } + + ret = gpio_direction_output(gpio, 1); + if (ret) + pr_err("%s: can not configure gpio %d as output (%d)\n", name, gpio, ret); + return ret; +} + +static struct fb_videomode at91fb_default_monspecs[] = { + { + .name = "MULTEK", + .refresh = 60, + .xres = 800, .yres = 480, + .pixclock = KHZ2PICOS(15000), + + .left_margin = 40, .right_margin = 40, + .upper_margin = 29, .lower_margin = 13, + .hsync_len = 48, .vsync_len = 3, + + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +#define AT91SAM9G45_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \ + | ATMEL_LCDC_DISTYPE_TFT \ + | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) + +static void at91_lcdc_power_control(int on) +{ + gpio_set_value(AT91_PIN_PE6, on); +} + +/* Driver datas */ +static struct atmel_lcdfb_platform_data ek_lcdc_data = { + .lcdcon_is_backlight = true, + .default_bpp = 16, + .default_dmacon = ATMEL_LCDC_DMAEN, + .default_lcdcon2 = AT91SAM9G45_DEFAULT_LCDCON2, + .guard_time = 9, + .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, + .atmel_lcdfb_power_control = at91_lcdc_power_control, + .mode_list = at91fb_default_monspecs, + .num_modes = ARRAY_SIZE(at91fb_default_monspecs), +}; + +static void ek_add_device_lcd(void) +{ + if (ek_gpio_request_output(AT91_PIN_PE6, "lcdc_power")) + return; + + at91_add_device_lcdc(&ek_lcdc_data); +} +#else +static void ek_add_device_lcd(void) {} +#endif + +static void ek_add_device_w1(void) +{ + at91_set_gpio_input(w1_pdata.pin, 0); + at91_set_multi_drive(w1_pdata.pin, 1); + add_generic_device_res("w1-gpio", DEVICE_ID_SINGLE, NULL, 0, &w1_pdata); + + at91sam9m10ihd_devices_detect_hw(); +} + +static int at91sam9m10ihd_devices_init(void) +{ + ek_add_device_w1(); + ek_add_device_nand(); + ek_add_device_eth(); + ek_add_device_mci(); + ek_add_device_spi(); + ek_add_device_i2c(); + ek_add_device_usb(); + ek_add_device_lcd(); + + devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw"); + dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap"); + devfs_add_partition("nand0", SZ_128K, SZ_256K, DEVFS_PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + devfs_add_partition("nand0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw1"); + dev_add_bb_dev("env_raw1", "env1"); + + armlinux_set_bootparams((void *)(AT91_CHIPSELECT_6 + 0x100)); + /* + * The internal Atmel kernel use the SAM9M10G45EK machine id + * The mainline use DT + */ + armlinux_set_architecture(MACH_TYPE_AT91SAM9M10G45EK); + + return 0; +} +device_initcall(at91sam9m10ihd_devices_init); + +static int at91sam9m10ihd_console_init(void) +{ + at91_register_uart(0, 0); + return 0; +} +console_initcall(at91sam9m10ihd_console_init); diff --git a/arch/arm/boards/at91sam9n12ek/env/bin/init_board b/arch/arm/boards/at91sam9n12ek/env/bin/init_board index 977430deb..b41b63847 100644 --- a/arch/arm/boards/at91sam9n12ek/env/bin/init_board +++ b/arch/arm/boards/at91sam9n12ek/env/bin/init_board @@ -1,5 +1,12 @@ #!/bin/sh +splash=/env/splash.png + +if [ -f ${splash} -a -e /dev/fb0 ]; then + splash -o ${splash} + fb0.enable=1 +fi + button_name="dfu_bp" button_wait=5 diff --git a/arch/arm/boards/at91sam9n12ek/init.c b/arch/arm/boards/at91sam9n12ek/init.c index 2fe7a1142..a1816664f 100644 --- a/arch/arm/boards/at91sam9n12ek/init.c +++ b/arch/arm/boards/at91sam9n12ek/init.c @@ -124,6 +124,75 @@ static void __init ek_add_device_ks8851(void) static void __init ek_add_device_ks8851(void) {} #endif /* CONFIG_DRIVER_NET_KS8851_MLL */ +#if defined(CONFIG_DRIVER_VIDEO_ATMEL_HLCD) +static int ek_gpio_request_output(int gpio, const char *name) +{ + int ret; + + ret = gpio_request(gpio, name); + if (ret) { + pr_err("%s: can not request gpio %d (%d)\n", name, gpio, ret); + return ret; + } + + ret = gpio_direction_output(gpio, 1); + if (ret) + pr_err("%s: can not configure gpio %d as output (%d)\n", name, gpio, ret); + return ret; +} + + +/* + * LCD Controller + */ +static struct fb_videomode at91_tft_vga_modes[] = { + { + .name = "QD", + .refresh = 60, + .xres = 480, .yres = 272, + .pixclock = KHZ2PICOS(9000), + + .left_margin = 8, .right_margin = 43, + .upper_margin = 4, .lower_margin = 12, + .hsync_len = 5, .vsync_len = 10, + + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +/* Default output mode is TFT 24 bit */ +#define BPP_OUT_DEFAULT_LCDCFG5 (LCDC_LCDCFG5_MODE_OUTPUT_24BPP) + +static void at91_lcdc_power_control(int on) +{ + gpio_set_value(AT91_PIN_PC25, !on); +} + +/* Driver datas */ +static struct atmel_lcdfb_platform_data ek_lcdc_data = { + .lcdcon_is_backlight = true, + .default_bpp = 16, + .default_dmacon = ATMEL_LCDC_DMAEN, + .default_lcdcon2 = BPP_OUT_DEFAULT_LCDCFG5, + .guard_time = 9, + .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, + .atmel_lcdfb_power_control = at91_lcdc_power_control, + .mode_list = at91_tft_vga_modes, + .num_modes = ARRAY_SIZE(at91_tft_vga_modes), +}; + +static void ek_add_device_lcdc(void) +{ + if (ek_gpio_request_output(AT91_PIN_PC25, "lcdc_power")) + return; + + at91_add_device_lcdc(&ek_lcdc_data); +} +#else +static void ek_add_device_lcdc(void) {} +#endif + /* * MCI (SD/MMC) */ @@ -228,7 +297,7 @@ static void __init ek_add_device_buttons(void) static int at91sam9n12ek_mem_init(void) { - at91_add_device_sdram(128 * 1024 * 1024); + at91_add_device_sdram(0); return 0; } @@ -244,6 +313,7 @@ static int at91sam9n12ek_devices_init(void) ek_add_device_i2c(); ek_add_device_ks8851(); ek_add_device_buttons(); + ek_add_device_lcdc(); armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100)); armlinux_set_architecture(CONFIG_MACH_AT91SAM9N12EK); diff --git a/arch/arm/boards/at91sam9x5ek/env/bin/init_board b/arch/arm/boards/at91sam9x5ek/env/bin/init_board new file mode 100644 index 000000000..f3d417e35 --- /dev/null +++ b/arch/arm/boards/at91sam9x5ek/env/bin/init_board @@ -0,0 +1,15 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config + +splash=/env/splash.png + +if [ -f ${splash} -a -e /dev/fb0 ]; then + splash -o ${splash} + fb0.enable=1 +fi + +exit 1 diff --git a/arch/arm/boards/at91sam9x5ek/init.c b/arch/arm/boards/at91sam9x5ek/init.c index bcb961a94..4e1e06956 100644 --- a/arch/arm/boards/at91sam9x5ek/init.c +++ b/arch/arm/boards/at91sam9x5ek/init.c @@ -106,7 +106,7 @@ static void ek_add_device_nand(void) } static struct at91_ether_platform_data macb_pdata = { - .is_rmii = 1, + .phy_interface = PHY_INTERFACE_MODE_RMII, .phy_addr = 0, }; @@ -118,6 +118,49 @@ static void ek_add_device_eth(void) at91_add_device_eth(0, &macb_pdata); } +#if defined(CONFIG_DRIVER_VIDEO_ATMEL_HLCD) +/* + * LCD Controller + */ +static struct fb_videomode at91_tft_vga_modes[] = { + { + .name = "LG", + .refresh = 60, + .xres = 800, .yres = 480, + .pixclock = KHZ2PICOS(33260), + + .left_margin = 88, .right_margin = 168, + .upper_margin = 8, .lower_margin = 37, + .hsync_len = 128, .vsync_len = 2, + + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +/* Default output mode is TFT 24 bit */ +#define AT91SAM9X5_DEFAULT_LCDCFG5 (LCDC_LCDCFG5_MODE_OUTPUT_24BPP) + +/* Driver datas */ +static struct atmel_lcdfb_platform_data ek_lcdc_data = { + .lcdcon_is_backlight = true, + .default_bpp = 16, + .default_lcdcon2 = AT91SAM9X5_DEFAULT_LCDCFG5, + .guard_time = 9, + .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, + .mode_list = at91_tft_vga_modes, + .num_modes = ARRAY_SIZE(at91_tft_vga_modes), +}; + +static void ek_add_device_lcdc(void) +{ + at91_add_device_lcdc(&ek_lcdc_data); +} + +#else +static void ek_add_device_lcdc(void) {} +#endif + /* * MCI (SD/MMC) */ @@ -192,14 +235,24 @@ static void ek_add_device_spi(void) at91_add_device_spi(0, &spi_pdata); } +#if defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI) /* - * USB Host port + * USB HS Host port (common to OHCI & EHCI) */ -static struct at91_usbh_data __initdata ek_usbh_data = { - .ports = 2, - .vbus_pin = {AT91_PIN_PD20, AT91_PIN_PD19}, +static struct at91_usbh_data ek_usbh_hs_data = { + .ports = 2, + .vbus_pin = {AT91_PIN_PD19, AT91_PIN_PD20}, }; +static void ek_add_device_usb(void) +{ + at91_add_device_usbh_ohci(&ek_usbh_hs_data); + at91_add_device_usbh_ehci(&ek_usbh_hs_data); +} +#else +static void ek_add_device_usb(void) {} +#endif + struct gpio_led leds[] = { { .gpio = AT91_PIN_PB18, @@ -228,7 +281,7 @@ static void __init ek_add_led(void) static int at91sam9x5ek_mem_init(void) { - at91_add_device_sdram(128 * 1024 * 1024); + at91_add_device_sdram(0); return 0; } @@ -250,9 +303,10 @@ static int at91sam9x5ek_devices_init(void) ek_add_device_eth(); ek_add_device_spi(); ek_add_device_mci(); - at91_add_device_usbh_ohci(&ek_usbh_data); + ek_add_device_usb(); ek_add_led(); ek_add_device_i2c(); + ek_add_device_lcdc(); armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100)); armlinux_set_architecture(CONFIG_MACH_AT91SAM9X5EK); diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c index f9ac7a469..86de3b0f1 100644 --- a/arch/arm/boards/beaglebone/board.c +++ b/arch/arm/boards/beaglebone/board.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/boards/mmccpu/Makefile b/arch/arm/boards/mmccpu/Makefile index eb072c016..b6460c398 100644 --- a/arch/arm/boards/mmccpu/Makefile +++ b/arch/arm/boards/mmccpu/Makefile @@ -1 +1,5 @@ obj-y += init.o + +obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o + +pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o diff --git a/arch/arm/boards/mmccpu/config.h b/arch/arm/boards/mmccpu/config.h index e6215dc46..c896a93b4 100644 --- a/arch/arm/boards/mmccpu/config.h +++ b/arch/arm/boards/mmccpu/config.h @@ -3,122 +3,4 @@ #define AT91_MAIN_CLOCK 18432000 -/* values */ -#define MASTER_PLL_MUL 54 -#define MASTER_PLL_DIV 4 - -/* clocks */ -#define CONFIG_SYS_MOR_VAL \ - (AT91_PMC_MOSCEN | \ - (255 << 8)) /* Main Oscillator Start-up Time */ -#define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ - AT91_PMC_OUT | \ - AT91_PMC_PLLCOUNT | /* PLL Counter */ \ - (2 << 28) | /* PLL Clock Frequency Range */ \ - ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) - -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_CSS_SLOW | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_CSS_PLLA | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) - -/* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 -/* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 -/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 1.8V memories */ -#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ - (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_1_8V | \ - AT91_MATRIX_EBI0_CS1A_SDRAMC | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA) - -/* SDRAM */ -/* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x13c -/* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ - (AT91_SDRAMC_NC_9 | \ - AT91_SDRAMC_NR_13 | \ - AT91_SDRAMC_NB_4 | \ - AT91_SDRAMC_CAS_3 | \ - AT91_SDRAMC_DBW_32 | \ - (2 << 8) | /* tWR - Write Recovery Delay */ \ - (8 << 12) | /* tRC - Row Cycle Delay */ \ - (2 << 16) | /* tRP - Row Precharge Delay */ \ - (2 << 20) | /* tRCD - Row to Column Delay */ \ - (5 << 24) | /* tRAS - Active to Precharge Delay */ \ - (12 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ - -/* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_TR_VAL2 780 /* SDRAM_TR */ - -/* setup CS0 (NOR Flash) - 16-bit */ -#define CONFIG_SYS_SMC_CS 0 -#if 1 -#define CONFIG_SYS_SMC_SETUP_VAL \ - (AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | \ - AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0)) -#define CONFIG_SYS_SMC_PULSE_VAL \ - (AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | \ - AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13)) -#define CONFIG_SYS_SMC_CYCLE_VAL \ - (AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)) -#define CONFIG_SYS_SMC_MODE_VAL \ - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ - AT91_SMC_DBW_16 | \ - AT91_SMC_TDFMODE | \ - AT91_SMC_TDF_(6)) -#elif 0 /* slow setup */ -#define CONFIG_SYS_SMC_SETUP_VAL \ - (AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | \ - AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0)) -#define CONFIG_SYS_SMC_PULSE_VAL \ - (AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | \ - AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13)) -#define CONFIG_SYS_SMC_CYCLE_VAL \ - (AT91_SMC_NWECYCLE_(0xd00) | AT91_SMC_NRDCYCLE_(0xd00)) -#define CONFIG_SYS_SMC_MODE_VAL \ - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ - AT91_SMC_DBW_16 | \ - AT91_SMC_TDFMODE | \ - AT91_SMC_TDF_(1)) -#else /* RONETIX' original values */ -#define CONFIG_SYS_SMC_SETUP_VAL \ - (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ - AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) -#define CONFIG_SYS_SMC_PULSE_VAL \ - (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ - AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) -#define CONFIG_SYS_SMC_CYCLE_VAL \ - (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) -#define CONFIG_SYS_SMC_MODE_VAL \ - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ - AT91_SMC_DBW_16 | \ - AT91_SMC_TDFMODE | \ - AT91_SMC_TDF_(6)) -#endif - -/* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ - (AT91_RSTC_KEY | \ - AT91_RSTC_PROCRST | \ - AT91_RSTC_RSTTYP_WAKEUP | \ - AT91_RSTC_RSTTYP_WATCHDOG) - -/* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ - (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ - AT91_WDT_WDV | \ - AT91_WDT_WDDIS | \ - AT91_WDT_WDD) - #endif /* __CONFIG_H */ diff --git a/arch/arm/boards/mmccpu/lowlevel_init.c b/arch/arm/boards/mmccpu/lowlevel_init.c new file mode 100644 index 000000000..c193eae58 --- /dev/null +++ b/arch/arm/boards/mmccpu/lowlevel_init.c @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD + * + * Under GPLv2 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MASTER_PLL_MUL 54 +#define MASTER_PLL_DIV 4 + +void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg) +{ + /* Disable Watchdog */ + cfg->wdt_mr = + AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | + AT91_WDT_WDV | + AT91_WDT_WDDIS | + AT91_WDT_WDD; + + /* define PDC[31:16] as DATA[31:16] */ + cfg->ebi_pio_pdr = 0xFFFF0000; + /* no pull-up for D[31:16] */ + cfg->ebi_pio_ppudr = 0xFFFF0000; + /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ + cfg->ebi_csa = + AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_1_8V | + AT91_MATRIX_EBI0_CS1A_SDRAMC | + AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA; + + cfg->smc_cs = 0; +#if 1 + cfg->smc_mode = + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_DBW_16 | + AT91_SMC_TDFMODE | + AT91_SMC_TDF_(6); + cfg->smc_cycle = + AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16); + cfg->smc_pulse = + AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | + AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13); + cfg->smc_setup = + AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | + AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0); +#elif 0 /* slow setup */ + cfg->smc_mode = + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_DBW_16 | + AT91_SMC_TDFMODE | + AT91_SMC_TDF_(1); + cfg->smc_cycle = + AT91_SMC_NWECYCLE_(0xd00) | AT91_SMC_NRDCYCLE_(0xd00); + cfg->smc_pulse = + AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | + AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13); + cfg->smc_setup = + AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | + AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0); +#else /* RONETIX' original values */ + cfg->smc_mode = + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_DBW_16 | + AT91_SMC_TDFMODE | + AT91_SMC_TDF_(6); + cfg->smc_cycle = + AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22); + cfg->smc_pulse = + AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | + AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11); + cfg->smc_setup = + AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | + AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10); +#endif + + cfg->pmc_mor = + AT91_PMC_MOSCEN | + (255 << 8); /* Main Oscillator Start-up Time */ + cfg->pmc_pllar = + AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ + AT91_PMC_OUT | + AT91_PMC_PLLCOUNT | /* PLL Counter */ + (2 << 28) | /* PLL Clock Frequency Range */ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV); + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr1 = + AT91_PMC_CSS_SLOW | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr2 = + AT91_PMC_CSS_PLLA | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + + /* SDRAM */ + /* SDRAMC_TR - Refresh Timer register */ + cfg->sdrc_tr1 = 0x13C; + /* SDRAMC_CR - Configuration register*/ + cfg->sdrc_cr = + AT91_SDRAMC_NC_9 | + AT91_SDRAMC_NR_13 | + AT91_SDRAMC_NB_4 | + AT91_SDRAMC_CAS_3 | + AT91_SDRAMC_DBW_32 | + (2 << 8) | /* tWR - Write Recovery Delay */ + (8 << 12) | /* tRC - Row Cycle Delay */ + (2 << 16) | /* tRP - Row Precharge Delay */ + (2 << 20) | /* tRCD - Row to Column Delay */ + (5 << 24) | /* tRAS - Active to Precharge Delay */ + (12 << 28); /* tXSR - Exit Self Refresh to Active Delay */ + + /* Memory Device Register -> SDRAM */ + cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM; + /* SDRAM_TR */ + cfg->sdrc_tr2 = 780; + + /* user reset enable */ + cfg->rstc_rmr = + AT91_RSTC_KEY | + AT91_RSTC_PROCRST | + AT91_RSTC_RSTTYP_WAKEUP | + AT91_RSTC_RSTTYP_WATCHDOG; +} diff --git a/arch/arm/boards/panda/board.c b/arch/arm/boards/panda/board.c index c5d8fe640..f1fbd5e94 100644 --- a/arch/arm/boards/panda/board.c +++ b/arch/arm/boards/panda/board.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/boards/pm9261/Makefile b/arch/arm/boards/pm9261/Makefile index eb072c016..b6460c398 100644 --- a/arch/arm/boards/pm9261/Makefile +++ b/arch/arm/boards/pm9261/Makefile @@ -1 +1,5 @@ obj-y += init.o + +obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o + +pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o diff --git a/arch/arm/boards/pm9261/config.h b/arch/arm/boards/pm9261/config.h index 4602aa7e8..006820cf2 100644 --- a/arch/arm/boards/pm9261/config.h +++ b/arch/arm/boards/pm9261/config.h @@ -3,91 +3,4 @@ #define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ -#define MASTER_PLL_DIV 15 -#define MASTER_PLL_MUL 162 -#define MAIN_PLL_DIV 2 - -/* clocks */ -#define CONFIG_SYS_MOR_VAL \ - (AT91_PMC_MOSCEN | \ - (255 << 8)) /* Main Oscillator Start-up Time */ -#define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ - AT91_PMC_OUT | \ - ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) - -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_CSS_SLOW | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) - -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_CSS_PLLA | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) - -/* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 -/* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 - -/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ -#define CONFIG_SYS_MATRIX_EBICSA_VAL \ - (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC) - -/* SDRAM */ -/* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x13C -/* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ - (AT91_SDRAMC_NC_9 | \ - AT91_SDRAMC_NR_13 | \ - AT91_SDRAMC_NB_4 | \ - AT91_SDRAMC_CAS_3 | \ - AT91_SDRAMC_DBW_32 | \ - (1 << 8) | /* Write Recovery Delay */ \ - (7 << 12) | /* Row Cycle Delay */ \ - (3 << 16) | /* Row Precharge Delay */ \ - (2 << 20) | /* Row to Column Delay */ \ - (5 << 24) | /* Active to Precharge Delay */ \ - (1 << 28)) /* Exit Self Refresh to Active Delay */ - -/* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ - -/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC_CS 0 -#define CONFIG_SYS_SMC_SETUP_VAL \ - (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ - AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) -#define CONFIG_SYS_SMC_PULSE_VAL \ - (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ - AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) -#define CONFIG_SYS_SMC_CYCLE_VAL \ - (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) -#define CONFIG_SYS_SMC_MODE_VAL \ - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ - AT91_SMC_DBW_16 | \ - AT91_SMC_TDFMODE | \ - AT91_SMC_TDF_(6)) - -/* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ - (AT91_RSTC_KEY | \ - AT91_RSTC_PROCRST | \ - AT91_RSTC_RSTTYP_WAKEUP | \ - AT91_RSTC_RSTTYP_WATCHDOG) - -/* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ - (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ - AT91_WDT_WDV | \ - AT91_WDT_WDDIS | \ - AT91_WDT_WDD) - #endif /* __CONFIG_H */ diff --git a/arch/arm/boards/pm9261/lowlevel_init.c b/arch/arm/boards/pm9261/lowlevel_init.c new file mode 100644 index 000000000..91a64b415 --- /dev/null +++ b/arch/arm/boards/pm9261/lowlevel_init.c @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD + * + * Under GPLv2 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MASTER_PLL_DIV 15 +#define MASTER_PLL_MUL 162 +#define MAIN_PLL_DIV 2 + +void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg) +{ + /* Disable Watchdog */ + cfg->wdt_mr = + AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | + AT91_WDT_WDV | + AT91_WDT_WDDIS | + AT91_WDT_WDD; + + /* define PDC[31:16] as DATA[31:16] */ + cfg->ebi_pio_pdr = 0xFFFF0000; + /* no pull-up for D[31:16] */ + cfg->ebi_pio_ppudr = 0xFFFF0000; + /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ + cfg->ebi_csa = + AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC; + + cfg->smc_cs = 0; + cfg->smc_mode = + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_DBW_16 | + AT91_SMC_TDFMODE | + AT91_SMC_TDF_(6); + cfg->smc_cycle = + AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22); + cfg->smc_pulse = + AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | + AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11); + cfg->smc_setup = + AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | + AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10); + + cfg->pmc_mor = + AT91_PMC_MOSCEN | + (255 << 8); /* Main Oscillator Start-up Time */ + cfg->pmc_pllar = + AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ + AT91_PMC_OUT | + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV); + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr1 = + AT91_PMC_CSS_SLOW | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr2 = + AT91_PMC_CSS_PLLA | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + + /* SDRAM */ + /* SDRAMC_TR - Refresh Timer register */ + cfg->sdrc_tr1 = 0x13C; + /* SDRAMC_CR - Configuration register*/ + cfg->sdrc_cr = + AT91_SDRAMC_NC_9 | + AT91_SDRAMC_NR_13 | + AT91_SDRAMC_NB_4 | + AT91_SDRAMC_CAS_3 | + AT91_SDRAMC_DBW_32 | + (1 << 8) | /* Write Recovery Delay */ + (7 << 12) | /* Row Cycle Delay */ + (3 << 16) | /* Row Precharge Delay */ + (2 << 20) | /* Row to Column Delay */ + (5 << 24) | /* Active to Precharge Delay */ + (1 << 28); /* Exit Self Refresh to Active Delay */ + + /* Memory Device Register -> SDRAM */ + cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM; + /* SDRAM_TR */ + cfg->sdrc_tr2 = 1200; + + /* user reset enable */ + cfg->rstc_rmr = + AT91_RSTC_KEY | + AT91_RSTC_PROCRST | + AT91_RSTC_RSTTYP_WAKEUP | + AT91_RSTC_RSTTYP_WATCHDOG; +} diff --git a/arch/arm/boards/pm9263/Makefile b/arch/arm/boards/pm9263/Makefile index eb072c016..b6460c398 100644 --- a/arch/arm/boards/pm9263/Makefile +++ b/arch/arm/boards/pm9263/Makefile @@ -1 +1,5 @@ obj-y += init.o + +obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o + +pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o diff --git a/arch/arm/boards/pm9263/config.h b/arch/arm/boards/pm9263/config.h index 322c1f3d3..906661330 100644 --- a/arch/arm/boards/pm9263/config.h +++ b/arch/arm/boards/pm9263/config.h @@ -3,107 +3,4 @@ #define AT91_MAIN_CLOCK 18432000 -#define MASTER_PLL_DIV 6 -#define MASTER_PLL_MUL 65 -#define MAIN_PLL_DIV 2 /* 2 or 4 */ - -/* clocks */ -#define CONFIG_SYS_MOR_VAL \ - (AT91_PMC_MOSCEN | \ - (255 << 8)) /* Main Oscillator Start-up Time */ -#define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ - AT91_PMC_OUT | \ - AT91_PMC_PLLCOUNT | /* PLL Counter */ \ - (2 << 28) | /* PLL Clock Frequency Range */ \ - ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) - -#if (MAIN_PLL_DIV == 2) -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_CSS_SLOW | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_CSS_PLLA | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) -#else -/* PCK/4 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_CSS_SLOW | \ - AT91_PMC_PRES_1 | \ - AT91RM9200_PMC_MDIV_3 | \ - AT91_PMC_PDIV_1) -/* PCK/4 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_CSS_PLLA | \ - AT91_PMC_PRES_1 | \ - AT91RM9200_PMC_MDIV_3 | \ - AT91_PMC_PDIV_1) -#endif -/* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 -/* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 -/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ -#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ - (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \ - AT91_MATRIX_EBI0_CS1A_SDRAMC) - -/* SDRAM */ -/* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA -/* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ - (AT91_SDRAMC_NC_9 | \ - AT91_SDRAMC_NR_13 | \ - AT91_SDRAMC_NB_4 | \ - AT91_SDRAMC_CAS_2 | \ - AT91_SDRAMC_DBW_32 | \ - (2 << 8) | /* tWR - Write Recovery Delay */ \ - (7 << 12) | /* tRC - Row Cycle Delay */ \ - (2 << 16) | /* tRP - Row Precharge Delay */ \ - (2 << 20) | /* tRCD - Row to Column Delay */ \ - (5 << 24) | /* tRAS - Active to Precharge Delay */ \ - (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ - -/* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ - -/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC_CS 0 -#define CONFIG_SYS_SMC_SETUP_VAL \ - (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ - AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) -#define CONFIG_SYS_SMC_PULSE_VAL \ - (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ - AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) -#define CONFIG_SYS_SMC_CYCLE_VAL \ - (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) -#define CONFIG_SYS_SMC_MODE_VAL \ - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ - AT91_SMC_DBW_16 | \ - AT91_SMC_TDFMODE | \ - AT91_SMC_TDF_(6)) - -/* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ - (AT91_RSTC_KEY | \ - AT91_RSTC_PROCRST | \ - AT91_RSTC_RSTTYP_WAKEUP | \ - AT91_RSTC_RSTTYP_WATCHDOG) - -/* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ - (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ - AT91_WDT_WDV | \ - AT91_WDT_WDDIS | \ - AT91_WDT_WDD) - - #endif /* __CONFIG_H */ diff --git a/arch/arm/boards/pm9263/init.c b/arch/arm/boards/pm9263/init.c index 0be5cf54b..4afa09536 100644 --- a/arch/arm/boards/pm9263/init.c +++ b/arch/arm/boards/pm9263/init.c @@ -89,7 +89,7 @@ static void pm_add_device_nand(void) } static struct at91_ether_platform_data macb_pdata = { - .is_rmii = 1, + .phy_interface = PHY_INTERFACE_MODE_RMII, .phy_addr = -1, }; diff --git a/arch/arm/boards/pm9263/lowlevel_init.c b/arch/arm/boards/pm9263/lowlevel_init.c new file mode 100644 index 000000000..6336d5106 --- /dev/null +++ b/arch/arm/boards/pm9263/lowlevel_init.c @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD + * + * Under GPLv2 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MASTER_PLL_DIV 6 +#define MASTER_PLL_MUL 65 +#define MAIN_PLL_DIV 2 /* 2 or 4 */ + +void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg) +{ + /* Disable Watchdog */ + cfg->wdt_mr = + AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | + AT91_WDT_WDV | + AT91_WDT_WDDIS | + AT91_WDT_WDD; + + /* define PDC[31:16] as DATA[31:16] */ + cfg->ebi_pio_pdr = 0xFFFF0000; + /* no pull-up for D[31:16] */ + cfg->ebi_pio_ppudr = 0xFFFF0000; + /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ + cfg->ebi_csa = + AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | + AT91_MATRIX_EBI0_CS1A_SDRAMC; + + cfg->smc_cs = 0; + cfg->smc_mode = + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_DBW_16 | + AT91_SMC_TDFMODE | + AT91_SMC_TDF_(6); + cfg->smc_cycle = + AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22); + cfg->smc_pulse = + AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | + AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11); + cfg->smc_setup = + AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | + AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10); + + cfg->pmc_mor = + AT91_PMC_MOSCEN | + (255 << 8); /* Main Oscillator Start-up Time */ + cfg->pmc_pllar = + AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ + AT91_PMC_OUT | + AT91_PMC_PLLCOUNT | /* PLL Counter */ + (2 << 28) | /* PLL Clock Frequency Range */ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV); + + if (MAIN_PLL_DIV == 2) { + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr1 = + AT91_PMC_CSS_SLOW | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr2 = + AT91_PMC_CSS_PLLA | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + } else { + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr1 = + AT91_PMC_CSS_SLOW | + AT91_PMC_PRES_1 | + AT91RM9200_PMC_MDIV_3 | + AT91_PMC_PDIV_1; + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr2 = + AT91_PMC_CSS_PLLA | + AT91_PMC_PRES_1 | + AT91RM9200_PMC_MDIV_3 | + AT91_PMC_PDIV_1; + } + + /* SDRAM */ + /* SDRAMC_TR - Refresh Timer register */ + cfg->sdrc_tr1 = 0x3AA; + /* SDRAMC_CR - Configuration register*/ + cfg->sdrc_cr = + AT91_SDRAMC_NC_9 | + AT91_SDRAMC_NR_13 | + AT91_SDRAMC_NB_4 | + AT91_SDRAMC_CAS_2 | + AT91_SDRAMC_DBW_32 | + (2 << 8) | /* tWR - Write Recovery Delay */ + (7 << 12) | /* tRC - Row Cycle Delay */ + (2 << 16) | /* tRP - Row Precharge Delay */ + (2 << 20) | /* tRCD - Row to Column Delay */ + (5 << 24) | /* tRAS - Active to Precharge Delay */ + (8 << 28); /* tXSR - Exit Self Refresh to Active Delay */ + + /* Memory Device Register -> SDRAM */ + cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM; + /* SDRAM_TR */ + cfg->sdrc_tr2 = 1200; + + /* user reset enable */ + cfg->rstc_rmr = + AT91_RSTC_KEY | + AT91_RSTC_PROCRST | + AT91_RSTC_RSTTYP_WAKEUP | + AT91_RSTC_RSTTYP_WATCHDOG; +} diff --git a/arch/arm/boards/pm9g45/init.c b/arch/arm/boards/pm9g45/init.c index 8e29f62e8..720099b12 100644 --- a/arch/arm/boards/pm9g45/init.c +++ b/arch/arm/boards/pm9g45/init.c @@ -113,7 +113,7 @@ static void __init pm9g45_add_device_usbh(void) {} #endif static struct at91_ether_platform_data macb_pdata = { - .is_rmii = 1, + .phy_interface = PHY_INTERFACE_MODE_RMII, .phy_addr = 0, }; @@ -137,7 +137,7 @@ static void pm9g45_add_device_eth(void) static int pm9g45_mem_init(void) { - at91_add_device_sdram(128 * 1024 * 1024); + at91_add_device_sdram(0); return 0; } diff --git a/arch/arm/boards/qil-a9260/init.c b/arch/arm/boards/qil-a9260/init.c index 4977d3b75..2e131fee8 100644 --- a/arch/arm/boards/qil-a9260/init.c +++ b/arch/arm/boards/qil-a9260/init.c @@ -78,7 +78,7 @@ static void qil_a9260_add_device_mci(void) {} #ifdef CONFIG_CALAO_MB_QIL_A9260 static struct at91_ether_platform_data macb_pdata = { - .is_rmii = 1, + .phy_interface = PHY_INTERFACE_MODE_RMII, .phy_addr = -1, }; diff --git a/arch/arm/boards/sama5d3xek/Makefile b/arch/arm/boards/sama5d3xek/Makefile new file mode 100644 index 000000000..db021eeb7 --- /dev/null +++ b/arch/arm/boards/sama5d3xek/Makefile @@ -0,0 +1,2 @@ +obj-y += init.o +obj-$(CONFIG_W1) += hw_version.o diff --git a/arch/arm/boards/sama5d3xek/config.h b/arch/arm/boards/sama5d3xek/config.h new file mode 100644 index 000000000..d97181032 --- /dev/null +++ b/arch/arm/boards/sama5d3xek/config.h @@ -0,0 +1,6 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/sama5d3xek/env/bin/init_board b/arch/arm/boards/sama5d3xek/env/bin/init_board new file mode 100644 index 000000000..f3d417e35 --- /dev/null +++ b/arch/arm/boards/sama5d3xek/env/bin/init_board @@ -0,0 +1,15 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config + +splash=/env/splash.png + +if [ -f ${splash} -a -e /dev/fb0 ]; then + splash -o ${splash} + fb0.enable=1 +fi + +exit 1 diff --git a/arch/arm/boards/sama5d3xek/env/config b/arch/arm/boards/sama5d3xek/env/config new file mode 100644 index 000000000..375e90d74 --- /dev/null +++ b/arch/arm/boards/sama5d3xek/env/config @@ -0,0 +1,44 @@ +#!/bin/sh + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=dhcp-barebox +global.dhcp.vendor_id=barebox-sama5d3xek +global.dhcp.client_id="${sama5d3xcm.board}-${sama5d3xcm.vendor}" + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d + +# can be either 'nfs', 'tftp', 'nor' or 'nand' +kernel_loc=nfs +# can be either 'net', 'nor', 'nand' or 'initrd' +rootfs_loc=net +# can be either 'nfs', 'tftp', 'nand' or empty +oftree_loc=nfs + +# can be either 'jffs2' or 'ubifs' +rootfs_type=ubifs +rootfsimage=root.$rootfs_type +ubiroot=rootfs + +# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo +kernelimage=zImage +#kernelimage=uImage +#kernelimage=Image +#kernelimage=Image.lzo + +nand_device=atmel_nand +nand_parts="256k(at91bootstrap),384k(barebox)ro,256k@768k(bareboxenv),256k(bareboxenv2),128k@1536k(oftree),5M@2M(kernel),-@8M(rootfs)" +rootfs_mtdblock_nand=7 + +m25p80_parts="64k(bootstrap),384k(barebox),256k(bareboxenv),256k(bareboxenv2),128k(oftree),-(updater)" + +autoboot_timeout=3 + +bootargs="console=ttyS0,115200" + +# set a fancy prompt (if support is compiled in) +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m\n# " diff --git a/arch/arm/boards/sama5d3xek/hw_version.c b/arch/arm/boards/sama5d3xek/hw_version.c new file mode 100644 index 000000000..a9fcf7dc1 --- /dev/null +++ b/arch/arm/boards/sama5d3xek/hw_version.c @@ -0,0 +1,251 @@ +/* + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "hw_version.h" + +enum board_type { + BOARD_TYPE_MB, + BOARD_TYPE_DM, + BOARD_TYPE_CPU, +}; + +static struct board_info { + char *name; + enum board_type type; + unsigned char id; +} board_list[] = { + {"SAMA5D3x-MB", BOARD_TYPE_MB, 0}, + {"SAMA5D3x-DM", BOARD_TYPE_DM, 1}, + {"SAMA5D31-CM", BOARD_TYPE_CPU, 2}, + {"SAMA5D33-CM", BOARD_TYPE_CPU, 3}, + {"SAMA5D34-CM", BOARD_TYPE_CPU, 4}, + {"SAMA5D35-CM", BOARD_TYPE_CPU, 5}, + {"PDA-DM", BOARD_TYPE_DM, 7}, +}; + +static struct board_info* get_board_info_by_name(const char *name) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(board_list); i++) { + char *bname = board_list[i].name; + if (strncmp(name, bname, strlen(bname)) == 0) + return &board_list[i]; + } + + return NULL; +} + +static struct vendor_info { + char *name; + enum vendor_id id; +} vendor_list[] = { + {"EMBEST", VENDOR_EMBEST}, + {"FLEX", VENDOR_FLEX}, + {"RONETIX", VENDOR_RONETIX}, + {"COGENT", VENDOR_COGENT}, + {"PDA", VENDOR_PDA}, +}; + +static struct vendor_info* get_vendor_info_by_name(const char *name) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(vendor_list); i++) { + char *vname = vendor_list[i].name; + if (strncmp(name, vname, strlen(vname)) == 0) + return &vendor_list[i]; + } + + return NULL; +} + +#define BOARD_NAME_LEN 12 +#define VENDOR_NAME_LEN 10 +#define VENDOR_COUNTRY_LEN 2 + +struct one_wire_info { + u8 total_bytes; + u8 vendor_name[VENDOR_NAME_LEN]; + u8 vendor_country[VENDOR_COUNTRY_LEN]; + u8 board_name[BOARD_NAME_LEN]; + u8 year; + u8 week; + u8 revision_board; + u8 revision_schema; + u8 revision_bom; + u8 checksum_l; + u8 checksum_h; +}__attribute__ ((packed)); + +static int at91sama5d3xek_read_w1(const char *file, struct one_wire_info *info) +{ + int fd; + int ret; + + fd = open(file, O_RDONLY); + if (fd < 0) { + ret = fd; + goto err; + } + + ret = read_full(fd, info, sizeof(*info)); + if (ret < 0) + goto err_open; + + if (ret < sizeof(*info)) { + ret = -EINVAL; + goto err_open; + } + + pr_debug("total_bytes = %d\n", info->total_bytes); + pr_debug("vendor_name = %s\n", info->vendor_name); + pr_debug("vendor_country = %.2s\n", info->vendor_country); + pr_debug("board_name = %s\n", info->board_name); + pr_debug("year = %d\n", info->year); + pr_debug("week = %d\n", info->week); + pr_debug("revision_board = %x\n", info->revision_board); + pr_debug("revision_schema = %x\n", info->revision_schema); + pr_debug("revision_bom = %x\n", info->revision_bom); + pr_debug("checksum_l = %x\n", info->checksum_l); + pr_debug("checksum_h = %x\n", info->checksum_h); + + ret = 0; + +err_open: + close(fd); +err: + if (ret) + pr_err("can not read 1-wire %s (%s)\n", file, strerror(ret)); + return ret; +} + +static u32 sn = 0; +static u32 rev = 0; + +bool at91sama5d3xek_cm_is_vendor(enum vendor_id vid) +{ + return ((sn >> 5) & 0x1f) == vid; +} + +bool at91sama5d3xek_ek_is_vendor(enum vendor_id vid) +{ + return ((sn >> 25) & 0x1f) == vid; +} + +bool at91sama5d3xek_dm_is_vendor(enum vendor_id vid) +{ + return ((sn >> 15) & 0x1f) == vid; +} + +static void at91sama5d3xek_devices_detect_one(const char *name) +{ + struct one_wire_info info; + struct board_info* binfo; + struct vendor_info* vinfo; + struct device_d *dev = NULL; + char str[16]; + char *bname, *vname; + u8 vendor_id = 0; + + if (at91sama5d3xek_read_w1(name, &info)) + return; + + binfo = get_board_info_by_name(info.board_name); + + if (!binfo) { + pr_err("board %s no supported\n", info.board_name); + return; + } + bname = binfo->name; + + vinfo = get_vendor_info_by_name(info.vendor_name); + vname = info.vendor_name; + if (vinfo) { + vendor_id = vinfo->id; + vname = vinfo->name; + } + + switch (binfo->type) { + case BOARD_TYPE_CPU: + dev = add_generic_device_res("sama5d3xcm", DEVICE_ID_SINGLE, NULL, 0, NULL); + if (!dev) + return; + sn |= (binfo->id & 0x1f); + sn |= ((vendor_id & 0x1f) << 5); + rev |= (info.revision_board - 'A'); + rev |= (((info.revision_schema - '0') & 0x3) << 15); + pr_info("CM"); + break; + case BOARD_TYPE_MB: + dev = add_generic_device_res("sama5d3xmb", DEVICE_ID_SINGLE, NULL, 0, NULL); + if (!dev) + return; + sn |= ((binfo->id & 0x1f) << 20); + sn |= ((vendor_id & 0x1f) << 25); + rev |= ((info.revision_board - 'A') << 10); + rev |= (((info.revision_schema - '0') & 0x3) << 21); + pr_info("MB"); + break; + case BOARD_TYPE_DM: + dev = add_generic_device_res("sama5d3xdm", DEVICE_ID_SINGLE, NULL, 0, NULL); + if (!dev) + return; + sn |= ((binfo->id & 0x1f) << 10); + sn |= ((vendor_id & 0x1f) << 15); + rev |= ((info.revision_board - 'A') << 5); + rev |= (((info.revision_schema - '0') & 0x3) << 18); + pr_info("DM"); + break; + } + + pr_info(": %s [%c%c] from %s\n", + bname, info.revision_board, info.revision_schema, vname); + + dev_add_param_fixed(dev, "vendor", vname); + dev_add_param_fixed(dev, "board", bname); + sprintf(str, "%.2s", info.vendor_country); + dev_add_param_fixed(dev, "country", str); + sprintf(str, "%d", info.year); + dev_add_param_fixed(dev, "year", str); + sprintf(str, "%d", info.week); + dev_add_param_fixed(dev, "week", str); + sprintf(str, "%c", info.revision_board); + dev_add_param_fixed(dev, "revision_board", str); + sprintf(str, "%c", info.revision_schema); + dev_add_param_fixed(dev, "revision_schema", str); + sprintf(str, "%c", info.revision_bom); + dev_add_param_fixed(dev, "revision_bom", str); +} + +void at91sama5d3xek_devices_detect_hw(void) +{ + at91sama5d3xek_devices_detect_one("/dev/ds24310"); + at91sama5d3xek_devices_detect_one("/dev/ds28ec200"); + at91sama5d3xek_devices_detect_one("/dev/ds24330"); + + pr_info("sn: 0x%x, rev: 0x%x\n", sn, rev); + armlinux_set_revision(rev); + armlinux_set_serial(sn); +} diff --git a/arch/arm/boards/sama5d3xek/hw_version.h b/arch/arm/boards/sama5d3xek/hw_version.h new file mode 100644 index 000000000..ed9ea88d4 --- /dev/null +++ b/arch/arm/boards/sama5d3xek/hw_version.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __HW_REVISION_H__ +#define __HW_REVISION_H__ + +enum vendor_id { + VENDOR_UNKNOWN = 0, + VENDOR_EMBEST = 1, + VENDOR_FLEX = 2, + VENDOR_RONETIX = 3, + VENDOR_COGENT = 4, + VENDOR_PDA = 5, +}; + +#ifdef CONFIG_W1 +bool at91sama5d3xek_cm_is_vendor(enum vendor_id vid); +bool at91sama5d3xek_ek_is_vendor(enum vendor_id vid); +bool at91sama5d3xek_dm_is_vendor(enum vendor_id vid); +void at91sama5d3xek_devices_detect_hw(void); +#else +bool at91sama5d3xek_cm_is_vendor(enum vendor_id vid) +{ + return false; +} + +bool at91sama5d3xek_ek_is_vendor(enum vendor_id vid) +{ + return false; +} + +bool at91sama5d3xek_dm_is_vendor(enum vendor_id vid) +{ + return false; +} + +void at91sama5d3xek_devices_detect_hw(void) {} +#endif + +#endif /* __HW_REVISION_H__ */ diff --git a/arch/arm/boards/sama5d3xek/init.c b/arch/arm/boards/sama5d3xek/init.c new file mode 100644 index 000000000..110a83f80 --- /dev/null +++ b/arch/arm/boards/sama5d3xek/init.c @@ -0,0 +1,403 @@ +/* + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hw_version.h" + +struct w1_gpio_platform_data w1_pdata = { + .pin = AT91_PIN_PE25, + .ext_pullup_enable_pin = -EINVAL, + .is_open_drain = 0, +}; + +#if defined(CONFIG_NAND_ATMEL) +static struct atmel_nand_data nand_pdata = { + .ale = 21, + .cle = 22, + .det_pin = -EINVAL, + .rdy_pin = -EINVAL, + .enable_pin = -EINVAL, + .ecc_mode = NAND_ECC_HW, + .pmecc_sector_size = 512, + .pmecc_corr_cap = 4, +#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) + .bus_width_16 = 1, +#endif + .on_flash_bbt = 1, +}; + +static struct sam9_smc_config cm_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 6, + .nrd_pulse = 4, + .ncs_write_pulse = 5, + .nwe_pulse = 3, + + .read_cycle = 6, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, + .tdf_cycles = 1, +}; + +static void ek_add_device_nand(void) +{ + struct clk *clk = clk_get(NULL, "smc_clk"); + + clk_enable(clk); + + /* setup bus-width (8 or 16) */ + if (nand_pdata.bus_width_16) + cm_nand_smc_config.mode |= AT91_SMC_DBW_16; + else + cm_nand_smc_config.mode |= AT91_SMC_DBW_8; + + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(0, 3, &cm_nand_smc_config); + + at91_add_device_nand(&nand_pdata); +} +#else +static void ek_add_device_nand(void) {} +#endif + +#if defined(CONFIG_DRIVER_NET_MACB) +static struct at91_ether_platform_data macb_pdata = { + .phy_interface = PHY_INTERFACE_MODE_RMII, + .phy_addr = 0, +}; + +static bool used_23 = false; +static bool used_43 = false; + +static int ek_register_mac_address_23(int id) +{ + if (used_23) + return -EBUSY; + + used_23 = true; + + return w1_local_mac_address_register(id, "tml", "w1-23-0"); +} + +static int ek_register_mac_address_43(int id) +{ + if (used_43) + return -EBUSY; + + used_43 = true; + + return w1_local_mac_address_register(id, "tml", "w1-43-0"); +} + +static void ek_add_device_eth(void) +{ + if (w1_local_mac_address_register(0, "tml", "w1-2d-0")) + if (ek_register_mac_address_23(0)) + ek_register_mac_address_43(0); + + if (ek_register_mac_address_23(1)) + ek_register_mac_address_43(1); + + at91_add_device_eth(1, &macb_pdata); +} +#else +static void ek_add_device_eth(void) {} +#endif + +#if defined(CONFIG_DRIVER_VIDEO_ATMEL_HLCD) +/* + * LCD Controller + */ +static struct fb_videomode at91_tft_vga_modes[] = { + { + .name = "LG", + .refresh = 60, + .xres = 800, .yres = 480, + .pixclock = KHZ2PICOS(33260), + + .left_margin = 88, .right_margin = 168, + .upper_margin = 8, .lower_margin = 37, + .hsync_len = 128, .vsync_len = 2, + + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +/* Default output mode is TFT 24 bit */ +#define BPP_OUT_DEFAULT_LCDCFG5 (LCDC_LCDCFG5_MODE_OUTPUT_24BPP) + +/* Driver datas */ +static struct atmel_lcdfb_platform_data ek_lcdc_data = { + .lcdcon_is_backlight = true, + .default_bpp = 16, + .default_dmacon = ATMEL_LCDC_DMAEN, + .default_lcdcon2 = BPP_OUT_DEFAULT_LCDCFG5, + .guard_time = 9, + .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, + .mode_list = at91_tft_vga_modes, + .num_modes = ARRAY_SIZE(at91_tft_vga_modes), +}; + +static void ek_add_device_lcdc(void) +{ + at91_add_device_lcdc(&ek_lcdc_data); +} + +#else +static void ek_add_device_lcdc(void) {} +#endif + +#if defined(CONFIG_MCI_ATMEL) +/* + * MCI (SD/MMC) + */ +static struct atmel_mci_platform_data mci0_data = { + .bus_width = 4, + .detect_pin = AT91_PIN_PD17, + .wp_pin = -EINVAL, +}; + +static struct atmel_mci_platform_data mci1_data = { + .bus_width = 4, + .detect_pin = AT91_PIN_PD18, + .wp_pin = -EINVAL, +}; + +static void ek_add_device_mci(void) +{ + /* MMC0 */ + at91_add_device_mci(0, &mci0_data); + /* MMC1 */ + at91_add_device_mci(1, &mci1_data); +} +#else +static void ek_add_device_mci(void) {} +#endif + +#if defined(CONFIG_I2C_GPIO) +struct qt1070_platform_data qt1070_pdata = { + .irq_pin = AT91_PIN_PE31, +}; + +static struct i2c_board_info i2c_devices[] = { + { + .platform_data = &qt1070_pdata, + I2C_BOARD_INFO("qt1070", 0x1b), + }, +}; + +static void ek_add_device_i2c(void) +{ + at91_set_gpio_input(qt1070_pdata.irq_pin, 0); + at91_set_deglitch(qt1070_pdata.irq_pin, 1); + at91_add_device_i2c(1, i2c_devices, ARRAY_SIZE(i2c_devices)); + at91_add_device_i2c(0, NULL, 0); +} +#else +static void ek_add_device_i2c(void) {} +#endif + +#if defined(CONFIG_DRIVER_SPI_ATMEL) +static const struct spi_board_info ek_spi_devices[] = { + { + .name = "m25p80", + .chip_select = 0, + .max_speed_hz = 30 * 1000 * 1000, + .bus_num = 0, + } +}; + +static unsigned spi0_standard_cs[] = { AT91_PIN_PD13 }; +static struct at91_spi_platform_data spi_pdata = { + .chipselect = spi0_standard_cs, + .num_chipselect = ARRAY_SIZE(spi0_standard_cs), +}; + +static void ek_add_device_spi(void) +{ + spi_register_board_info(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); + at91_add_device_spi(0, &spi_pdata); +} +#else +static void ek_add_device_spi(void) {} +#endif + +#ifdef CONFIG_LED_GPIO +struct gpio_led leds[] = { + { + .gpio = AT91_PIN_PE24, + .active_low = 1, + .led = { + .name = "d1", + }, + }, { + .gpio = AT91_PIN_PE25, + .active_low = 1, + .led = { + .name = "d2", + }, + }, +}; + +static void ek_add_led(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(leds); i++) { + at91_set_gpio_output(leds[i].gpio, leds[i].active_low); + led_gpio_register(&leds[i]); + } + led_set_trigger(LED_TRIGGER_HEARTBEAT, &leds[0].led); +} +#else +static void ek_add_led(void) {} +#endif + +static int at91sama5d3xek_mem_init(void) +{ + at91_add_device_sdram(0); + + return 0; +} +mem_initcall(at91sama5d3xek_mem_init); + +static void ek_add_device_w1(void) +{ + at91_set_gpio_input(w1_pdata.pin, 0); + at91_set_multi_drive(w1_pdata.pin, 1); + add_generic_device_res("w1-gpio", DEVICE_ID_SINGLE, NULL, 0, &w1_pdata); + + at91sama5d3xek_devices_detect_hw(); +} + +#ifdef CONFIG_POLLER +/* + * The SiI9022A (HDMI) and QT1070 share the same irq + * but if the SiI9022A is not reset the irq is pull down + * So do it. As the SiI9022A need 1s to reset (500ms up then 500ms down then up) + * do it poller to do not slow down the boot + */ +static int hdmi_reset_pin = AT91_PIN_PC31; +static uint64_t hdmi_reset_start; +struct poller_struct hdmi_poller; + +static void hdmi_on_poller(struct poller_struct *poller) +{ + if (!is_timeout_non_interruptible(hdmi_reset_start, 500 * MSECOND)) + return; + + gpio_set_value(hdmi_reset_pin, 1); + + poller_unregister(poller); + ek_add_device_i2c(); +} + +static void hdmi_off_poller(struct poller_struct *poller) +{ + if (!is_timeout_non_interruptible(hdmi_reset_start, 500 * MSECOND)) + return; + + gpio_set_value(hdmi_reset_pin, 0); + + hdmi_reset_start = get_time_ns(); + poller->func = hdmi_on_poller; +} + +static void ek_add_device_hdmi(void) +{ + at91_set_gpio_output(hdmi_reset_pin, 1); + hdmi_reset_start = get_time_ns(); + hdmi_poller.func = hdmi_off_poller; + + poller_register(&hdmi_poller); +} +#else +static void ek_add_device_hdmi(void) +{ + ek_add_device_i2c(); +} +#endif + +static int at91sama5d3xek_devices_init(void) +{ + ek_add_device_w1(); + ek_add_device_hdmi(); + ek_add_device_nand(); + ek_add_led(); + ek_add_device_eth(); + ek_add_device_spi(); + ek_add_device_mci(); + ek_add_device_lcdc(); + + armlinux_set_bootparams((void *)(SAMA5_DDRCS + 0x100)); + + devfs_add_partition("nand0", 0x00000, SZ_256K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw"); + dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap"); + devfs_add_partition("nand0", SZ_256K, SZ_256K + SZ_128K, DEVFS_PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", SZ_512K + SZ_256K, SZ_256K, DEVFS_PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + devfs_add_partition("nand0", SZ_1M, SZ_256K, DEVFS_PARTITION_FIXED, "env_raw1"); + dev_add_bb_dev("env_raw1", "env1"); + + return 0; +} +device_initcall(at91sama5d3xek_devices_init); + +static int at91sama5d3xek_console_init(void) +{ + at91_register_uart(0, 0); + at91_register_uart(2, 0); + return 0; +} +console_initcall(at91sama5d3xek_console_init); diff --git a/arch/arm/boards/telit-evk-pro3/Makefile b/arch/arm/boards/telit-evk-pro3/Makefile new file mode 100644 index 000000000..eb072c016 --- /dev/null +++ b/arch/arm/boards/telit-evk-pro3/Makefile @@ -0,0 +1 @@ +obj-y += init.o diff --git a/arch/arm/boards/telit-evk-pro3/config.h b/arch/arm/boards/telit-evk-pro3/config.h new file mode 100644 index 000000000..7aeff30e8 --- /dev/null +++ b/arch/arm/boards/telit-evk-pro3/config.h @@ -0,0 +1,6 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define AT91_MAIN_CLOCK 6000000 /* 6.000 MHz crystal */ + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/telit-evk-pro3/env/boot/nand-ubi b/arch/arm/boards/telit-evk-pro3/env/boot/nand-ubi new file mode 100644 index 000000000..1987492df --- /dev/null +++ b/arch/arm/boards/telit-evk-pro3/env/boot/nand-ubi @@ -0,0 +1,10 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "nand (UBI)" + exit +fi + +global.bootm.image="/dev/nand0.kernel.bb" +#global.bootm.oftree="/env/oftree" +global.linux.bootargs.dyn.root="root=ubi0:rootfs ubi.mtd=nand0.rootfs rootfstype=ubifs" diff --git a/arch/arm/boards/telit-evk-pro3/env/init/config-board b/arch/arm/boards/telit-evk-pro3/env/init/config-board new file mode 100644 index 000000000..741b90213 --- /dev/null +++ b/arch/arm/boards/telit-evk-pro3/env/init/config-board @@ -0,0 +1,8 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.hostname=evk-pro3 +global.linux.bootargs.base="console=ttyS0,115200" +global.boot.default=nand-ubi diff --git a/arch/arm/boards/telit-evk-pro3/env/init/mtdparts-nand b/arch/arm/boards/telit-evk-pro3/env/init/mtdparts-nand new file mode 100644 index 000000000..58e859bb9 --- /dev/null +++ b/arch/arm/boards/telit-evk-pro3/env/init/mtdparts-nand @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "NAND partitions" + exit +fi + +mtdparts="0xC0000(nand0.bootstrap),256k(nand0.barebox)ro,128k(nand0.bareboxenv),3M(nand0.kernel),-(nand0.rootfs)" +kernelname="atmel_nand" + +mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/telit-evk-pro3/env/init/usb b/arch/arm/boards/telit-evk-pro3/env/init/usb new file mode 100644 index 000000000..47429f50a --- /dev/null +++ b/arch/arm/boards/telit-evk-pro3/env/init/usb @@ -0,0 +1,40 @@ +#!/bin/sh + +# Connect PC31 to GND to enable DFU +gpio_dfu=95 +gpio_name="PC31" +gpio_wait=5 + +product_id=0x1234 +vendor_id=0x4321 + +dfu_config="/dev/nand0.bootstrap.bb(bootstrap)sr,/dev/nand0.barebox.bb(barebox)sr,/dev/nand0.kernel.bb(kernel)r,/dev/nand0.rootfs.bb(rootfs)r" + +echo + +if [ $at91_udc0.vbus != 1 ]; then + echo "No USB Device cable plugged, normal boot" + exit +fi + +gpio_get_value ${gpio_dfu} +if [ $? = 0 ]; then + echo "${gpio_name} low value detected wait ${gpio_wait}s" + timeout -s -a ${gpio_wait} + + if [ $at91_udc0.vbus != 1 ]; then + echo "No USB Device cable plugged, normal boot" + exit + fi + + gpio_get_value ${gpio_dfu} + if [ $? = 0 ]; then + echo "Start DFU Mode" + dfu ${dfu_config} -P ${product_id} -V ${vendor_id} + exit + fi +fi + +global.autoboot_timeout=16 +echo "enable tty over USB Device, increase the boot delay to ${global.autoboot_timeout}s" +usbserial diff --git a/arch/arm/boards/telit-evk-pro3/init.c b/arch/arm/boards/telit-evk-pro3/init.c new file mode 100644 index 000000000..d5f1b3ea2 --- /dev/null +++ b/arch/arm/boards/telit-evk-pro3/init.c @@ -0,0 +1,176 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * Copyright (C) 2013 Fabio Porcedda , Telit + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BOOTSTRAP_SIZE 0xC0000 + +static struct atmel_nand_data nand_pdata = { + .ale = 21, + .cle = 22, + .det_pin = -EINVAL, + .rdy_pin = AT91_PIN_PC13, + .enable_pin = AT91_PIN_PC14, + .on_flash_bbt = 1, +}; + +static struct sam9_smc_config evk_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 3, + .nrd_pulse = 3, + .ncs_write_pulse = 3, + .nwe_pulse = 3, + + .read_cycle = 5, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, + .tdf_cycles = 2, +}; + +static void evk_add_device_nand(void) +{ + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(0, 3, &evk_nand_smc_config); + + at91_add_device_nand(&nand_pdata); +} + +static struct at91_ether_platform_data macb_pdata = { + .phy_interface = PHY_INTERFACE_MODE_RMII, + .phy_addr = 0, +}; + +static void evk_phy_reset(void) +{ + unsigned long rstc; + struct clk *clk = clk_get(NULL, "macb_clk"); + + clk_enable(clk); + + at91_set_gpio_input(AT91_PIN_PA14, 0); + at91_set_gpio_input(AT91_PIN_PA15, 0); + at91_set_gpio_input(AT91_PIN_PA17, 0); + at91_set_gpio_input(AT91_PIN_PA25, 0); + at91_set_gpio_input(AT91_PIN_PA26, 0); + at91_set_gpio_input(AT91_PIN_PA28, 0); + + rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL; + + /* Need to reset PHY -> 500ms reset */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0d << 8)) | + AT91_RSTC_URSTEN); + + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + + /* Wait for end hardware reset */ + while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)) + ; + + /* Restore NRST value */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | (rstc) | AT91_RSTC_URSTEN); +} + +/* + * MCI (SD/MMC) + */ +#if defined(CONFIG_MCI_ATMEL) +static struct atmel_mci_platform_data __initdata evk_mci_data = { + .bus_width = 4, + .detect_pin = AT91_PIN_PA27, + .wp_pin = AT91_PIN_PA25, +}; + +static void evk_usb_add_device_mci(void) +{ + at91_add_device_mci(0, &evk_mci_data); +} +#else +static void evk_usb_add_device_mci(void) {} +#endif + +/* + * USB Host port + */ +static struct at91_usbh_data __initdata evk_usbh_data = { + .ports = 2, + .vbus_pin = { -EINVAL, -EINVAL }, +}; + +/* + * USB Device port + */ +static struct at91_udc_data __initdata evk_udc_data = { + .vbus_pin = AT91_PIN_PC4, + .pullup_pin = -EINVAL, /* pull-up driven by UDC */ +}; + +static int evk_mem_init(void) +{ + at91_add_device_sdram(0); + + return 0; +} +mem_initcall(evk_mem_init); + +static int evk_devices_init(void) +{ + evk_add_device_nand(); + evk_phy_reset(); + at91_add_device_eth(0, &macb_pdata); + at91_add_device_usbh_ohci(&evk_usbh_data); + at91_add_device_udc(&evk_udc_data); + evk_usb_add_device_mci(); + + armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100)); + + devfs_add_partition("nand0", 0x00000, BOOTSTRAP_SIZE, + DEVFS_PARTITION_FIXED, "bootstrap_raw"); + dev_add_bb_dev("bootstrap_raw", "bootstrap"); + devfs_add_partition("nand0", BOOTSTRAP_SIZE, SZ_256K, + DEVFS_PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", BOOTSTRAP_SIZE + SZ_256K, SZ_128K, + DEVFS_PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + devfs_add_partition("nand0", BOOTSTRAP_SIZE + SZ_256K + SZ_128K, + SZ_128K, DEVFS_PARTITION_FIXED, "env_raw1"); + dev_add_bb_dev("env_raw1", "env1"); + + return 0; +} +device_initcall(evk_devices_init); + +static int evk_console_init(void) +{ + at91_register_uart(0, 0); + return 0; +} +console_initcall(evk_console_init); diff --git a/arch/arm/boards/tny-a926x/Makefile b/arch/arm/boards/tny-a926x/Makefile index eb072c016..36ea09fca 100644 --- a/arch/arm/boards/tny-a926x/Makefile +++ b/arch/arm/boards/tny-a926x/Makefile @@ -1 +1,10 @@ obj-y += init.o + +bootstrap-$(CONFIG_MACH_TNY_A9263) = tny_a9263_bootstrap.o +obj-$(CONFIG_AT91_BOOTSTRAP) += $(bootstrap-y) + +lowlevel_init-$(CONFIG_MACH_TNY_A9263) = tny_a9263_lowlevel_init.o + +obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y) + +pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y) diff --git a/arch/arm/boards/tny-a926x/init.c b/arch/arm/boards/tny-a926x/init.c index 5fe653173..4228254e3 100644 --- a/arch/arm/boards/tny-a926x/init.c +++ b/arch/arm/boards/tny-a926x/init.c @@ -113,7 +113,7 @@ static void tny_a9260_add_device_nand(void) #ifdef CONFIG_DRIVER_NET_MACB static struct at91_ether_platform_data macb_pdata = { - .is_rmii = 1, + .phy_interface = PHY_INTERFACE_MODE_RMII, .phy_addr = -1, }; @@ -160,16 +160,31 @@ static struct spi_board_info tny_a9g20_lpw_spi_devices[] = { }, }; -static int spi0_standard_cs[] = { AT91_PIN_PC11 }; -struct at91_spi_platform_data spi0_pdata = { - .chipselect = spi0_standard_cs, - .num_chipselect = ARRAY_SIZE(spi0_standard_cs), +static struct spi_board_info tny_a9263_spi_devices[] = { + { + .name = "mtd_dataflash", + .max_speed_hz = 15 * 1000 * 1000, + .bus_num = 0, + .chip_select = 0, + }, }; -static int spi1_standard_cs[] = { AT91_PIN_PC3 }; -struct at91_spi_platform_data spi1_pdata = { - .chipselect = spi1_standard_cs, - .num_chipselect = ARRAY_SIZE(spi1_standard_cs), +static int tny_a9263_spi0_standard_cs[] = { AT91_PIN_PA5 }; +struct at91_spi_platform_data tny_a9263_spi0_pdata = { + .chipselect = tny_a9263_spi0_standard_cs, + .num_chipselect = ARRAY_SIZE(tny_a9263_spi0_standard_cs), +}; + +static int tny_a9g20_spi0_standard_cs[] = { AT91_PIN_PC11 }; +struct at91_spi_platform_data tny_a9g20_spi0_pdata = { + .chipselect = tny_a9g20_spi0_standard_cs, + .num_chipselect = ARRAY_SIZE(tny_a9g20_spi0_standard_cs), +}; + +static int tny_a9g20_spi1_standard_cs[] = { AT91_PIN_PC3 }; +struct at91_spi_platform_data tny_a9g20_spi1_pdata = { + .chipselect = tny_a9g20_spi1_standard_cs, + .num_chipselect = ARRAY_SIZE(tny_a9g20_spi1_standard_cs), }; static void __init ek_add_device_udc(void) @@ -182,17 +197,19 @@ static void __init ek_add_device_udc(void) static void __init ek_add_device_spi(void) { - if (machine_is_tny_a9263()) - return; + if (machine_is_tny_a9263()) { + spi_register_board_info(tny_a9263_spi_devices, + ARRAY_SIZE(tny_a9263_spi_devices)); + at91_add_device_spi(0, &tny_a9263_spi0_pdata); - if (machine_is_tny_a9g20() && at91_is_low_power_sdram()) { + } else if (machine_is_tny_a9g20() && at91_is_low_power_sdram()) { spi_register_board_info(tny_a9g20_lpw_spi_devices, ARRAY_SIZE(tny_a9g20_lpw_spi_devices)); - at91_add_device_spi(1, &spi1_pdata); + at91_add_device_spi(1, &tny_a9g20_spi1_pdata); } else { spi_register_board_info(tny_a9g20_spi_devices, ARRAY_SIZE(tny_a9g20_spi_devices)); - at91_add_device_spi(0, &spi0_pdata); + at91_add_device_spi(0, &tny_a9g20_spi0_pdata); } } diff --git a/arch/arm/boards/tny-a926x/tny_a9263_bootstrap.c b/arch/arm/boards/tny-a926x/tny_a9263_bootstrap.c new file mode 100644 index 000000000..368c67744 --- /dev/null +++ b/arch/arm/boards/tny-a926x/tny_a9263_bootstrap.c @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + * + * Under GPLv2 + */ + +#include +#include +#include + +#ifdef CONFIG_MTD_DATAFLASH +void * bootstrap_board_read_dataflash(void) +{ + return bootstrap_read_devfs("dataflash0", false, 0xffc0, 204864, 204864); +} +#endif diff --git a/arch/arm/boards/tny-a926x/tny_a9263_lowlevel_init.c b/arch/arm/boards/tny-a926x/tny_a9263_lowlevel_init.c new file mode 100644 index 000000000..1b146da62 --- /dev/null +++ b/arch/arm/boards/tny-a926x/tny_a9263_lowlevel_init.c @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD + * + * Under GPLv2 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MASTER_CLOCK 180 + +#if MASTER_CLOCK == 200 +#define MASTER_PLL_MUL 100 +#else +#define MASTER_PLL_MUL 90 +#endif +#define MASTER_PLL_DIV 6 + +void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg) +{ + /* Disable Watchdog */ + cfg->wdt_mr = + AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | + AT91_WDT_WDV | + AT91_WDT_WDDIS | + AT91_WDT_WDD; + + /* define PDC[31:16] as DATA[31:16] */ + cfg->ebi_pio_pdr = 0xFFFF0000; + /* no pull-up for D[31:16] */ + cfg->ebi_pio_ppudr = 0xFFFF0000; + /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ + cfg->ebi_csa = + AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | + AT91_MATRIX_EBI0_CS1A_SDRAMC; + + cfg->smc_cs = 3; + cfg->smc_mode = + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_DBW_8 | + AT91_SMC_EXNWMODE_DISABLE | + AT91_SMC_TDF_(2); + cfg->smc_cycle = + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5); + cfg->smc_pulse = + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3); + cfg->smc_setup = + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0); + + cfg->pmc_mor = AT91_PMC_OSCBYPASS; + cfg->pmc_pllar = + AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ + AT91_PMC_PLLCOUNT | /* PLL Counter */ + (0 << 28) | /* PLL Clock Frequency Range */ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV); + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr1 = + AT91_PMC_CSS_SLOW | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr2 = + AT91_PMC_CSS_PLLA | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + + /* SDRAM */ + /* SDRAMC_TR - Refresh Timer register */ + cfg->sdrc_tr1 = 0x13C; + /* SDRAMC_CR - Configuration register*/ + cfg->sdrc_cr = + AT91_SDRAMC_NR_13 | + AT91_SDRAMC_NC_9 | + AT91_SDRAMC_NB_4 | + AT91_SDRAMC_CAS_2 | + AT91_SDRAMC_DBW_32 | + (2 << 8) | /* Write Recovery Delay */ + (7 << 12) | /* Row Cycle Delay */ + (2 << 16) | /* Row Precharge Delay */ + (2 << 20) | /* Row to Column Delay */ + (5 << 24) | /* Active to Precharge Delay */ + (8 << 28); /* Exit Self Refresh to Active Delay */ + + /* Memory Device Register -> SDRAM */ + cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM; + /* SDRAM_TR */ + cfg->sdrc_tr2 = (MASTER_CLOCK * 7); + + /* user reset enable */ + cfg->rstc_rmr = + AT91_RSTC_KEY | + AT91_RSTC_PROCRST | + AT91_RSTC_RSTTYP_WAKEUP | + AT91_RSTC_RSTTYP_WATCHDOG; +} diff --git a/arch/arm/boards/usb-a926x/Makefile b/arch/arm/boards/usb-a926x/Makefile index eb072c016..e314dd5b0 100644 --- a/arch/arm/boards/usb-a926x/Makefile +++ b/arch/arm/boards/usb-a926x/Makefile @@ -1 +1,10 @@ obj-y += init.o + +bootstrap-$(CONFIG_MACH_USB_A9263) = usb_a9263_bootstrap.o +obj-$(CONFIG_AT91_BOOTSTRAP) += $(bootstrap-y) + +lowlevel_init-$(CONFIG_MACH_USB_A9263) = usb_a9263_lowlevel_init.o + +obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y) + +pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y) diff --git a/arch/arm/boards/usb-a926x/init.c b/arch/arm/boards/usb-a926x/init.c index 95ac6a80c..0383280b6 100644 --- a/arch/arm/boards/usb-a926x/init.c +++ b/arch/arm/boards/usb-a926x/init.c @@ -51,6 +51,7 @@ static void usb_a9260_set_board_type(void) armlinux_set_architecture(MACH_TYPE_USB_A9260); } +#if defined(CONFIG_NAND_ATMEL) static struct atmel_nand_data nand_pdata = { .ale = 21, .cle = 22, @@ -111,9 +112,13 @@ static void usb_a9260_add_device_nand(void) at91_add_device_nand(&nand_pdata); } +#else +static void usb_a9260_add_device_nand(void) {} +#endif +#if defined(CONFIG_DRIVER_NET_MACB) static struct at91_ether_platform_data macb_pdata = { - .is_rmii = 1, + .phy_interface = PHY_INTERFACE_MODE_RMII, .phy_addr = -1, }; @@ -149,6 +154,16 @@ static void usb_a9260_phy_reset(void) AT91_RSTC_URSTEN); } +static void usb_a9260_add_device_eth(void) +{ + usb_a9260_phy_reset(); + at91_add_device_eth(0, &macb_pdata); +} +#else +static void usb_a9260_add_device_eth(void) {} +#endif + +#if defined(CONFIG_DRIVER_SPI_ATMEL) static const struct spi_board_info usb_a9263_spi_devices[] = { { .name = "mtd_dataflash", @@ -191,6 +206,9 @@ static void usb_a9260_add_spi(void) at91_add_device_spi(1, &spi_a9g20_pdata); } } +#else +static void usb_a9260_add_spi(void) {} +#endif #if defined(CONFIG_MCI_ATMEL) static struct atmel_mci_platform_data __initdata usb_a9260_mci_data = { @@ -205,11 +223,21 @@ static void usb_a9260_add_device_mci(void) static void usb_a9260_add_device_mci(void) {} #endif +#if defined(CONFIG_USB_OHCI) static struct at91_usbh_data ek_usbh_data = { .ports = 2, .vbus_pin = { -EINVAL, -EINVAL }, }; +static void usb_a9260_add_device_usb(void) +{ + at91_add_device_usbh_ohci(&ek_usbh_data); +} +#else +static void usb_a9260_add_device_usb(void) {} +#endif + +#ifdef CONFIG_USB_GADGET_DRIVER_AT91 /* * USB Device port */ @@ -225,7 +253,11 @@ static void __init ek_add_device_udc(void) at91_add_device_udc(&ek_udc_data); } +#else +static void __init ek_add_device_udc(void) {} +#endif +#ifdef CONFIG_LED_GPIO struct gpio_led led = { .gpio = AT91_PIN_PB21, .led = { @@ -241,6 +273,9 @@ static void __init ek_add_led(void) at91_set_gpio_output(led.gpio, led.active_low); led_gpio_register(&led); } +#else +static void ek_add_led(void) {} +#endif static int usb_a9260_mem_init(void) { @@ -356,11 +391,10 @@ static void usb_a9260_device_dab_mmx(void) {} static int usb_a9260_devices_init(void) { usb_a9260_add_device_nand(); - usb_a9260_phy_reset(); - at91_add_device_eth(0, &macb_pdata); usb_a9260_add_device_mci(); + usb_a9260_add_device_eth(); usb_a9260_add_spi(); - at91_add_device_usbh_ohci(&ek_usbh_data); + usb_a9260_add_device_usb(); ek_add_device_udc(); ek_add_led(); ek_add_device_button(); @@ -382,6 +416,7 @@ static int usb_a9260_devices_init(void) } device_initcall(usb_a9260_devices_init); +#ifndef CONFIG_CONSOLE_NONE static int usb_a9260_console_init(void) { struct device_d *dev; @@ -398,3 +433,4 @@ static int usb_a9260_console_init(void) return 0; } console_initcall(usb_a9260_console_init); +#endif diff --git a/arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c b/arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c new file mode 100644 index 000000000..368c67744 --- /dev/null +++ b/arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + * + * Under GPLv2 + */ + +#include +#include +#include + +#ifdef CONFIG_MTD_DATAFLASH +void * bootstrap_board_read_dataflash(void) +{ + return bootstrap_read_devfs("dataflash0", false, 0xffc0, 204864, 204864); +} +#endif diff --git a/arch/arm/boards/usb-a926x/usb_a9263_lowlevel_init.c b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel_init.c new file mode 100644 index 000000000..f6dc58e3f --- /dev/null +++ b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel_init.c @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD + * + * Under GPLv2 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MASTER_CLOCK 180 + +#if MASTER_CLOCK == 200 +#define MASTER_PLL_MUL 100 +#else +#define MASTER_PLL_MUL 90 +#endif +#define MASTER_PLL_DIV 6 + +void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg) +{ + /* Disable Watchdog */ + cfg->wdt_mr = + AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | + AT91_WDT_WDV | + AT91_WDT_WDDIS | + AT91_WDT_WDD; + + /* define PDC[31:16] as DATA[31:16] */ + cfg->ebi_pio_pdr = 0xFFFF0000; + /* no pull-up for D[31:16] */ + cfg->ebi_pio_ppudr = 0xFFFF0000; + /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ + cfg->ebi_csa = + AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | + AT91_MATRIX_EBI0_CS1A_SDRAMC; + + cfg->smc_cs = 3; + cfg->smc_mode = + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_DBW_8 | + AT91_SMC_EXNWMODE_DISABLE | + AT91_SMC_TDF_(2); + cfg->smc_cycle = + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5); + cfg->smc_pulse = + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3); + cfg->smc_setup = + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0); + + cfg->pmc_mor = AT91_PMC_OSCBYPASS; + cfg->pmc_pllar = + AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ + AT91_PMC_PLLCOUNT | /* PLL Counter */ + (0 << 28) | /* PLL Clock Frequency Range */ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV); + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr1 = + AT91_PMC_CSS_SLOW | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr2 = + AT91_PMC_CSS_PLLA | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + + /* SDRAM */ + /* SDRAMC_TR - Refresh Timer register */ + cfg->sdrc_tr1 = 0x13C; + /* SDRAMC_CR - Configuration register*/ + cfg->sdrc_cr = + AT91_SDRAMC_NR_13 | + AT91_SDRAMC_NB_4 | + AT91_SDRAMC_CAS_2 | + AT91_SDRAMC_DBW_32 | + (2 << 8) | /* Write Recovery Delay */ + (7 << 12) | /* Row Cycle Delay */ + (2 << 16) | /* Row Precharge Delay */ + (2 << 20) | /* Row to Column Delay */ + (5 << 24) | /* Active to Precharge Delay */ + (8 << 28); /* Exit Self Refresh to Active Delay */ + + if (IS_ENABLED(CONFIG_AT91_HAVE_SRAM_128M)) + cfg->sdrc_cr |= AT91_SDRAMC_NC_10; + else + cfg->sdrc_cr |= AT91_SDRAMC_NC_9; + + /* Memory Device Register -> SDRAM */ + cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM; + /* SDRAM_TR */ + cfg->sdrc_tr2 = (MASTER_CLOCK * 7); + + /* user reset enable */ + cfg->rstc_rmr = + AT91_RSTC_KEY | + AT91_RSTC_PROCRST | + AT91_RSTC_RSTTYP_WAKEUP | + AT91_RSTC_RSTTYP_WATCHDOG; +} diff --git a/arch/arm/configs/animeo_ip_defconfig b/arch/arm/configs/animeo_ip_defconfig new file mode 100644 index 000000000..23e7278ab --- /dev/null +++ b/arch/arm/configs/animeo_ip_defconfig @@ -0,0 +1,79 @@ +CONFIG_ARCH_AT91SAM9260=y +CONFIG_MACH_ANIMEO_IP=y +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 +CONFIG_AEABI=y +# CONFIG_CMD_ARM_CPUINFO is not set +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_PBL_IMAGE=y +CONFIG_MMU=y +CONFIG_EXPERIMENTAL=y +CONFIG_MALLOC_TLSF=y +CONFIG_PROMPT="Animeo-IP:" +CONFIG_BAUDRATE=38400 +CONFIG_LONGHELP=y +CONFIG_GLOB=y +CONFIG_PROMPT_HUSH_PS2="y" +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_CONSOLE_ACTIVATE_ALL=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/animeo_ip/env" +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +CONFIG_CMD_UIMAGE=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_MTEST=y +CONFIG_CMD_MTEST_ALTERNATIVE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_LED=y +CONFIG_CMD_LED_TRIGGER=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_WD=y +CONFIG_CMD_WD_DEFAULT_TIMOUT=16 +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y +CONFIG_NET_PING=y +CONFIG_MICREL_PHY=y +CONFIG_DRIVER_NET_MACB=y +# CONFIG_SPI is not set +CONFIG_MTD=y +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_NAND=y +# CONFIG_NAND_ECC_HW is not set +# CONFIG_NAND_ECC_HW_SYNDROME is not set +# CONFIG_NAND_ECC_HW_NONE is not set +CONFIG_NAND_ATMEL=y +CONFIG_UBI=y +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +CONFIG_MCI_ATMEL=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_GPIO_BICOLOR=y +CONFIG_LED_TRIGGERS=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_AT91SAM9X=y +CONFIG_FS_TFTP=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/at91sam9260ek_defconfig b/arch/arm/configs/at91sam9260ek_defconfig index b746bc801..9c5c7d520 100644 --- a/arch/arm/configs/at91sam9260ek_defconfig +++ b/arch/arm/configs/at91sam9260ek_defconfig @@ -1,4 +1,5 @@ CONFIG_ARCH_AT91SAM9260=y +CONFIG_MACH_AT91SAM9260EK=y CONFIG_AEABI=y # CONFIG_CMD_ARM_CPUINFO is not set CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y diff --git a/arch/arm/configs/at91sam9261ek_bootstrap_defconfig b/arch/arm/configs/at91sam9261ek_bootstrap_defconfig new file mode 100644 index 000000000..1511ecbb3 --- /dev/null +++ b/arch/arm/configs/at91sam9261ek_bootstrap_defconfig @@ -0,0 +1,25 @@ +CONFIG_ARCH_AT91SAM9261=y +CONFIG_AT91_BOOTSTRAP=y +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x27000 +CONFIG_AEABI=y +# CONFIG_CMD_ARM_CPUINFO is not set +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_PBL_IMAGE=y +CONFIG_MMU=y +CONFIG_MALLOC_DUMMY=y +CONFIG_PROMPT="9261-EK:" +CONFIG_SHELL_NONE=y +# CONFIG_TIMESTAMP is not set +CONFIG_CONSOLE_SIMPLE=y +# CONFIG_DEFAULT_ENVIRONMENT is not set +# CONFIG_SPI is not set +CONFIG_MTD=y +# CONFIG_MTD_WRITE is not set +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_NAND=y +# CONFIG_NAND_ECC_HW is not set +# CONFIG_NAND_ECC_HW_SYNDROME is not set +# CONFIG_NAND_ECC_HW_NONE is not set +CONFIG_NAND_ATMEL=y +# CONFIG_FS_RAMFS is not set +CONFIG_BOOTSTRAP_DEVFS=y diff --git a/arch/arm/configs/at91sam9261ek_defconfig b/arch/arm/configs/at91sam9261ek_defconfig index 5daa47b07..ac5c6638b 100644 --- a/arch/arm/configs/at91sam9261ek_defconfig +++ b/arch/arm/configs/at91sam9261ek_defconfig @@ -38,6 +38,7 @@ CONFIG_CMD_UIMAGE=y # CONFIG_CMD_BOOTU is not set CONFIG_CMD_RESET=y CONFIG_CMD_GO=y +CONFIG_CMD_SPLASH=y CONFIG_CMD_TIMEOUT=y CONFIG_CMD_PARTITION=y CONFIG_CMD_GPIO=y @@ -51,9 +52,10 @@ CONFIG_CMD_TFTP=y CONFIG_FS_TFTP=y CONFIG_NET_RESOLV=y CONFIG_DRIVER_NET_DM9K=y -# CONFIG_SPI is not set +CONFIG_DRIVER_SPI_ATMEL=y CONFIG_MTD=y # CONFIG_MTD_OOB_DEVICE is not set +CONFIG_MTD_DATAFLASH=y CONFIG_NAND=y # CONFIG_NAND_ECC_HW is not set # CONFIG_NAND_ECC_HW_SYNDROME is not set @@ -63,7 +65,10 @@ CONFIG_UBI=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DFU=y CONFIG_USB_GADGET_SERIAL=y +CONFIG_VIDEO=y +CONFIG_DRIVER_VIDEO_ATMEL=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_LED_TRIGGERS=y CONFIG_KEYBOARD_GPIO=y +CONFIG_PNG=y diff --git a/arch/arm/configs/at91sam9261ek_first_stage_defconfig b/arch/arm/configs/at91sam9261ek_first_stage_defconfig new file mode 100644 index 000000000..c4bc207ae --- /dev/null +++ b/arch/arm/configs/at91sam9261ek_first_stage_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARCH_AT91SAM9261=y +CONFIG_CMD_AT91_BOOT_TEST=y +CONFIG_AT91_LOAD_BAREBOX_SRAM=y +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x27000 +CONFIG_AEABI=y +# CONFIG_CMD_ARM_CPUINFO is not set +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_PBL_IMAGE=y +CONFIG_MMU=y +CONFIG_EXPERIMENTAL=y +CONFIG_MALLOC_TLSF=y +CONFIG_PROMPT="9261-EK:" +CONFIG_LONGHELP=y +CONFIG_GLOB=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_CONSOLE_ACTIVATE_ALL=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/at91sam9261ek/env" +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_PASSWD=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_UIMAGE=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_MTEST=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_LED=y +CONFIG_CMD_LED_TRIGGER=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y +CONFIG_NET_PING=y +CONFIG_NET_RESOLV=y +CONFIG_DRIVER_NET_DM9K=y +CONFIG_DRIVER_SPI_ATMEL=y +CONFIG_MTD=y +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_MTD_DATAFLASH=y +CONFIG_NAND=y +# CONFIG_NAND_ECC_HW is not set +# CONFIG_NAND_ECC_HW_SYNDROME is not set +# CONFIG_NAND_ECC_HW_NONE is not set +CONFIG_NAND_ATMEL=y +CONFIG_UBI=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DFU=y +CONFIG_USB_GADGET_SERIAL=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_TRIGGERS=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_FS_TFTP=y diff --git a/arch/arm/configs/at91sam9263ek_defconfig b/arch/arm/configs/at91sam9263ek_defconfig index 5d440525a..e78849a4a 100644 --- a/arch/arm/configs/at91sam9263ek_defconfig +++ b/arch/arm/configs/at91sam9263ek_defconfig @@ -36,6 +36,7 @@ CONFIG_CMD_UIMAGE=y CONFIG_CMD_RESET=y CONFIG_CMD_GO=y CONFIG_CMD_OFTREE=y +CONFIG_CMD_SPLASH=y CONFIG_CMD_TIMEOUT=y CONFIG_CMD_PARTITION=y CONFIG_CMD_GPIO=y @@ -63,6 +64,8 @@ CONFIG_UBI=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DFU=y CONFIG_USB_GADGET_SERIAL=y +CONFIG_VIDEO=y +CONFIG_DRIVER_VIDEO_ATMEL=y CONFIG_MCI=y CONFIG_MCI_ATMEL=y CONFIG_LED=y @@ -70,3 +73,4 @@ CONFIG_LED_GPIO=y CONFIG_LED_TRIGGERS=y CONFIG_FS_FAT=y CONFIG_FS_FAT_LFN=y +CONFIG_PNG=y diff --git a/arch/arm/configs/at91sam9m10g45ek_defconfig b/arch/arm/configs/at91sam9m10g45ek_defconfig index 0929f8e7b..1df34f751 100644 --- a/arch/arm/configs/at91sam9m10g45ek_defconfig +++ b/arch/arm/configs/at91sam9m10g45ek_defconfig @@ -1,10 +1,12 @@ CONFIG_ARCH_AT91SAM9G45=y +CONFIG_MACH_AT91SAM9M10G45EK=y CONFIG_AEABI=y # CONFIG_CMD_ARM_CPUINFO is not set CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_PBL_IMAGE=y CONFIG_MMU=y CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 +CONFIG_MALLOC_SIZE=0x800000 CONFIG_MALLOC_TLSF=y CONFIG_PROMPT="9M10G45-EK:" CONFIG_LONGHELP=y @@ -29,8 +31,6 @@ CONFIG_CMD_PASSWD=y CONFIG_CMD_ECHO_E=y CONFIG_CMD_LOADB=y CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MTEST=y -CONFIG_CMD_MTEST_ALTERNATIVE=y CONFIG_CMD_FLASH=y CONFIG_CMD_BOOTM_SHOW_TYPE=y CONFIG_CMD_BOOTM_VERBOSE=y @@ -38,13 +38,17 @@ CONFIG_CMD_BOOTM_INITRD=y CONFIG_CMD_BOOTM_OFTREE=y CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y CONFIG_CMD_UIMAGE=y +# CONFIG_CMD_BOOTU is not set CONFIG_CMD_RESET=y CONFIG_CMD_GO=y CONFIG_CMD_OFTREE=y +CONFIG_CMD_MTEST=y +CONFIG_CMD_MTEST_ALTERNATIVE=y CONFIG_CMD_TIMEOUT=y CONFIG_CMD_PARTITION=y CONFIG_CMD_MAGICVAR=y CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_SPLASH=y CONFIG_CMD_GPIO=y CONFIG_CMD_UNCOMPRESS=y CONFIG_CMD_LED=y @@ -58,6 +62,8 @@ CONFIG_FS_TFTP=y CONFIG_NET_NETCONSOLE=y CONFIG_NET_RESOLV=y CONFIG_DRIVER_NET_MACB=y +CONFIG_NET_USB=y +CONFIG_NET_USB_ASIX=y # CONFIG_SPI is not set CONFIG_MTD=y CONFIG_NAND=y @@ -66,6 +72,12 @@ CONFIG_NAND=y # CONFIG_NAND_ECC_HW_NONE is not set CONFIG_NAND_ATMEL=y CONFIG_UBI=y +CONFIG_USB=y +CONFIG_USB_EHCI=y +CONFIG_USB_EHCI_ATMEL=y +CONFIG_USB_STORAGE=y +CONFIG_VIDEO=y +CONFIG_DRIVER_VIDEO_ATMEL=y CONFIG_MCI=y CONFIG_MCI_STARTUP=y CONFIG_MCI_ATMEL=y @@ -75,4 +87,4 @@ CONFIG_LED_TRIGGERS=y CONFIG_FS_FAT=y CONFIG_FS_FAT_WRITE=y CONFIG_FS_FAT_LFN=y -CONFIG_LZO_DECOMPRESS=y +CONFIG_PNG=y diff --git a/arch/arm/configs/at91sam9m10ihd_defconfig b/arch/arm/configs/at91sam9m10ihd_defconfig new file mode 100644 index 000000000..2faaa6857 --- /dev/null +++ b/arch/arm/configs/at91sam9m10ihd_defconfig @@ -0,0 +1,99 @@ +CONFIG_ARCH_AT91SAM9G45=y +CONFIG_MACH_AT91SAM9M10IHD=y +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 +CONFIG_AEABI=y +# CONFIG_CMD_ARM_CPUINFO is not set +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_PBL_IMAGE=y +CONFIG_MMU=y +CONFIG_MALLOC_SIZE=0xa00000 +CONFIG_MALLOC_TLSF=y +CONFIG_PROMPT="9M10IHD:" +CONFIG_LONGHELP=y +CONFIG_PROMPT_HUSH_PS2=">" +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_PASSWD_SUM_SHA1=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/at91sam9m10ihd/env" +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_PASSWD=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_UBIFORMAT=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +CONFIG_CMD_BOOTM_AIMAGE=y +CONFIG_CMD_UIMAGE=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_MTEST=y +CONFIG_CMD_MTEST_ALTERNATIVE=y +CONFIG_CMD_SPLASH=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SPI=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y +CONFIG_NET_PING=y +CONFIG_NET_NETCONSOLE=y +CONFIG_NET_RESOLV=y +CONFIG_DRIVER_NET_MACB=y +CONFIG_NET_USB=y +CONFIG_NET_USB_ASIX=y +CONFIG_DRIVER_SPI_ATMEL=y +CONFIG_I2C=y +CONFIG_I2C_GPIO=y +CONFIG_MTD=y +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_MTD_M25P80=y +CONFIG_NAND=y +# CONFIG_NAND_ECC_HW is not set +# CONFIG_NAND_ECC_HW_SYNDROME is not set +# CONFIG_NAND_ECC_HW_NONE is not set +CONFIG_NAND_ATMEL=y +CONFIG_UBI=y +CONFIG_USB=y +CONFIG_USB_EHCI=y +CONFIG_USB_EHCI_ATMEL=y +CONFIG_USB_STORAGE=y +CONFIG_VIDEO=y +CONFIG_DRIVER_VIDEO_ATMEL=y +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +CONFIG_MCI_ATMEL=y +CONFIG_EEPROM_AT24=y +CONFIG_KEYBOARD_QT1070=y +CONFIG_W1=y +CONFIG_W1_MASTER_GPIO=y +CONFIG_W1_SLAVE_DS2431=y +CONFIG_W1_SLAVE_DS2433=y +CONFIG_FS_EXT4=y +CONFIG_FS_TFTP=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_PNG=y diff --git a/arch/arm/configs/at91sam9n12ek_defconfig b/arch/arm/configs/at91sam9n12ek_defconfig index 3e25c8ff9..3e3bd5109 100644 --- a/arch/arm/configs/at91sam9n12ek_defconfig +++ b/arch/arm/configs/at91sam9n12ek_defconfig @@ -6,6 +6,8 @@ CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_PBL_IMAGE=y CONFIG_MMU=y CONFIG_TEXT_BASE=0x26f00000 +CONFIG_MALLOC_SIZE=0xa00000 +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 CONFIG_EXPERIMENTAL=y CONFIG_MALLOC_TLSF=y CONFIG_PROMPT="9G20-EK:" @@ -40,6 +42,7 @@ CONFIG_CMD_GO=y CONFIG_CMD_OFTREE=y CONFIG_CMD_MTEST=y CONFIG_CMD_MTEST_ALTERNATIVE=y +CONFIG_CMD_SPLASH=y CONFIG_CMD_TIMEOUT=y CONFIG_CMD_PARTITION=y CONFIG_CMD_GPIO=y @@ -70,6 +73,8 @@ CONFIG_UBI=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DFU=y CONFIG_USB_GADGET_SERIAL=y +CONFIG_VIDEO=y +CONFIG_DRIVER_VIDEO_ATMEL_HLCD=y CONFIG_MCI=y CONFIG_MCI_STARTUP=y CONFIG_MCI_ATMEL=y @@ -83,4 +88,4 @@ CONFIG_FS_TFTP=y CONFIG_FS_FAT=y CONFIG_FS_FAT_WRITE=y CONFIG_FS_FAT_LFN=y -CONFIG_ZLIB=y +CONFIG_PNG=y diff --git a/arch/arm/configs/at91sam9x5ek_defconfig b/arch/arm/configs/at91sam9x5ek_defconfig index 0df86310a..d2cdaf279 100644 --- a/arch/arm/configs/at91sam9x5ek_defconfig +++ b/arch/arm/configs/at91sam9x5ek_defconfig @@ -4,6 +4,7 @@ CONFIG_AEABI=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_PBL_IMAGE=y CONFIG_MMU=y +CONFIG_MALLOC_SIZE=0xa00000 CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 CONFIG_EXPERIMENTAL=y CONFIG_MALLOC_TLSF=y @@ -40,6 +41,7 @@ CONFIG_CMD_GO=y CONFIG_CMD_OFTREE=y CONFIG_CMD_MTEST=y CONFIG_CMD_MTEST_ALTERNATIVE=y +CONFIG_CMD_SPLASH=y CONFIG_CMD_TIMEOUT=y CONFIG_CMD_PARTITION=y CONFIG_CMD_GPIO=y @@ -52,6 +54,8 @@ CONFIG_NET_NFS=y CONFIG_NET_PING=y CONFIG_NET_NETCONSOLE=y CONFIG_DRIVER_NET_MACB=y +CONFIG_NET_USB=y +CONFIG_NET_USB_ASIX=y CONFIG_DRIVER_SPI_ATMEL=y CONFIG_MTD_M25P80=y CONFIG_I2C=y @@ -66,6 +70,10 @@ CONFIG_NAND=y CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL_PMECC=y CONFIG_UBI=y +CONFIG_USB=y +CONFIG_USB_EHCI=y +CONFIG_USB_EHCI_ATMEL=y +CONFIG_USB_STORAGE=y CONFIG_MCI=y CONFIG_MCI_STARTUP=y CONFIG_MCI_ATMEL=y @@ -83,4 +91,4 @@ CONFIG_FS_TFTP=y CONFIG_FS_FAT=y CONFIG_FS_FAT_WRITE=y CONFIG_FS_FAT_LFN=y -CONFIG_ZLIB=y +CONFIG_PNG=y diff --git a/arch/arm/configs/sama5d3xek_defconfig b/arch/arm/configs/sama5d3xek_defconfig new file mode 100644 index 000000000..970ded52c --- /dev/null +++ b/arch/arm/configs/sama5d3xek_defconfig @@ -0,0 +1,95 @@ +CONFIG_ARCH_SAMA5D3=y +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x60000 +CONFIG_AEABI=y +# CONFIG_CMD_ARM_CPUINFO is not set +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_PBL_IMAGE=y +CONFIG_MMU=y +CONFIG_TEXT_BASE=0x26f00000 +CONFIG_MALLOC_SIZE=0xA00000 +CONFIG_EXPERIMENTAL=y +CONFIG_MALLOC_TLSF=y +CONFIG_PROMPT="A5D3X-EK:" +CONFIG_LONGHELP=y +CONFIG_GLOB=y +CONFIG_PROMPT_HUSH_PS2="y" +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_CONSOLE_ACTIVATE_ALL=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/sama5d3xek/env" +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +CONFIG_CMD_UIMAGE=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_MTEST=y +CONFIG_CMD_MTEST_ALTERNATIVE=y +CONFIG_CMD_SPLASH=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SPI=y +CONFIG_CMD_LED=y +CONFIG_CMD_LED_TRIGGER=y +CONFIG_CMD_MIITOOL=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y +CONFIG_NET_PING=y +CONFIG_NET_NETCONSOLE=y +CONFIG_MICREL_PHY=y +CONFIG_DRIVER_NET_MACB=y +CONFIG_DRIVER_SPI_ATMEL=y +CONFIG_I2C=y +CONFIG_I2C_GPIO=y +CONFIG_MTD=y +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_MTD_M25P80=y +CONFIG_NAND=y +# CONFIG_NAND_ECC_SOFT is not set +# CONFIG_NAND_ECC_HW_SYNDROME is not set +# CONFIG_NAND_ECC_HW_NONE is not set +CONFIG_NAND_ATMEL=y +CONFIG_NAND_ATMEL_PMECC=y +CONFIG_UBI=y +CONFIG_VIDEO=y +CONFIG_DRIVER_VIDEO_ATMEL_HLCD=y +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +CONFIG_MCI_ATMEL=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_TRIGGERS=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_QT1070=y +CONFIG_W1=y +CONFIG_W1_MASTER_GPIO=y +CONFIG_W1_SLAVE_DS2431=y +CONFIG_W1_SLAVE_DS2433=y +CONFIG_W1_DUAL_SEARCH=y +CONFIG_FS_EXT4=y +CONFIG_FS_TFTP=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_PNG=y diff --git a/arch/arm/configs/telit_evk_pro3_defconfig b/arch/arm/configs/telit_evk_pro3_defconfig new file mode 100644 index 000000000..050d1763b --- /dev/null +++ b/arch/arm/configs/telit_evk_pro3_defconfig @@ -0,0 +1,73 @@ +CONFIG_ARCH_AT91SAM9260=y +CONFIG_MACH_GE863=y +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 +CONFIG_AEABI=y +# CONFIG_CMD_ARM_CPUINFO is not set +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_PBL_IMAGE=y +CONFIG_MMU=y +CONFIG_EXPERIMENTAL=y +CONFIG_PROMPT="EVK-PRO3:" +CONFIG_LONGHELP=y +CONFIG_PROMPT_HUSH_PS2="y" +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_CONSOLE_ACTIVATE_ALL=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/telit-evk-pro3/env" +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_UBIFORMAT=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +CONFIG_CMD_UIMAGE=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_MTEST=y +CONFIG_CMD_MTEST_ALTERNATIVE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_LED=y +CONFIG_CMD_LED_TRIGGER=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y +CONFIG_NET_PING=y +CONFIG_NET_NETCONSOLE=y +CONFIG_DRIVER_NET_MACB=y +# CONFIG_SPI is not set +CONFIG_MTD=y +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_NAND=y +# CONFIG_NAND_ECC_HW is not set +# CONFIG_NAND_ECC_HW_SYNDROME is not set +# CONFIG_NAND_ECC_HW_NONE is not set +CONFIG_NAND_ATMEL=y +CONFIG_UBI=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DFU=y +CONFIG_USB_GADGET_SERIAL=y +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +CONFIG_MCI_ATMEL=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_TRIGGERS=y +CONFIG_FS_TFTP=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/tny_a9263_bootstrap_defconfig b/arch/arm/configs/tny_a9263_bootstrap_defconfig new file mode 100644 index 000000000..d968b6f00 --- /dev/null +++ b/arch/arm/configs/tny_a9263_bootstrap_defconfig @@ -0,0 +1,26 @@ +CONFIG_ARCH_AT91SAM9263=y +CONFIG_MACH_TNY_A9263=y +CONFIG_AT91_BOOTSTRAP=y +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x12000 +CONFIG_AEABI=y +# CONFIG_CMD_ARM_CPUINFO is not set +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ENVIRONMENT_VARIABLES=y +CONFIG_PBL_IMAGE=y +CONFIG_MMU=y +CONFIG_MALLOC_DUMMY=y +CONFIG_PROMPT="USB-9263:" +CONFIG_SHELL_NONE=y +CONFIG_CONSOLE_SIMPLE=y +# CONFIG_DEFAULT_ENVIRONMENT is not set +# CONFIG_SPI is not set +CONFIG_MTD=y +# CONFIG_MTD_WRITE is not set +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_NAND=y +# CONFIG_NAND_ECC_HW is not set +# CONFIG_NAND_ECC_HW_SYNDROME is not set +# CONFIG_NAND_ECC_HW_NONE is not set +CONFIG_NAND_ATMEL=y +# CONFIG_FS_RAMFS is not set +CONFIG_BOOTSTRAP_DEVFS=y diff --git a/arch/arm/configs/tny_a9263_defconfig b/arch/arm/configs/tny_a9263_defconfig index c199cca55..652fd3d45 100644 --- a/arch/arm/configs/tny_a9263_defconfig +++ b/arch/arm/configs/tny_a9263_defconfig @@ -62,6 +62,7 @@ CONFIG_DRIVER_NET_MACB=y CONFIG_DRIVER_SPI_ATMEL=y CONFIG_MTD=y # CONFIG_MTD_OOB_DEVICE is not set +CONFIG_MTD_DATAFLASH=y CONFIG_NAND=y # CONFIG_NAND_ECC_HW is not set # CONFIG_NAND_ECC_HW_SYNDROME is not set diff --git a/arch/arm/configs/usb_a9263_128mib_bootstrap_defconfig b/arch/arm/configs/usb_a9263_128mib_bootstrap_defconfig new file mode 100644 index 000000000..0411bd805 --- /dev/null +++ b/arch/arm/configs/usb_a9263_128mib_bootstrap_defconfig @@ -0,0 +1,27 @@ +CONFIG_ARCH_AT91SAM9263=y +CONFIG_MACH_USB_A9263=y +CONFIG_AT91_HAVE_SRAM_128M=y +CONFIG_AT91_BOOTSTRAP=y +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x12000 +CONFIG_AEABI=y +# CONFIG_CMD_ARM_CPUINFO is not set +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ENVIRONMENT_VARIABLES=y +CONFIG_PBL_IMAGE=y +CONFIG_MMU=y +CONFIG_MALLOC_DUMMY=y +CONFIG_PROMPT="USB-9263:" +CONFIG_SHELL_NONE=y +# CONFIG_CONSOLE_FULL is not set +# CONFIG_DEFAULT_ENVIRONMENT is not set +# CONFIG_SPI is not set +CONFIG_MTD=y +# CONFIG_MTD_WRITE is not set +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_NAND=y +# CONFIG_NAND_ECC_HW is not set +# CONFIG_NAND_ECC_HW_SYNDROME is not set +# CONFIG_NAND_ECC_HW_NONE is not set +CONFIG_NAND_ATMEL=y +# CONFIG_FS_RAMFS is not set +CONFIG_BOOTSTRAP_DEVFS=y diff --git a/arch/arm/configs/usb_a9263_bootstrap_defconfig b/arch/arm/configs/usb_a9263_bootstrap_defconfig new file mode 100644 index 000000000..78c1c8f7b --- /dev/null +++ b/arch/arm/configs/usb_a9263_bootstrap_defconfig @@ -0,0 +1,26 @@ +CONFIG_ARCH_AT91SAM9263=y +CONFIG_MACH_USB_A9263=y +CONFIG_AT91_BOOTSTRAP=y +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x12000 +CONFIG_AEABI=y +# CONFIG_CMD_ARM_CPUINFO is not set +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ENVIRONMENT_VARIABLES=y +CONFIG_PBL_IMAGE=y +CONFIG_MMU=y +CONFIG_MALLOC_DUMMY=y +CONFIG_PROMPT="USB-9263:" +CONFIG_SHELL_NONE=y +# CONFIG_CONSOLE_FULL is not set +# CONFIG_DEFAULT_ENVIRONMENT is not set +# CONFIG_SPI is not set +CONFIG_MTD=y +# CONFIG_MTD_WRITE is not set +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_NAND=y +# CONFIG_NAND_ECC_HW is not set +# CONFIG_NAND_ECC_HW_SYNDROME is not set +# CONFIG_NAND_ECC_HW_NONE is not set +CONFIG_NAND_ATMEL=y +# CONFIG_FS_RAMFS is not set +CONFIG_BOOTSTRAP_DEVFS=y diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index f2a2ee781..14bab550c 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -18,11 +18,18 @@ config SOC_AT91SAM9 select AT91SAM9_SMC select AT91SAM9_TIMER +config SOC_SAMA5 + bool + select CPU_V7 + select AT91SAM9_SMC + select AT91SAM9_TIMER + config ARCH_TEXT_BASE hex default 0x73f00000 if ARCH_AT91SAM9G45 default 0x26f00000 if ARCH_AT91SAM9X5 default 0x20f00000 if ARCH_AT91RM9200 + default 0x21f00000 if MACH_ANIMEO_IP default 0x23f00000 config BOARDINFO @@ -32,9 +39,11 @@ config BOARDINFO default "Atmel at91sam9263-ek" if MACH_AT91SAM9263EK default "Atmel at91sam9g10-ek" if MACH_AT91SAM9G10EK default "Atmel at91sam9g20-ek" if MACH_AT91SAM9G20EK + default "Atmel at91sam9m10ihd" if MACH_AT91SAM9M10IHD default "Atmel at91sam9m10g45-ek" if MACH_AT91SAM9M10G45EK default "Atmel at91sam9n12-ek" if MACH_AT91SAM9N12EK default "Atmel at91sam9x5-ek" if MACH_AT91SAM9X5EK + default "Atmel sama5d3x-ek" if MACH_SAMA5D3XEK default "Bucyrus MMC-CPU" if MACH_MMCCPU default "Calao USB-A9260" if MACH_USB_A9260 default "Calao USB-A9263" if MACH_USB_A9263 @@ -47,6 +56,8 @@ config BOARDINFO default "Calao TNY-A9263" if MACH_TNY_A9263 default "Calao TNY-A9G20" if MACH_TNY_A9G20 default "Calao QIL-A9260" if MACH_QIL_A9260 + default "Somfy Animeo IP" if MACH_ANIMEO_IP + default "Telit EVK-PRO3" if MACH_GE863 config HAVE_NAND_ATMEL_BUSWIDTH_16 bool @@ -60,6 +71,12 @@ config AT91SAM9_RESET config AT91SAM9G45_RESET bool +config HAVE_AT91_LOAD_BAREBOX_SRAM + bool + +config AT91SAM9_LOWLEVEL_INIT + bool + comment "Atmel AT91 System-on-Chip" config SOC_AT91RM9200 @@ -75,6 +92,7 @@ config SOC_AT91SAM9260 select HAVE_AT91_DBGU0 select HAS_MACB select AT91SAM9_RESET + select AT91SAM9_LOWLEVEL_INIT help Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE or AT91SAM9G20 SoC. @@ -84,6 +102,7 @@ config SOC_AT91SAM9261 select SOC_AT91SAM9 select HAVE_AT91_DBGU0 select AT91SAM9_RESET + select AT91SAM9_LOWLEVEL_INIT help Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC. @@ -93,6 +112,8 @@ config SOC_AT91SAM9263 select HAVE_AT91_DBGU1 select HAS_MACB select AT91SAM9_RESET + select AT91SAM9_LOWLEVEL_INIT + select HAVE_AT91_LOAD_BAREBOX_SRAM config SOC_AT91SAM9G45 bool @@ -140,6 +161,7 @@ config ARCH_AT91SAM9260 config ARCH_AT91SAM9261 bool "AT91SAM9261" select SOC_AT91SAM9261 + select HAVE_AT91_LOAD_BAREBOX_SRAM config ARCH_AT91SAM9263 bool "AT91SAM9263" @@ -165,6 +187,13 @@ config ARCH_AT91SAM9N12 bool "AT91SAM9N12" select SOC_AT91SAM9N12 +config ARCH_SAMA5D3 + bool "SAMA5D3x" + select SOC_SAMA5 + select HAVE_AT91_DBGU1 + select HAS_MACB + select AT91SAM9G45_RESET + endchoice config ARCH_BAREBOX_MAX_BARE_INIT_SIZE @@ -177,6 +206,7 @@ config ARCH_BAREBOX_MAX_BARE_INIT_SIZE default 0xF000 if ARCH_AT91SAM9G45 default 0x6000 if ARCH_AT91SAM9X5 default 0x6000 if ARCH_AT91SAM9N12 + default 0x6000 if ARCH_SAMA5D3 default 0xffffffff config SUPPORT_CALAO_DAB_MMX @@ -210,6 +240,9 @@ if ARCH_AT91SAM9260 choice prompt "AT91SAM9260 Board Type" +config MACH_ANIMEO_IP + bool "Somfy Animeo IP" + config MACH_AT91SAM9260EK bool "Atmel AT91SAM9260-EK" select HAVE_NAND_ATMEL_BUSWIDTH_16 @@ -236,6 +269,13 @@ config MACH_USB_A9260 Select this if you are using a Calao Systems USB-A9260. +config MACH_GE863 + bool "Telit EVK-PRO3" + select HAVE_DEFAULT_ENVIRONMENT_NEW + help + Say y here if you are using Telit EVK-PRO3 with GE863-PRO3 + + endchoice endif @@ -250,6 +290,8 @@ choice config MACH_AT91SAM9261EK bool "Atmel AT91SAM9261-EK Evaluation Kit" select HAS_DM9000 + select HAVE_AT91_DATAFLASH_CARD + select MACH_HAS_LOWLEVEL_INIT select HAVE_NAND_ATMEL_BUSWIDTH_16 help Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit. @@ -352,12 +394,14 @@ config MACH_PM9263 config MACH_TNY_A9263 bool "CALAO TNY-A9263" select SUPPORT_CALAO_MOB_TNY_MD2 + select MACH_HAS_LOWLEVEL_INIT help Select this if you are using a Calao Systems TNY-A9263. config MACH_USB_A9263 bool "CALAO USB-A9263" + select MACH_HAS_LOWLEVEL_INIT help Select this if you are using a Calao Systems USB-A9263. @@ -371,6 +415,11 @@ if ARCH_AT91SAM9G45 choice prompt "AT91SAM9G45 or AT91SAM9M10 Board Type" +config MACH_AT91SAM9M10IHD + bool "Atmel AT91SAM9M10IDH Tablet" + help + Select this if you are using Atmel's AT91SAM9M10IHD Tablet + config MACH_AT91SAM9M10G45EK bool "Atmel AT91SAM9M10G45-EK Evaluation Kit" select HAVE_NAND_ATMEL_BUSWIDTH_16 @@ -423,6 +472,22 @@ endif # ---------------------------------------------------------- +if ARCH_SAMA5D3 + +choice + prompt "SAMA5D3 Board Type" + +config MACH_SAMA5D3XEK + bool "Atmel SAMA5D3X Evaluation Kit" + help + Select this if you are using Atmel's SAMA5D3X-EK Evaluation Kit. + +endchoice + +endif + +# ---------------------------------------------------------- + comment "AT91 Board Options" config MTD_AT91_DATAFLASH_CARD @@ -480,8 +545,33 @@ config CALAO_MB_QIL_A9260 bool "MB-QIL A9260 Motherboard Board support" depends on MACH_QIL_A9260 +if COMMAND_SUPPORT + config CMD_AT91MUX bool "at91mux dump command" default y +config CMD_AT91CLK + bool "at91clk dump command" + default y + +config CMD_AT91_BOOT_TEST + bool "at91_boot_test" + help + allow to upload a boot binary to sram and execute it + useful to test bootstrap or barebox lowlevel init + +endif + +config AT91_BOOTSTRAP + bool "at91 bootstrap" + depends on MACH_HAS_LOWLEVEL_INIT + select BOOTSTRAP + +config AT91_LOAD_BAREBOX_SRAM + bool "at91 laad barebox in sram" + depends on MACH_HAS_LOWLEVEL_INIT + depends on SHELL_NONE || HAVE_AT91_LOAD_BAREBOX_SRAM + default y if SHELL_NONE + endif diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 53b4dd89a..f6c850084 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -1,6 +1,11 @@ obj-y += setup.o clock.o gpio.o +obj-$(CONFIG_CMD_AT91_BOOT_TEST) += boot_test_cmd.o -lowlevel_init-y = at91sam926x_lowlevel_init.o +obj-$(CONFIG_AT91_BOOTSTRAP) += bootstrap.o +lowlevel_init-$(CONFIG_AT91SAM9_LOWLEVEL_INIT) = at91sam926x_lowlevel_init.o +lowlevel_init-$(CONFIG_SOC_AT91SAM9260) += at91sam9260_lowlevel_init.o +lowlevel_init-$(CONFIG_SOC_AT91SAM9261) += at91sam9261_lowlevel_init.o +lowlevel_init-$(CONFIG_SOC_AT91SAM9263) += at91sam9263_lowlevel_init.o lowlevel_init-$(CONFIG_ARCH_AT91RM9200) = at91rm9200_lowlevel_init.o obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y) @@ -22,3 +27,4 @@ obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam9260_devices.o obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam9g45_devices.o obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam9x5_devices.o obj-$(CONFIG_ARCH_AT91SAM9N12) += at91sam9n12.o at91sam9n12_devices.o +obj-$(CONFIG_ARCH_SAMA5D3) += sama5d3.o sama5d3_devices.o diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c index 4109172a5..82862d7c3 100644 --- a/arch/arm/mach-at91/at91rm9200_devices.c +++ b/arch/arm/mach-at91/at91rm9200_devices.c @@ -25,6 +25,9 @@ void at91_add_device_sdram(u32 size) { + if (!size) + size = at91rm9200_get_sdram_size(); + arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size); add_mem_device("sram0", AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE, IORESOURCE_MEM_WRITEABLE); @@ -37,9 +40,18 @@ void at91_add_device_sdram(u32 size) #if defined(CONFIG_USB_OHCI) void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) { + int i; + if (!data) return; + /* Enable VBus control for UHP ports */ + for (i = 0; i < data->ports; i++) { + if (gpio_is_valid(data->vbus_pin[i])) + at91_set_gpio_output(data->vbus_pin[i], + data->vbus_pin_active_low[i]); + } + add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91RM9200_UHP_BASE, 1024 * 1024, IORESOURCE_MEM, data); } @@ -91,7 +103,7 @@ void __init at91_add_device_eth(int id, struct at91_ether_platform_data *data) at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */ at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */ - if (!data->is_rmii) { + if (data->phy_interface != PHY_INTERFACE_MODE_RMII) { at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */ at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */ at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */ diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index a893a9581..6e8c37b14 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c @@ -42,9 +42,18 @@ void at91_add_device_sdram(u32 size) #if defined(CONFIG_USB_OHCI) void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) { + int i; + if (!data) return; + /* Enable VBus control for UHP ports */ + for (i = 0; i < data->ports; i++) { + if (gpio_is_valid(data->vbus_pin[i])) + at91_set_gpio_output(data->vbus_pin[i], + data->vbus_pin_active_low[i]); + } + add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91SAM9260_UHP_BASE, 1024 * 1024, IORESOURCE_MEM, data); } @@ -89,7 +98,7 @@ void at91_add_device_eth(int id, struct at91_ether_platform_data *data) at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */ at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */ - if (!data->is_rmii) { + if (data->phy_interface != PHY_INTERFACE_MODE_RMII) { at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */ at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */ at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */ diff --git a/arch/arm/mach-at91/at91sam9260_lowlevel_init.c b/arch/arm/mach-at91/at91sam9260_lowlevel_init.c new file mode 100644 index 000000000..c2cf8bfcb --- /dev/null +++ b/arch/arm/mach-at91/at91sam9260_lowlevel_init.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD + * + * Under GPLv2 + */ + +#define __LOWLEVEL_INIT__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void __naked __bare_init reset(void) +{ + common_reset(); + + arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16); + + at91sam926x_lowlevel_init(IOMEM(AT91SAM9260_BASE_PIOC), false, + AT91_MATRIX_EBICSA); +} diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index becd25f37..e9ca51c82 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c @@ -45,9 +45,18 @@ void at91_add_device_sdram(u32 size) #if defined(CONFIG_USB_OHCI) void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) { + int i; + if (!data) return; + /* Enable VBus control for UHP ports */ + for (i = 0; i < data->ports; i++) { + if (gpio_is_valid(data->vbus_pin[i])) + at91_set_gpio_output(data->vbus_pin[i], + data->vbus_pin_active_low[i]); + } + add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91SAM9261_UHP_BASE, 1024 * 1024, IORESOURCE_MEM, data); } @@ -199,6 +208,59 @@ void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) void __init at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) {} #endif +/* -------------------------------------------------------------------- + * LCD Controller + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_DRIVER_VIDEO_ATMEL) +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) +{ + BUG_ON(!data); + + data->have_intensity_bit = true; + +#if defined(CONFIG_FB_ATMEL_STN) + at91_set_A_periph(AT91_PIN_PB0, 0); /* LCDVSYNC */ + at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ + at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PB5, 0); /* LCDD0 */ + at91_set_A_periph(AT91_PIN_PB6, 0); /* LCDD1 */ + at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ +#else + at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ + at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */ + at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */ + at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */ + at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */ + at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */ + at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */ + at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ + at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ +#endif + + add_generic_device("atmel_lcdfb", DEVICE_ID_SINGLE, NULL, AT91SAM9261_LCDC_BASE, SZ_4K, + IORESOURCE_MEM, data); +} +#else +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) {} +#endif + resource_size_t __init at91_configure_dbgu(void) { at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */ diff --git a/arch/arm/mach-at91/at91sam9261_lowlevel_init.c b/arch/arm/mach-at91/at91sam9261_lowlevel_init.c new file mode 100644 index 000000000..a2e065fe7 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9261_lowlevel_init.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD + * + * Under GPLv2 + */ + +#define __LOWLEVEL_INIT__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void __naked __bare_init reset(void) +{ + common_reset(); + + arm_setup_stack(AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 16); + + at91sam926x_lowlevel_init(IOMEM(AT91SAM9261_BASE_PIOC), false, + AT91_MATRIX_EBICSA); +} diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index eeea1cea2..49d280dd0 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c @@ -175,6 +175,7 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_DEV_ID("at91rm9200-gpio3", &pioCDE_clk), CLKDEV_DEV_ID("at91rm9200-gpio4", &pioCDE_clk), CLKDEV_DEV_ID("at91-pit", &mck), + CLKDEV_CON_DEV_ID("hck1", "atmel_lcdfb", &lcdc_clk), }; static struct clk_lookup usart_clocks_lookups[] = { diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index b72cc5a84..528a07b7a 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c @@ -50,7 +50,8 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) /* Enable VBus control for UHP ports */ for (i = 0; i < data->ports; i++) { if (gpio_is_valid(data->vbus_pin[i])) - at91_set_gpio_output(data->vbus_pin[i], 0); + at91_set_gpio_output(data->vbus_pin[i], + data->vbus_pin_active_low[i]); } add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91SAM9263_UHP_BASE, @@ -96,7 +97,7 @@ void at91_add_device_eth(int id, struct at91_ether_platform_data *data) at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */ at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */ - if (!data->is_rmii) { + if (data->phy_interface != PHY_INTERFACE_MODE_RMII) { at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */ at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */ at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */ @@ -249,6 +250,48 @@ void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) void __init at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) {} #endif + +/* -------------------------------------------------------------------- + * LCD Controller + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_DRIVER_VIDEO_ATMEL) +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) +{ + BUG_ON(!data); + + data->have_intensity_bit = true; + + at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */ + at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */ + at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */ + at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */ + at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */ + at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */ + at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */ + at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */ + at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */ + + add_generic_device("atmel_lcdfb", DEVICE_ID_SINGLE, NULL, AT91SAM9263_LCDC_BASE, SZ_4K, + IORESOURCE_MEM, data); +} +#else +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) {} +#endif + resource_size_t __init at91_configure_dbgu(void) { at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ diff --git a/arch/arm/mach-at91/at91sam9263_lowlevel_init.c b/arch/arm/mach-at91/at91sam9263_lowlevel_init.c new file mode 100644 index 000000000..526065854 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9263_lowlevel_init.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD + * + * Under GPLv2 + */ + +#define __LOWLEVEL_INIT__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void __naked __bare_init reset(void) +{ + common_reset(); + + arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE - 16); + + at91sam926x_lowlevel_init(IOMEM(AT91SAM9263_BASE_PIOD), true, + AT91_MATRIX_EBI0CSA); +} diff --git a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c index cfae9824d..8b9b33e2e 100644 --- a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c +++ b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c @@ -19,8 +19,10 @@ #include #include #include +#include #include #include +#include static void inline access_sdram(void) { @@ -36,51 +38,54 @@ static void inline pmc_check_mckrdy(void) } while (!(r & AT91_PMC_MCKRDY)); } -void __naked __bare_init reset(void) +static int inline running_in_sram(void) +{ + u32 addr = get_pc(); + + addr >>= 28; + return addr == 0; +} + +void __bare_init at91sam926x_lowlevel_init(void *pio, bool is_pio_asr, + u32 matrix_csa) { u32 r; int i; + int in_sram = running_in_sram(); + struct at91sam926x_lowlevel_cfg cfg; - common_reset(); + at91sam926x_lowlevel_board_config(&cfg); - __raw_writel(CONFIG_SYS_WDTC_WDMR_VAL, AT91_BASE_WDT + AT91_WDT_MR); + __raw_writel(cfg.wdt_mr, AT91_BASE_WDT + AT91_WDT_MR); /* configure PIOx as EBI0 D[16-31] */ -#ifdef CONFIG_ARCH_AT91SAM9263 - __raw_writel(CONFIG_SYS_PIOD_PDR_VAL1, AT91_BASE_PIOD + PIO_PDR); - __raw_writel(CONFIG_SYS_PIOD_PPUDR_VAL, AT91_BASE_PIOD + PIO_PUDR); - __raw_writel(CONFIG_SYS_PIOD_PPUDR_VAL, AT91_BASE_PIOD + PIO_ASR); -#else - __raw_writel(CONFIG_SYS_PIOC_PDR_VAL1, AT91_BASE_PIOC + PIO_PDR); - __raw_writel(CONFIG_SYS_PIOC_PPUDR_VAL, AT91_BASE_PIOC + PIO_PUDR); -#endif + __raw_writel(cfg.ebi_pio_pdr, pio + PIO_PDR); + __raw_writel(cfg.ebi_pio_ppudr, pio + PIO_PUDR); + if (is_pio_asr) + __raw_writel(cfg.ebi_pio_ppudr, pio + PIO_ASR); -#if defined(AT91_MATRIX_EBI0CSA) - at91_sys_write(AT91_MATRIX_EBI0CSA, CONFIG_SYS_MATRIX_EBI0CSA_VAL); -#else /* AT91_MATRIX_EBICSA */ - at91_sys_write(AT91_MATRIX_EBICSA, CONFIG_SYS_MATRIX_EBICSA_VAL); -#endif + at91_sys_write(matrix_csa, cfg.ebi_csa); /* flash */ - at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_MODE, CONFIG_SYS_SMC_MODE_VAL); + at91_smc_write(cfg.smc_cs, AT91_SMC_MODE, cfg.smc_mode); - at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_CYCLE, CONFIG_SYS_SMC_CYCLE_VAL); + at91_smc_write(cfg.smc_cs, AT91_SMC_CYCLE, cfg.smc_cycle); - at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_PULSE, CONFIG_SYS_SMC_PULSE_VAL); + at91_smc_write(cfg.smc_cs, AT91_SMC_PULSE, cfg.smc_pulse); - at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_SETUP, CONFIG_SYS_SMC_SETUP_VAL); + at91_smc_write(cfg.smc_cs, AT91_SMC_SETUP, cfg.smc_setup); /* * PMC Check if the PLL is already initialized */ r = at91_pmc_read(AT91_PMC_MCKR); - if (r & AT91_PMC_CSS) + if (r & AT91_PMC_CSS && !in_sram) goto end; /* * Enable the Main Oscillator */ - at91_pmc_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL); + at91_pmc_write(AT91_CKGR_MOR, cfg.pmc_mor); do { r = at91_pmc_read(AT91_PMC_SR); @@ -89,7 +94,7 @@ void __naked __bare_init reset(void) /* * PLLAR: x MHz for PCK */ - at91_pmc_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL); + at91_pmc_write(AT91_CKGR_PLLAR, cfg.pmc_pllar); do { r = at91_pmc_read(AT91_PMC_SR); @@ -98,14 +103,14 @@ void __naked __bare_init reset(void) /* * PCK/x = MCK Master Clock from SLOW */ - at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR1_VAL); + at91_pmc_write(AT91_PMC_MCKR, cfg.pmc_mckr1); pmc_check_mckrdy(); /* * PCK/x = MCK Master Clock from PLLA */ - at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL); + at91_pmc_write(AT91_PMC_MCKR, cfg.pmc_mckr2); pmc_check_mckrdy(); @@ -117,20 +122,20 @@ void __naked __bare_init reset(void) * SDRAMC Check if Refresh Timer Counter is already initialized */ r = at91_sys_read(AT91_SDRAMC_TR); - if (r) + if (r && !in_sram) goto end; /* SDRAMC_MR : Normal Mode */ at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL); /* SDRAMC_TR - Refresh Timer register */ - at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL1); + at91_sys_write(AT91_SDRAMC_TR, cfg.sdrc_tr1); /* SDRAMC_CR - Configuration register*/ - at91_sys_write(AT91_SDRAMC_CR, CONFIG_SYS_SDRC_CR_VAL); + at91_sys_write(AT91_SDRAMC_CR, cfg.sdrc_cr); /* Memory Device Type */ - at91_sys_write(AT91_SDRAMC_MDR, CONFIG_SYS_SDRC_MDR_VAL); + at91_sys_write(AT91_SDRAMC_MDR, cfg.sdrc_mdr); /* SDRAMC_MR : Precharge All */ at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE); @@ -158,18 +163,25 @@ void __naked __bare_init reset(void) access_sdram(); /* SDRAMC_TR : Refresh Timer Counter */ - at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL2); + at91_sys_write(AT91_SDRAMC_TR, cfg.sdrc_tr2); /* access SDRAM */ access_sdram(); /* User reset enable*/ - at91_sys_write(AT91_RSTC_MR, CONFIG_SYS_RSTC_RMR_VAL); + at91_sys_write(AT91_RSTC_MR, cfg.rstc_rmr); #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP /* MATRIX_MCFG - REMAP all masters */ at91_sys_write(AT91_MATRIX_MCFG0, 0x1FF); #endif + /* + * When boot from external boot + * we need to enable mck and ohter clock + * so enable all of them + * We will shutdown what we don't need later + */ + at91_pmc_write(AT91_PMC_PCER, 0xffffffff); end: board_init_lowlevel_return(); diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 7118efe9a..deb9b6295 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -187,6 +187,7 @@ static struct clk *periph_clocks[] __initdata = { static struct clk_lookup periph_clocks_lookups[] = { /* One additional fake clock for ohci */ CLKDEV_CON_ID("ohci_clk", &uhphs_clk), + CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci0", &mmc0_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk), @@ -197,6 +198,7 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_DEV_ID("at91rm9200-gpio3", &pioDE_clk), CLKDEV_DEV_ID("at91rm9200-gpio4", &pioDE_clk), CLKDEV_DEV_ID("at91-pit", &mck), + CLKDEV_CON_DEV_ID("hck1", "atmel_lcdfb", &lcdc_clk), }; static struct clk_lookup usart_clocks_lookups[] = { diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index d2746da9d..bde3429ed 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,9 @@ void at91_add_device_sdram(u32 size) { + if (!size) + size = at91sam9g45_get_ddram_size(1); + arm_add_mem_device("ram0", AT91_CHIPSELECT_6, size); add_mem_device("sram0", AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE, IORESOURCE_MEM_WRITEABLE); @@ -44,7 +48,8 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) /* Enable VBus control for UHP ports */ for (i = 0; i < data->ports; i++) { if (gpio_is_valid(data->vbus_pin[i])) - at91_set_gpio_output(data->vbus_pin[i], 0); + at91_set_gpio_output(data->vbus_pin[i], + data->vbus_pin_active_low[i]); } add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91SAM9G45_OHCI_BASE, @@ -54,6 +59,28 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {} #endif +#if defined(CONFIG_USB_EHCI) +void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) +{ + int i; + + if (!data) + return; + + /* Enable VBus control for UHP ports */ + for (i = 0; i < data->ports; i++) { + if (gpio_is_valid(data->vbus_pin[i])) + at91_set_gpio_output(data->vbus_pin[i], + data->vbus_pin_active_low[i]); + } + + add_generic_device("atmel-ehci", DEVICE_ID_SINGLE, NULL, AT91SAM9G45_EHCI_BASE, + 1024 * 1024, IORESOURCE_MEM, data); +} +#else +void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {} +#endif + #if defined(CONFIG_DRIVER_NET_MACB) void at91_add_device_eth(int id, struct at91_ether_platform_data *data) { @@ -72,7 +99,7 @@ void at91_add_device_eth(int id, struct at91_ether_platform_data *data) at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */ at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */ - if (!data->is_rmii) { + if (data->phy_interface != PHY_INTERFACE_MODE_RMII) { at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */ at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */ at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */ @@ -374,3 +401,52 @@ void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) #else void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) {} #endif + +/* -------------------------------------------------------------------- + * LCD Controller + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_DRIVER_VIDEO_ATMEL) +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) +{ + BUG_ON(!data); + + at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ + + at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ + at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */ + at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */ + at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */ + at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */ + at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */ + at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */ + at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */ + at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */ + at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */ + at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */ + at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */ + at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */ + at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */ + at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ + at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ + + add_generic_device("atmel_lcdfb", DEVICE_ID_SINGLE, NULL, AT91SAM9G45_LCDC_BASE, SZ_4K, + IORESOURCE_MEM, data); +} +#else +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) {} +#endif + diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c index c177975f3..e5aabd11e 100644 --- a/arch/arm/mach-at91/at91sam9n12.c +++ b/arch/arm/mach-at91/at91sam9n12.c @@ -156,6 +156,7 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_DEV_ID("at91sam9x5-gpio2", &pioCD_clk), CLKDEV_DEV_ID("at91sam9x5-gpio3", &pioCD_clk), CLKDEV_DEV_ID("at91-pit", &mck), + CLKDEV_CON_DEV_ID("hck1", "atmel_hlcdfb", &lcdc_clk), }; static struct clk_lookup usart_clocks_lookups[] = { diff --git a/arch/arm/mach-at91/at91sam9n12_devices.c b/arch/arm/mach-at91/at91sam9n12_devices.c index 3f41f3e3b..aeac2aab7 100644 --- a/arch/arm/mach-at91/at91sam9n12_devices.c +++ b/arch/arm/mach-at91/at91sam9n12_devices.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,9 @@ void at91_add_device_sdram(u32 size) { + if (!size) + size = at91sam9n12_get_ddram_size(); + arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size); add_mem_device("sram0", AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE, IORESOURCE_MEM_WRITEABLE); @@ -46,7 +50,8 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) /* Enable VBus control for UHP ports */ for (i = 0; i < data->ports; i++) { if (gpio_is_valid(data->vbus_pin[i])) - at91_set_gpio_output(data->vbus_pin[i], 0); + at91_set_gpio_output(data->vbus_pin[i], + data->vbus_pin_active_low[i]); } add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91SAM9N12_OHCI_BASE, @@ -307,6 +312,56 @@ void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) {} #endif +/* -------------------------------------------------------------------- + * LCD Controller + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_DRIVER_VIDEO_ATMEL_HLCD) +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) +{ + BUG_ON(!data); + + at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDPWM */ + + at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDVSYNC */ + at91_set_A_periph(AT91_PIN_PC28, 0); /* LCDHSYNC */ + + at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDDISP */ + at91_set_A_periph(AT91_PIN_PC29, 0); /* LCDDEN */ + at91_set_A_periph(AT91_PIN_PC30, 0); /* LCDPCK */ + + at91_set_A_periph(AT91_PIN_PC0, 0); /* LCDD0 */ + at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDD1 */ + at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PC4, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD8 */ + at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD9 */ + at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PC12, 0); /* LCDD12 */ + at91_set_A_periph(AT91_PIN_PC13, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD15 */ + at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD16 */ + at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD17 */ + at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD18 */ + at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD19 */ + at91_set_A_periph(AT91_PIN_PC20, 0); /* LCDD20 */ + at91_set_A_periph(AT91_PIN_PC21, 0); /* LCDD21 */ + at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD22 */ + at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD23 */ + + add_generic_device("atmel_hlcdfb", DEVICE_ID_SINGLE, NULL, AT91SAM9N12_BASE_LCDC, SZ_4K, + IORESOURCE_MEM, data); +} +#else +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) {} +#endif + /* -------------------------------------------------------------------- * UART * -------------------------------------------------------------------- */ diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c index 5d43423eb..01eac1888 100644 --- a/arch/arm/mach-at91/at91sam9x5.c +++ b/arch/arm/mach-at91/at91sam9x5.c @@ -206,6 +206,7 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("macb_clk", "macb0", &macb0_clk), CLKDEV_CON_DEV_ID("macb_clk", "macb1", &macb1_clk), CLKDEV_CON_ID("ohci_clk", &uhphs_clk), + CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci0", &mmc0_clk), @@ -215,6 +216,7 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_DEV_ID("at91sam9x5-gpio2", &pioCD_clk), CLKDEV_DEV_ID("at91sam9x5-gpio3", &pioCD_clk), CLKDEV_DEV_ID("at91-pit", &mck), + CLKDEV_CON_DEV_ID("hck1", "atmel_hlcdfb", &lcdc_clk), }; static struct clk_lookup usart_clocks_lookups[] = { diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c index e92fa0de2..9f211e3bd 100644 --- a/arch/arm/mach-at91/at91sam9x5_devices.c +++ b/arch/arm/mach-at91/at91sam9x5_devices.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -25,6 +26,9 @@ void at91_add_device_sdram(u32 size) { + if (!size) + size = at91sam9x5_get_ddram_size(); + arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size); add_mem_device("sram0", AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE, IORESOURCE_MEM_WRITEABLE); @@ -45,7 +49,8 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) /* Enable VBus control for UHP ports */ for (i = 0; i < data->ports; i++) { if (gpio_is_valid(data->vbus_pin[i])) - at91_set_gpio_output(data->vbus_pin[i], 0); + at91_set_gpio_output(data->vbus_pin[i], + data->vbus_pin_active_low[i]); } add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91SAM9X5_OHCI_BASE, @@ -55,6 +60,28 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {} #endif +#if defined(CONFIG_USB_EHCI) +void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) +{ + int i; + + if (!data) + return; + + /* Enable VBus control for UHP ports */ + for (i = 0; i < data->ports; i++) { + if (gpio_is_valid(data->vbus_pin[i])) + at91_set_gpio_output(data->vbus_pin[i], + data->vbus_pin_active_low[i]); + } + + add_generic_device("atmel-ehci", DEVICE_ID_SINGLE, NULL, AT91SAM9X5_EHCI_BASE, + 1024 * 1024, IORESOURCE_MEM, data); +} +#else +void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {} +#endif + #if defined(CONFIG_DRIVER_NET_MACB) void at91_add_device_eth(int id, struct at91_ether_platform_data *data) { @@ -84,7 +111,7 @@ void at91_add_device_eth(int id, struct at91_ether_platform_data *data) at91_set_A_periph(AT91_PIN_PB5, 0); /* EMDIO */ at91_set_A_periph(AT91_PIN_PB6, 0); /* EMDC */ - if (!data->is_rmii) { + if (data->phy_interface != PHY_INTERFACE_MODE_RMII) { at91_set_A_periph(AT91_PIN_PB16, 0); /* ECRS */ at91_set_A_periph(AT91_PIN_PB17, 0); /* ECOL */ at91_set_A_periph(AT91_PIN_PB13, 0); /* ERX2 */ @@ -97,7 +124,7 @@ void at91_add_device_eth(int id, struct at91_ether_platform_data *data) break; case 1: start = AT91SAM9X5_BASE_EMAC1; - if (!data->is_rmii) + if (data->phy_interface != PHY_INTERFACE_MODE_RMII) pr_warn("AT91: Only RMII available on interface macb%d.\n", id); /* Pins used for RMII */ @@ -363,6 +390,61 @@ void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) {} #endif +/* -------------------------------------------------------------------- + * LCD Controller + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_DRIVER_VIDEO_ATMEL_HLCD) +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) +{ + BUG_ON(!data); + + if (cpu_is_at91sam9g25() || cpu_is_at91sam9x25()) { + pr_warn("AT91: no lcd on at91sam9g25 or at91sam9x25\n"); + return; + } + + at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDPWM */ + + at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDVSYNC */ + at91_set_A_periph(AT91_PIN_PC28, 0); /* LCDHSYNC */ + + at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDDISP */ + at91_set_A_periph(AT91_PIN_PC29, 0); /* LCDDEN */ + at91_set_A_periph(AT91_PIN_PC30, 0); /* LCDPCK */ + + at91_set_A_periph(AT91_PIN_PC0, 0); /* LCDD0 */ + at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDD1 */ + at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PC4, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD8 */ + at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD9 */ + at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PC12, 0); /* LCDD12 */ + at91_set_A_periph(AT91_PIN_PC13, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD15 */ + at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD16 */ + at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD17 */ + at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD18 */ + at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD19 */ + at91_set_A_periph(AT91_PIN_PC20, 0); /* LCDD20 */ + at91_set_A_periph(AT91_PIN_PC21, 0); /* LCDD21 */ + at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD22 */ + at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD23 */ + + add_generic_device("atmel_hlcdfb", DEVICE_ID_SINGLE, NULL, AT91SAM9X5_BASE_LCDC, SZ_4K, + IORESOURCE_MEM, data); +} +#else +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) {} +#endif + /* -------------------------------------------------------------------- * UART * -------------------------------------------------------------------- */ diff --git a/arch/arm/mach-at91/boot_test_cmd.c b/arch/arm/mach-at91/boot_test_cmd.c new file mode 100644 index 000000000..aa5c02046 --- /dev/null +++ b/arch/arm/mach-at91/boot_test_cmd.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2012 Jean-Christophe PLAGNIOL-VILLARD + * + * Under GPLv2 only + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static int do_at91_boot_test(int argc, char *argv[]) +{ + int opt; + u32 *buf32; + void *buf; + void (*jump)(void) = NULL; + int fd; + int ret = 1; + char *sram = "/dev/sram0"; + u32 read_size, write_size; + u32 tmp = 0; + + while ((opt = getopt(argc, argv, "j:s:")) > 0) { + switch (opt) { + case 'j': + jump = (void*)simple_strtoul(optarg, NULL, 0); + break; + case 's': + sram = optarg; + break; + default: + return COMMAND_ERROR_USAGE; + } + } + + if (argc < optind + 1) + return COMMAND_ERROR_USAGE; + + buf32 = buf = read_file(argv[optind], &read_size); + if (!buf) + return -EINVAL; + + write_size = buf32[5]; + + printf("size of the size %d\n", read_size); + printf("size to load in sram %d\n", write_size); + + if (write_size > read_size) { + printf("file smaller than requested sram loading size (%d < %d)\n", write_size, read_size); + goto err; + } + + fd = open(sram, O_WRONLY); + if (fd < 0) { + printf("could not open %s: %s\n", sram, errno_str()); + ret = fd; + goto err; + } + + while (write_size) { + tmp = write(fd, buf, write_size); + if (tmp < 0) { + perror("write"); + goto err_open; + } + buf += tmp; + write_size -= tmp; + } + + shutdown_barebox(); + + jump(); + +err_open: + close(fd); +err: + free(buf); + return ret; +} + +BAREBOX_CMD_HELP_START(at91_boot_test) +BAREBOX_CMD_HELP_USAGE("at91_boot_test [-j ] [-s ] file\n") +BAREBOX_CMD_HELP_SHORT("upload the binary to sram and jump as will do the romcode\n") +BAREBOX_CMD_HELP_END + +BAREBOX_CMD_START(at91_boot_test) + .cmd = do_at91_boot_test, + .usage = "upload the binary to sram and jump as will do the romcode", + BAREBOX_CMD_HELP(cmd_at91_boot_test_help) +BAREBOX_CMD_END diff --git a/arch/arm/mach-at91/bootstrap.c b/arch/arm/mach-at91/bootstrap.c new file mode 100644 index 000000000..4149304c9 --- /dev/null +++ b/arch/arm/mach-at91/bootstrap.c @@ -0,0 +1,260 @@ +/* + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + * + * Under GPLv2 + */ + +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_MCI_ATMEL) +#define is_mmc() 1 +#else +#define is_mmc() 0 +#endif + +#ifdef CONFIG_NAND_ATMEL +#define is_nand() 1 +#else +#define is_nand() 0 +#endif + +#ifdef CONFIG_MTD_M25P80 +#define is_m25p80() 1 +#else +#define is_m25p80() 0 +#endif + +#ifdef CONFIG_MTD_DATAFLASH +#define is_dataflash() 1 +#else +#define is_dataflash() 0 +#endif + +#if defined(CONFIG_MENU) && !defined(CONFIG_NONE) +#define is_menu() 1 +#else +#define is_menu() 0 +#endif + +static char* is_barebox_to_str(bool is_barebox) +{ + return is_barebox ? "barebox" : "unknown"; +} + +static void at91bootstrap_boot_m25p80(bool is_barebox) +{ + char *name = is_barebox_to_str(is_barebox); + int (*func)(void) = NULL; + + func = bootstrap_board_read_m25p80(); + printf("Boot %s from m25p80\n", name); + bootstrap_boot(func, is_barebox); + bootstrap_err("... failed\n"); + free(func); +} + +static void at91bootstrap_boot_dataflash(bool is_barebox) +{ + char *name = is_barebox_to_str(is_barebox); + int (*func)(void) = NULL; + + printf("Boot %s from dataflash\n", name); + func = bootstrap_board_read_dataflash(); + bootstrap_boot(func, is_barebox); + bootstrap_err("... failed\n"); + free(func); +} + +static void at91bootstrap_boot_nand(bool is_barebox) +{ + char *name = is_barebox_to_str(is_barebox); + int (*func)(void) = NULL; + + printf("Boot %s from nand\n", name); + func = bootstrap_read_devfs("nand0", true, SZ_128K, SZ_256K, SZ_1M); + bootstrap_boot(func, is_barebox); + bootstrap_err("... failed\n"); + free(func); +} + +static void at91bootstrap_boot_mmc(void) +{ + int (*func)(void) = NULL; + + printf("Boot from mmc\n"); + func = bootstrap_read_disk("disk0.0", NULL); + bootstrap_boot(func, false); + bootstrap_err("... failed\n"); + free(func); +} + +static void boot_nand_barebox_action(struct menu *m, struct menu_entry *me) +{ + at91bootstrap_boot_nand(true); + + getc(); +} + +static void boot_nand_action(struct menu *m, struct menu_entry *me) +{ + at91bootstrap_boot_nand(false); + + getc(); +} + +static void boot_m25p80_barebox_action(struct menu *m, struct menu_entry *me) +{ + at91bootstrap_boot_nand(true); + + getc(); +} + +static void boot_m25p80_action(struct menu *m, struct menu_entry *me) +{ + at91bootstrap_boot_nand(false); + + getc(); +} + +static void boot_dataflash_barebox_action(struct menu *m, struct menu_entry *me) +{ + at91bootstrap_boot_dataflash(true); + + getc(); +} + +static void boot_dataflash_action(struct menu *m, struct menu_entry *me) +{ + at91bootstrap_boot_dataflash(false); + + getc(); +} + +static void boot_mmc_disk_action(struct menu *m, struct menu_entry *me) +{ + at91bootstrap_boot_mmc(); + + getc(); +} + +static void boot_reset_action(struct menu *m, struct menu_entry *me) +{ + reset_cpu(0); +} + +void at91_bootstrap_menu(void) +{ + struct menu *m; + struct menu_entry *me; + + m = menu_alloc(); + m->display = m->name = "boot"; + + menu_add(m); + + if (is_mmc()) { + me = menu_entry_alloc(); + me->action = boot_mmc_disk_action; + me->type = MENU_ENTRY_NORMAL; + me->display = "mmc"; + menu_add_entry(m, me); + } + + if (is_m25p80()) { + me = menu_entry_alloc(); + me->action = boot_m25p80_barebox_action; + me->type = MENU_ENTRY_NORMAL; + me->display = "m25p80 (barebox)"; + menu_add_entry(m, me); + + me = menu_entry_alloc(); + me->action = boot_m25p80_action; + me->type = MENU_ENTRY_NORMAL; + me->display = "m25p80"; + menu_add_entry(m, me); + } + + if (is_dataflash()) { + me = menu_entry_alloc(); + me->action = boot_dataflash_barebox_action; + me->type = MENU_ENTRY_NORMAL; + me->display = "dataflash (barebox)"; + menu_add_entry(m, me); + + me = menu_entry_alloc(); + me->action = boot_dataflash_action; + me->type = MENU_ENTRY_NORMAL; + me->display = "dataflash"; + menu_add_entry(m, me); + } + + if (is_nand()) { + me = menu_entry_alloc(); + me->action = boot_nand_barebox_action; + me->type = MENU_ENTRY_NORMAL; + me->display = "nand (barebox)"; + menu_add_entry(m, me); + + me = menu_entry_alloc(); + me->action = boot_nand_action; + me->type = MENU_ENTRY_NORMAL; + me->display = "nand"; + menu_add_entry(m, me); + } + + me = menu_entry_alloc(); + me->action = boot_reset_action; + me->type = MENU_ENTRY_NORMAL; + me->display = "reset"; + menu_add_entry(m, me); + + menu_show(m); +} + +static void boot_seq(bool is_barebox) +{ + if (is_m25p80()) + at91bootstrap_boot_m25p80(is_barebox); + + if (is_dataflash()) + at91bootstrap_boot_dataflash(is_barebox); + + if (is_nand()) + at91bootstrap_boot_nand(is_barebox); +} + +static int at91_bootstrap(void) +{ + if (is_menu()) { + printf("press 'm' to start the menu\n"); + if (tstc() && getc() == 'm') + at91_bootstrap_menu(); + } + + if (is_mmc()) + at91bootstrap_boot_mmc(); + + /* First only bootstrap_boot a barebox */ + boot_seq(true); + /* Second bootstrap_boot any */ + boot_seq(false); + + bootstrap_err("bootstrap_booting failed\n"); + while (1); + + return 0; +} + +static int at91_set_bootstrap(void) +{ + barebox_main = at91_bootstrap; + + return 0; +} +late_initcall(at91_set_bootstrap); diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index b231ec078..2dde6325a 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -11,6 +11,8 @@ */ #include +#include +#include #include #include #include @@ -42,7 +44,10 @@ */ #define cpu_has_utmi() ( cpu_is_at91sam9rl() \ || cpu_is_at91sam9g45() \ - || cpu_is_at91sam9x5()) + || cpu_is_at91sam9x5() \ + || cpu_is_sama5d3()) + +#define cpu_has_1056M_plla() (cpu_is_sama5d3()) #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \ || cpu_is_at91sam9g45() \ @@ -63,7 +68,8 @@ || cpu_is_at91sam9n12())) #define cpu_has_upll() (cpu_is_at91sam9g45() \ - || cpu_is_at91sam9x5()) + || cpu_is_at91sam9x5() \ + || cpu_is_sama5d3()) /* USB host HS & FS */ #define cpu_has_uhp() (!cpu_is_at91sam9rl()) @@ -71,18 +77,22 @@ /* USB device FS only */ #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \ || cpu_is_at91sam9g45() \ - || cpu_is_at91sam9x5())) + || cpu_is_at91sam9x5() \ + || cpu_is_sama5d3())) #define cpu_has_plladiv2() (cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ - || cpu_is_at91sam9n12()) + || cpu_is_at91sam9n12() \ + || cpu_is_sama5d3()) #define cpu_has_mdiv3() (cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ - || cpu_is_at91sam9n12()) + || cpu_is_at91sam9n12() \ + || cpu_is_sama5d3()) #define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \ - || cpu_is_at91sam9n12()) + || cpu_is_at91sam9n12() \ + || cpu_is_sama5d3()) static LIST_HEAD(clocks); @@ -204,10 +214,26 @@ struct clk mck = { static void pmc_periph_mode(struct clk *clk, int is_on) { - if (is_on) - at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask); - else - at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask); + u32 regval = 0; + + /* + * With sama5d3 chips, you have more than 32 peripherals so only one + * register is not enough to manage their clocks. A peripheral + * control register has been introduced to solve this issue. + */ + if (cpu_is_sama5d3()) { + regval |= AT91_PMC_PCR_CMD; /* write command */ + regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */ + regval |= AT91_PMC_PCR_DIV(clk->div); + if (is_on) + regval |= AT91_PMC_PCR_EN; /* enable clock */ + at91_pmc_write(AT91_PMC_PCR, regval); + } else { + if (is_on) + at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask); + else + at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask); + } } static struct clk *at91_css_to_clk(unsigned long css) @@ -429,6 +455,8 @@ int clk_register(struct clk *clk) if (clk_is_peripheral(clk)) { if (!clk->parent) clk->parent = &mck; + if (cpu_is_sama5d3()) + clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz, 1 << clk->div); clk->mode = pmc_periph_mode; } else if (clk_is_sys(clk)) { @@ -454,7 +482,10 @@ static u32 at91_pll_rate(struct clk *pll, u32 freq, u32 reg) unsigned mul, div; div = reg & 0xff; - mul = (reg >> 16) & 0x7ff; + if (cpu_is_sama5d3()) + mul = (reg >> 18) & 0x7ff; + else + mul = (reg >> 16) & 0x7ff; if (div && mul) { freq /= div; freq *= mul + 1; @@ -609,12 +640,18 @@ int at91_clock_init(unsigned long main_clock) /* report if PLLA is more than mildly overclocked */ plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR)); - if (cpu_has_300M_plla()) { + if (cpu_has_1056M_plla()) { + if (plla.rate_hz > 1056000000) + pll_overclock = 1; + } else if (cpu_has_300M_plla()) { if (plla.rate_hz > 300000000) pll_overclock = 1; } else if (cpu_has_800M_plla()) { if (plla.rate_hz > 800000000) pll_overclock = 1; + } else if (cpu_has_300M_plla()) { + if (plla.rate_hz > 300000000) + pll_overclock = 1; } else if (cpu_has_240M_plla()) { if (plla.rate_hz > 240000000) pll_overclock = 1; @@ -734,6 +771,7 @@ postconsole_initcall(at91_clock_display); static int at91_clock_reset(void) { unsigned long pcdr = 0; + unsigned long pcdr1 = 0; unsigned long scdr = 0; struct clk *clk; @@ -741,8 +779,17 @@ static int at91_clock_reset(void) if (clk->users > 0) continue; - if (clk->mode == pmc_periph_mode) - pcdr |= clk->pmc_mask; + if (clk->mode == pmc_periph_mode) { + if (cpu_is_sama5d3()) { + u32 pmc_mask = 1 << (clk->pid % 32); + + if (clk->pid > 31) + pcdr1 |= pmc_mask; + else + pcdr |= pmc_mask; + } else + pcdr |= clk->pmc_mask; + } if (clk->mode == pmc_sys_mode) scdr |= clk->pmc_mask; @@ -751,8 +798,91 @@ static int at91_clock_reset(void) } at91_pmc_write(AT91_PMC_PCDR, pcdr); + if (cpu_is_sama5d3()) + at91_pmc_write(AT91_PMC_PCDR1, pcdr1); at91_pmc_write(AT91_PMC_SCDR, scdr); return 0; } late_initcall(at91_clock_reset); + +#ifdef CONFIG_CMD_AT91CLK +static int do_at91clk(int argc, char *argv[]) +{ + u32 scsr, pcsr, pcsr1 = 0, uckr = 0, sr; + struct clk *clk; + + scsr = at91_pmc_read(AT91_PMC_SCSR); + pcsr = at91_pmc_read(AT91_PMC_PCSR); + if (cpu_is_sama5d3()) + pcsr1 = at91_pmc_read(AT91_PMC_PCSR1); + sr = at91_pmc_read(AT91_PMC_SR); + printf("SCSR = %8x\n", scsr); + printf("PCSR = %8x\n", pcsr); + if (cpu_is_sama5d3()) + printf("PCSR1 = %8x\n", pcsr1); + printf("MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR)); + printf("MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR)); + printf("PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR)); + if (cpu_has_pllb()) + printf("PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR)); + if (cpu_has_utmi()) { + uckr = at91_pmc_read(AT91_CKGR_UCKR); + printf("UCKR = %8x\n", uckr); + } + printf("MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR)); + if (cpu_has_upll()) + printf("USB = %8x\n", at91_pmc_read(AT91_PMC_USB)); + printf("SR = %8x\n", sr); + + printf("\n"); + + list_for_each_entry(clk, &clocks, node) { + char *state; + char *mode = ""; + + if (clk->mode == pmc_sys_mode) { + state = (scsr & clk->pmc_mask) ? "on" : "off"; + mode = "sys"; + } else if (clk->mode == pmc_periph_mode) { + if (cpu_is_sama5d3()) { + u32 pmc_mask = 1 << (clk->pid % 32); + + if (clk->pid > 31) + state = (pcsr1 & pmc_mask) ? "on" : "off"; + else + state = (pcsr & pmc_mask) ? "on" : "off"; + } else { + state = (pcsr & clk->pmc_mask) ? "on" : "off"; + } + mode = "periph"; + } else if (clk->mode == pmc_uckr_mode) { + state = (uckr & clk->pmc_mask) ? "on" : "off"; + mode = "uckr"; + } else if (clk->pmc_mask) { + state = (sr & clk->pmc_mask) ? "on" : "off"; + } else if (clk == &clk32k || clk == &main_clk) { + state = "on"; + } else { + state = ""; + } + + printf("%-10s %-7s users=%2d %-3s %10lu Hz %s\n", + clk->name, mode, clk->users, state, clk_get_rate(clk), + clk->parent ? clk->parent->name : ""); + } + return 0; +} + +BAREBOX_CMD_HELP_START(at91clk) +BAREBOX_CMD_HELP_USAGE("at91clk\n") +BAREBOX_CMD_HELP_SHORT("dump current clock configuration\n"); +BAREBOX_CMD_HELP_END + +BAREBOX_CMD_START(at91clk) + .cmd = do_at91clk, + .usage = "dump current clock configuration", + BAREBOX_CMD_HELP(cmd_at91clk_help) + BAREBOX_CMD_COMPLETE(empty_complete) +BAREBOX_CMD_END +#endif diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h index cacc0b546..8af8d963c 100644 --- a/arch/arm/mach-at91/clock.h +++ b/arch/arm/mach-at91/clock.h @@ -20,7 +20,9 @@ struct clk { const char *name; /* unique clock name */ struct clk_lookup cl; unsigned long rate_hz; + unsigned div; /* parent clock divider */ struct clk *parent; + unsigned pid; /* peripheral ID */ u32 pmc_mask; void (*mode)(struct clk *, int); unsigned id:3; /* PCK0..4, or 32k/main/a/b */ diff --git a/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h b/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h new file mode 100644 index 000000000..8c53ce799 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD + * + * Under GPLv2 + */ + +#ifndef __AT91_LOWLEVEL_INIT_H__ +#define __AT91_LOWLEVEL_INIT_H__ + +struct at91sam926x_lowlevel_cfg { + u32 wdt_mr; + u32 ebi_pio_pdr; + u32 ebi_pio_ppudr; + u32 ebi_csa; + u32 smc_cs; + u32 smc_mode; + u32 smc_cycle; + u32 smc_pulse; + u32 smc_setup; + u32 pmc_mor; + u32 pmc_pllar; + u32 pmc_mckr1; + u32 pmc_mckr2; + u32 sdrc_cr; + u32 sdrc_tr1; + u32 sdrc_mdr; + u32 sdrc_tr2; + u32 rstc_rmr; +}; + +void at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg); +void at91sam926x_lowlevel_init(void *pio, bool is_pio_asr, u32 matrix_csa); + +#endif /* __AT91_LOWLEVEL_INIT_H__ */ diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 6fcbf4072..61078717c 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -163,13 +163,19 @@ #define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ #define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ -#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ +#define AT91_PMC_VER 0xfc /* PMC Module Version [AT91CAP9 only] */ -#define AT91_PMC_PCR (AT91_PMC + 0x10c) /* Peripheral Control Register [some SAM9] */ +#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9] */ #define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */ #define AT91_PMC_PCR_CMD (0x1 << 12) /* Command */ -#define AT91_PMC_PCR_DIV (0x3 << 16) /* Divisor Value */ -#define AT91_PMC_PCRDIV(n) (((n) << 16) & AT91_PMC_PCR_DIV) +#define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor value */ +#define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */ +#define AT91_PMC_PCR_DIV2 0x1 /* Peripheral clock is MCK/2 */ +#define AT91_PMC_PCR_DIV4 0x2 /* Peripheral clock is MCK/4 */ +#define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */ #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ +#define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 */ +#define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Disable Register 1 */ +#define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Status Register 1 */ #endif diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h index d34e4ed89..fc44a6109 100644 --- a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h +++ b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h @@ -157,4 +157,34 @@ #define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */ #define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */ +#ifndef __ASSEMBLY__ +#include +static inline u32 at91rm9200_get_sdram_size(void) +{ + u32 cr, mr; + u32 size; + + cr = at91_sys_read(AT91_SDRAMC_CR); + mr = at91_sys_read(AT91_SDRAMC_MR); + + /* Formula: + * size = bank << (col + row + 1); + * if (bandwidth == 32 bits) + * size <<= 1; + */ + size = 1; + /* COL */ + size += (cr & AT91_SDRAMC_NC) + 8; + /* ROW */ + size += ((cr & AT91_SDRAMC_NR) >> 2) + 11; + /* BANK */ + size = ((cr & AT91_SDRAMC_NB) ? 4 : 2) << size; + /* bandwidth */ + if (!(mr & AT91_SDRAMC_DBW)) + size <<= 1; + + return size; +} +#endif + #endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h index 070f73061..88796a6a2 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h @@ -50,6 +50,10 @@ #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */ #define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */ #define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */ +#define AT91_DDRSDRC_NB (1 << 20) /* Number of +Banks [not SAM9G45] */ +#define AT91_SDRAMC_NB_4 (0 << 20) +#define AT91_SDRAMC_NB_8 (1 << 20) #define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */ #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ @@ -131,4 +135,126 @@ #define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */ #define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */ +#ifndef __ASSEMBLY__ +#include + +static inline u32 at91_get_ddram_size(void * __iomem base, bool is_nb) +{ + u32 cr; + u32 mdr; + u32 size; + bool is_sdram; + + cr = __raw_readl(base + AT91_DDRSDRC_CR); + mdr = __raw_readl(base + AT91_DDRSDRC_MDR); + + is_sdram = (mdr & AT91_DDRSDRC_MD) <= AT91_DDRSDRC_MD_LOW_POWER_SDR; + + /* Formula: + * size = bank << (col + row + 1); + * if (bandwidth == 32 bits) + * size <<= 1; + */ + size = 1; + /* COL */ + size += (cr & AT91_DDRSDRC_NC) + 8; + if (!is_sdram) + size ++; + /* ROW */ + size += ((cr & AT91_DDRSDRC_NR) >> 2) + 11; + /* BANK */ + if (is_nb) + size = ((cr & AT91_DDRSDRC_NB) ? 8 : 4) << size; + else + size = 4 << size; + + /* bandwidth */ + if (!(mdr & AT91_DDRSDRC_DBW)) + size <<= 1; + + return size; +} + +#ifdef CONFIG_SOC_AT91SAM9G45 +static inline u32 at91sam9g45_get_ddram_size(int bank) +{ + switch (bank) { + case 0: + return at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC0), false); + case 1: + return at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC1), false); + default: + return 0; + } +} +#else +static inline u32 at91sam9g45_get_ddram_size(int bank) +{ + return 0; +} +#endif + +#ifdef CONFIG_SOC_AT91SAM9X5 +static inline u32 at91sam9x5_get_ddram_size(void) +{ + return at91_get_ddram_size(IOMEM(AT91SAM9X5_BASE_DDRSDRC0), true); +} +#else +static inline u32 at91sam9x5_get_ddram_size(void) +{ + return 0; +} +#endif + +#ifdef CONFIG_SOC_AT91SAM9N12 +static inline u32 at91sam9n12_get_ddram_size(void) +{ + return at91_get_ddram_size(IOMEM(AT91SAM9N12_BASE_DDRSDRC0), true); +} +#else +static inline u32 at91sam9n12_get_ddram_size(void) +{ + return 0; +} +#endif + +#ifdef CONFIG_SOC_SAMA5 +static inline u32 at91sama5_get_ddram_size(void) +{ + u32 cr; + u32 mdr; + u32 size; + void * __iomem base = IOMEM(SAMA5D3_BASE_MPDDRC); + + cr = __raw_readl(base + AT91_DDRSDRC_CR); + mdr = __raw_readl(base + AT91_DDRSDRC_MDR); + + /* Formula: + * size = bank << (col + row + 1); + * if (bandwidth == 32 bits) + * size <<= 1; + */ + size = 1; + /* COL */ + size += (cr & AT91_DDRSDRC_NC) + 9; + /* ROW */ + size += ((cr & AT91_DDRSDRC_NR) >> 2) + 11; + /* BANK */ + size = ((cr & AT91_DDRSDRC_NB) ? 8 : 4) << size; + + /* bandwidth */ + if (!(mdr & AT91_DDRSDRC_DBW)) + size <<= 1; + + return size; +} +#else +static inline u32 at91sama5_get_ddram_size(void) +{ + return 0; +} +#endif + +#endif + #endif diff --git a/arch/arm/mach-at91/include/mach/atmel_hlcdc.h b/arch/arm/mach-at91/include/mach/atmel_hlcdc.h new file mode 100644 index 000000000..71ccb9626 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/atmel_hlcdc.h @@ -0,0 +1,760 @@ +/* + * Header file for AT91 High end LCD Controller + * + * Data structure and register user interface + * + * Copyright (C) 2010 Atmel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PUROFFSETE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __MACH_ATMEL_HLCD_H__ +#define __MACH_ATMEL_HLCD_H__ + +/* Lcdc hardware registers */ +#define ATMEL_LCDC_LCDCFG0 0x0000 +#define LCDC_LCDCFG0_CLKPOL (0x1 << 0) +#define LCDC_LCDCFG0_CLKSEL (0x1 << 2) +#define LCDC_LCDCFG0_CLKPWMSEL (0x1 << 3) +#define LCDC_LCDCFG0_CGDISBASE (0x1 << 8) +#define LCDC_LCDCFG0_CGDISOVR1 (0x1 << 9) +#define LCDC_LCDCFG0_CGDISOVR2 (0x1 << 10) +#define LCDC_LCDCFG0_CGDISHEO (0x1 << 11) +#define LCDC_LCDCFG0_CGDISHCR (0x1 << 12) +#define LCDC_LCDCFG0_CGDISPP (0x1 << 13) +#define LCDC_LCDCFG0_CLKDIV_OFFSET 16 +#define LCDC_LCDCFG0_CLKDIV (0xff << LCDC_LCDCFG0_CLKDIV_OFFSET) + +#define ATMEL_LCDC_LCDCFG1 0x0004 +#define LCDC_LCDCFG1_HSPW_OFFSET 0 +#define LCDC_LCDCFG1_HSPW (0x3f << LCDC_LCDCFG1_HSPW_OFFSET) +#define LCDC_LCDCFG1_VSPW_OFFSET 16 +#define LCDC_LCDCFG1_VSPW (0x3f << LCDC_LCDCFG1_VSPW_OFFSET) + +#define ATMEL_LCDC_LCDCFG2 0x0008 +#define LCDC_LCDCFG2_VFPW_OFFSET 0 +#define LCDC_LCDCFG2_VFPW (0x3f << LCDC_LCDCFG2_VFPW_OFFSET) +#define LCDC_LCDCFG2_VBPW_OFFSET 16 +#define LCDC_LCDCFG2_VBPW (0x3f << LCDC_LCDCFG2_VBPW_OFFSET) + +#define ATMEL_LCDC_LCDCFG3 0x000C +#define LCDC_LCDCFG3_HFPW_OFFSET 0 +#define LCDC_LCDCFG3_HFPW (0xff << LCDC_LCDCFG3_HFPW_OFFSET) +#define LCDC2_LCDCFG3_HFPW (0x1ff << LCDC_LCDCFG3_HFPW_OFFSET) +#define LCDC_LCDCFG3_HBPW_OFFSET 16 +#define LCDC_LCDCFG3_HBPW (0xff << LCDC_LCDCFG3_HBPW_OFFSET) +#define LCDC2_LCDCFG3_HBPW (0x1ff << LCDC_LCDCFG3_HBPW_OFFSET) + +#define ATMEL_LCDC_LCDCFG4 0x0010 +#define LCDC_LCDCFG4_PPL_OFFSET 0 +#define LCDC_LCDCFG4_PPL (0x7ff << LCDC_LCDCFG4_PPL_OFFSET) +#define LCDC_LCDCFG4_RPF_OFFSET 16 +#define LCDC_LCDCFG4_RPF (0x7ff << LCDC_LCDCFG4_RPF_OFFSET) + +#define ATMEL_LCDC_LCDCFG5 0x0014 +#define LCDC_LCDCFG5_HSPOL (0x1 << 0) +#define LCDC_LCDCFG5_VSPOL (0x1 << 1) +#define LCDC_LCDCFG5_VSPDLYS (0x1 << 2) +#define LCDC_LCDCFG5_VSPDLYE (0x1 << 3) +#define LCDC_LCDCFG5_DISPPOL (0x1 << 4) +#define LCDC_LCDCFG5_SERIAL (0x1 << 5) +#define LCDC_LCDCFG5_DITHER (0x1 << 6) +#define LCDC_LCDCFG5_DISPDLY (0x1 << 7) +#define LCDC_LCDCFG5_MODE_OFFSET 8 +#define LCDC_LCDCFG5_MODE (0x3 << LCDC_LCDCFG5_MODE_OFFSET) +#define LCDC_LCDCFG5_MODE_OUTPUT_12BPP (0x0 << 8) +#define LCDC_LCDCFG5_MODE_OUTPUT_16BPP (0x1 << 8) +#define LCDC_LCDCFG5_MODE_OUTPUT_18BPP (0x2 << 8) +#define LCDC_LCDCFG5_MODE_OUTPUT_24BPP (0x3 << 8) +#define LCDC_LCDCFG5_PP (0x1 << 10) +#define LCDC_LCDCFG5_VSPSU (0x1 << 12) +#define LCDC_LCDCFG5_VSPHO (0x1 << 13) +#define LCDC_LCDCFG5_GUARDTIME_OFFSET 16 +#define LCDC_LCDCFG5_GUARDTIME (0x1f << LCDC_LCDCFG5_GUARDTIME_OFFSET) + +#define ATMEL_LCDC_LCDCFG6 0x0018 +#define LCDC_LCDCFG6_PWMPS_OFFSET 0 +#define LCDC_LCDCFG6_PWMPS (0x7 << LCDC_LCDCFG6_PWMPS_OFFSET) +#define LCDC_LCDCFG6_PWMPOL (0x1 << 4) +#define LCDC_LCDCFG6_PWMCVAL_OFFSET 8 +#define LCDC_LCDCFG6_PWMCVAL (0xff << LCDC_LCDCFG6_PWMCVAL_OFFSET) + +#define ATMEL_LCDC_LCDEN 0x0020 +#define LCDC_LCDEN_CLKEN (0x1 << 0) +#define LCDC_LCDEN_SYNCEN (0x1 << 1) +#define LCDC_LCDEN_DISPEN (0x1 << 2) +#define LCDC_LCDEN_PWMEN (0x1 << 3) + +#define ATMEL_LCDC_LCDDIS 0x0024 +#define LCDC_LCDDIS_CLKDIS (0x1 << 0) +#define LCDC_LCDDIS_SYNCDIS (0x1 << 1) +#define LCDC_LCDDIS_DISPDIS (0x1 << 2) +#define LCDC_LCDDIS_PWMDIS (0x1 << 3) +#define LCDC_LCDDIS_CLKRST (0x1 << 8) +#define LCDC_LCDDIS_SYNCRST (0x1 << 9) +#define LCDC_LCDDIS_DISPRST (0x1 << 10) +#define LCDC_LCDDIS_PWMRST (0x1 << 11) + +#define ATMEL_LCDC_LCDSR 0x0028 +#define LCDC_LCDSR_CLKSTS (0x1 << 0) +#define LCDC_LCDSR_LCDSTS (0x1 << 1) +#define LCDC_LCDSR_DISPSTS (0x1 << 2) +#define LCDC_LCDSR_PWMSTS (0x1 << 3) +#define LCDC_LCDSR_SIPSTS (0x1 << 4) + +#define ATMEL_LCDC_LCDIER 0x002C +#define LCDC_LCDIER_SOFIE (0x1 << 0) +#define LCDC_LCDIER_DISIE (0x1 << 1) +#define LCDC_LCDIER_DISPIE (0x1 << 2) +#define LCDC_LCDIER_FIFOERRIE (0x1 << 4) +#define LCDC_LCDIER_BASEIE (0x1 << 8) +#define LCDC_LCDIER_OVR1IE (0x1 << 9) +#define LCDC_LCDIER_OVR2IE (0x1 << 10) +#define LCDC_LCDIER_HEOIE (0x1 << 11) +#define LCDC_LCDIER_HCRIE (0x1 << 12) +#define LCDC_LCDIER_PPIE (0x1 << 13) + +#define ATMEL_LCDC_LCDIDR 0x0030 +#define LCDC_LCDIDR_SOFID (0x1 << 0) +#define LCDC_LCDIDR_DISID (0x1 << 1) +#define LCDC_LCDIDR_DISPID (0x1 << 2) +#define LCDC_LCDIDR_FIFOERRID (0x1 << 4) +#define LCDC_LCDIDR_BASEID (0x1 << 8) +#define LCDC_LCDIDR_OVR1ID (0x1 << 9) +#define LCDC_LCDIDR_OVR2ID (0x1 << 10) +#define LCDC_LCDIDR_HEOID (0x1 << 11) +#define LCDC_LCDIDR_HCRID (0x1 << 12) +#define LCDC_LCDIDR_PPID (0x1 << 13) + +#define ATMEL_LCDC_LCDIMR 0x0034 +#define LCDC_LCDIMR_SOFIM (0x1 << 0) +#define LCDC_LCDIMR_DISIM (0x1 << 1) +#define LCDC_LCDIMR_DISPIM (0x1 << 2) +#define LCDC_LCDIMR_FIFOERRIM (0x1 << 4) +#define LCDC_LCDIMR_BASEIM (0x1 << 8) +#define LCDC_LCDIMR_OVR1IM (0x1 << 9) +#define LCDC_LCDIMR_OVR2IM (0x1 << 10) +#define LCDC_LCDIMR_HEOIM (0x1 << 11) +#define LCDC_LCDIMR_HCRIM (0x1 << 12) +#define LCDC_LCDIMR_PPIM (0x1 << 13) + +#define ATMEL_LCDC_LCDISR 0x0038 +#define LCDC_LCDISR_SOF (0x1 << 0) +#define LCDC_LCDISR_DIS (0x1 << 1) +#define LCDC_LCDISR_DISP (0x1 << 2) +#define LCDC_LCDISR_FIFOERR (0x1 << 4) +#define LCDC_LCDISR_BASE (0x1 << 8) +#define LCDC_LCDISR_OVR1 (0x1 << 9) +#define LCDC_LCDISR_OVR2 (0x1 << 10) +#define LCDC_LCDISR_HEO (0x1 << 11) +#define LCDC_LCDISR_HCR (0x1 << 12) +#define LCDC_LCDISR_PP (0x1 << 13) + +#define ATMEL_LCDC_BASECHER 0x0040 +#define LCDC_BASECHER_CHEN (0x1 << 0) +#define LCDC_BASECHER_UPDATEEN (0x1 << 1) +#define LCDC_BASECHER_A2QEN (0x1 << 2) + +#define ATMEL_LCDC_BASECHDR 0x0044 +#define LCDC_BASECHDR_CHDIS (0x1 << 0) +#define LCDC_BASECHDR_CHRST (0x1 << 8) + +#define ATMEL_LCDC_BASECHSR 0x0048 +#define LCDC_BASECHSR_CHSR (0x1 << 0) +#define LCDC_BASECHSR_UPDATESR (0x1 << 1) +#define LCDC_BASECHSR_A2QSR (0x1 << 2) + +#define ATMEL_LCDC_BASEIER 0x004C +#define LCDC_BASEIER_DMA (0x1 << 2) +#define LCDC_BASEIER_DSCR (0x1 << 3) +#define LCDC_BASEIER_ADD (0x1 << 4) +#define LCDC_BASEIER_DONE (0x1 << 5) +#define LCDC_BASEIER_OVR (0x1 << 6) + +#define ATMEL_LCDC_BASEIDR 0x0050 +#define LCDC_BASEIDR_DMA (0x1 << 2) +#define LCDC_BASEIDR_DSCR (0x1 << 3) +#define LCDC_BASEIDR_ADD (0x1 << 4) +#define LCDC_BASEIDR_DONE (0x1 << 5) +#define LCDC_BASEIDR_OVR (0x1 << 6) + +#define ATMEL_LCDC_BASEIMR 0x0054 +#define LCDC_BASEIMR_DMA (0x1 << 2) +#define LCDC_BASEIMR_DSCR (0x1 << 3) +#define LCDC_BASEIMR_ADD (0x1 << 4) +#define LCDC_BASEIMR_DONE (0x1 << 5) +#define LCDC_BASEIMR_OVR (0x1 << 6) + +#define ATMEL_LCDC_BASEISR 0x0058 +#define LCDC_BASEISR_DMA (0x1 << 2) +#define LCDC_BASEISR_DSCR (0x1 << 3) +#define LCDC_BASEISR_ADD (0x1 << 4) +#define LCDC_BASEISR_DONE (0x1 << 5) +#define LCDC_BASEISR_OVR (0x1 << 6) + +#define ATMEL_LCDC_BASEHEAD 0x005C + +#define ATMEL_LCDC_BASEADDR 0x0060 + +#define ATMEL_LCDC_BASECTRL 0x0064 +#define LCDC_BASECTRL_DFETCH (0x1 << 0) +#define LCDC_BASECTRL_LFETCH (0x1 << 1) +#define LCDC_BASECTRL_DMAIEN (0x1 << 2) +#define LCDC_BASECTRL_DSCRIEN (0x1 << 3) +#define LCDC_BASECTRL_ADDIEN (0x1 << 4) +#define LCDC_BASECTRL_DONEIEN (0x1 << 5) + +#define ATMEL_LCDC_BASENEXT 0x0068 + +#define ATMEL_LCDC_BASECFG0 0x006C +#define LCDC_BASECFG0_SIF (0x1 << 0) +#define LCDC_BASECFG0_BLEN_OFFSET 4 +#define LCDC_BASECFG0_BLEN (0x3 << LCDC_BASECFG0_BLEN_OFFSET) +#define LCDC_BASECFG0_BLEN_AHB_SINGLE (0x0 << 4) +#define LCDC_BASECFG0_BLEN_AHB_INCR4 (0x1 << 4) +#define LCDC_BASECFG0_BLEN_AHB_INCR8 (0x2 << 4) +#define LCDC_BASECFG0_BLEN_AHB_INCR16 (0x3 << 4) +#define LCDC_BASECFG0_DLBO (0x1 << 8) + +#define ATMEL_LCDC_BASECFG1 0x0070 +#define LCDC_BASECFG1_CLUTEN (0x1 << 0) +#define LCDC_BASECFG1_RGBMODE_OFFSET 4 +#define LCDC_BASECFG1_RGBMODE (0xf << LCDC_BASECFG1_RGBMODE_OFFSET) +#define LCDC_BASECFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4) +#define LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4) +#define LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4) +#define LCDC_BASECFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4) +#define LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4) +#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4) +#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4) +#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4) +#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4) +#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4) +#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4) +#define LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4) +#define LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4) +#define LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4) +#define LCDC_BASECFG1_CLUTMODE_OFFSET 8 +#define LCDC_BASECFG1_CLUTMODE (0x3 << LCDC_BASECFG1_CLUTMODE_OFFSET) +#define LCDC_BASECFG1_CLUTMODE_1BPP (0x0 << 8) +#define LCDC_BASECFG1_CLUTMODE_2BPP (0x1 << 8) +#define LCDC_BASECFG1_CLUTMODE_4BPP (0x2 << 8) +#define LCDC_BASECFG1_CLUTMODE_8BPP (0x3 << 8) + +#define ATMEL_LCDC_BASECFG2 0x0074 + +#define ATMEL_LCDC_BASECFG3 0x0078 +#define LCDC_BASECFG3_BDEF_OFFSET 0 +#define LCDC_BASECFG3_BDEF (0xff << LCDC_BASECFG3_BDEF_OFFSET) +#define LCDC_BASECFG3_GDEF_OFFSET 8 +#define LCDC_BASECFG3_GDEF (0xff << LCDC_BASECFG3_GDEF_OFFSET) +#define LCDC_BASECFG3_RDEF_OFFSET 16 +#define LCDC_BASECFG3_RDEF (0xff << LCDC_BASECFG3_RDEF_OFFSET) + +#define ATMEL_LCDC_BASECFG4 0x007C +#define LCDC_BASECFG4_DMA (0x1 << 8) +#define LCDC_BASECFG4_REP (0x1 << 9) +#define LCDC_BASECFG4_DISCEN (0x1 << 11) + +#define ATMEL_LCDC_BASECFG5 0x0080 +#define LCDC_BASECFG5_DISCXPOS_OFFSET 0 +#define LCDC_BASECFG5_DISCXPOS (0x7ff << LCDC_BASECFG5_DISCXPOS_OFFSET) +#define LCDC_BASECFG5_DISCYPOS_OFFSET 16 +#define LCDC_BASECFG5_DISCYPOS (0x7ff << LCDC_BASECFG5_DISCYPOS_OFFSET) + +#define ATMEL_LCDC_BASECFG6 0x0084 +#define LCDC_BASECFG6_DISCXSIZE_OFFSET 0 +#define LCDC_BASECFG6_DISCXSIZE (0x7ff << LCDC_BASECFG6_DISCXSIZE_OFFSET) +#define LCDC_BASECFG6_DISCYSIZE_OFFSET 16 +#define LCDC_BASECFG6_DISCYSIZE (0x7ff << LCDC_BASECFG6_DISCYSIZE_OFFSET) + +#define ATMEL_LCDC_HEOCHER 0x0280 +#define ATMEL_LCDC2_HEOCHER 0x0340 +#define LCDC_HEOCHER_CHEN (0x1 << 0) +#define LCDC_HEOCHER_UPDATEEN (0x1 << 1) +#define LCDC_HEOCHER_A2QEN (0x1 << 2) + +#define ATMEL_LCDC_HEOCHDR 0x0284 +#define LCDC_HEOCHDR_CHDIS (0x1 << 0) +#define LCDC_HEOCHDR_CHRST (0x1 << 8) + +#define ATMEL_LCDC_HEOCHSR 0x0288 +#define LCDC_HEOCHSR_CHSR (0x1 << 0) +#define LCDC_HEOCHSR_UPDATESR (0x1 << 1) +#define LCDC_HEOCHSR_A2QSR (0x1 << 2) + +#define ATMEL_LCDC_HEOIER 0x028C +#define LCDC_HEOIER_DMA (0x1 << 2) +#define LCDC_HEOIER_DSCR (0x1 << 3) +#define LCDC_HEOIER_ADD (0x1 << 4) +#define LCDC_HEOIER_DONE (0x1 << 5) +#define LCDC_HEOIER_OVR (0x1 << 6) +#define LCDC_HEOIER_UDMA (0x1 << 10) +#define LCDC_HEOIER_UDSCR (0x1 << 11) +#define LCDC_HEOIER_UADD (0x1 << 12) +#define LCDC_HEOIER_UDONE (0x1 << 13) +#define LCDC_HEOIER_UOVR (0x1 << 14) +#define LCDC_HEOIER_VDMA (0x1 << 18) +#define LCDC_HEOIER_VDSCR (0x1 << 19) +#define LCDC_HEOIER_VADD (0x1 << 20) +#define LCDC_HEOIER_VDONE (0x1 << 21) +#define LCDC_HEOIER_VOVR (0x1 << 22) + +#define ATMEL_LCDC_HEOIDR 0x0290 +#define LCDC_HEOIDR_DMA (0x1 << 2) +#define LCDC_HEOIDR_DSCR (0x1 << 3) +#define LCDC_HEOIDR_ADD (0x1 << 4) +#define LCDC_HEOIDR_DONE (0x1 << 5) +#define LCDC_HEOIDR_OVR (0x1 << 6) +#define LCDC_HEOIDR_UDMA (0x1 << 10) +#define LCDC_HEOIDR_UDSCR (0x1 << 11) +#define LCDC_HEOIDR_UADD (0x1 << 12) +#define LCDC_HEOIDR_UDONE (0x1 << 13) +#define LCDC_HEOIDR_UOVR (0x1 << 14) +#define LCDC_HEOIDR_VDMA (0x1 << 18) +#define LCDC_HEOIDR_VDSCR (0x1 << 19) +#define LCDC_HEOIDR_VADD (0x1 << 20) +#define LCDC_HEOIDR_VDONE (0x1 << 21) +#define LCDC_HEOIDR_VOVR (0x1 << 22) + +#define ATMEL_LCDC_HEOIMR 0x0294 +#define LCDC_HEOIMR_DMA (0x1 << 2) +#define LCDC_HEOIMR_DSCR (0x1 << 3) +#define LCDC_HEOIMR_ADD (0x1 << 4) +#define LCDC_HEOIMR_DONE (0x1 << 5) +#define LCDC_HEOIMR_OVR (0x1 << 6) +#define LCDC_HEOIMR_UDMA (0x1 << 10) +#define LCDC_HEOIMR_UDSCR (0x1 << 11) +#define LCDC_HEOIMR_UADD (0x1 << 12) +#define LCDC_HEOIMR_UDONE (0x1 << 13) +#define LCDC_HEOIMR_UOVR (0x1 << 14) +#define LCDC_HEOIMR_VDMA (0x1 << 18) +#define LCDC_HEOIMR_VDSCR (0x1 << 19) +#define LCDC_HEOIMR_VADD (0x1 << 20) +#define LCDC_HEOIMR_VDONE (0x1 << 21) +#define LCDC_HEOIMR_VOVR (0x1 << 22) + +#define ATMEL_LCDC_HEOISR 0x0298 +#define LCDC_HEOISR_DMA (0x1 << 2) +#define LCDC_HEOISR_DSCR (0x1 << 3) +#define LCDC_HEOISR_ADD (0x1 << 4) +#define LCDC_HEOISR_DONE (0x1 << 5) +#define LCDC_HEOISR_OVR (0x1 << 6) +#define LCDC_HEOISR_UDMA (0x1 << 10) +#define LCDC_HEOISR_UDSCR (0x1 << 11) +#define LCDC_HEOISR_UADD (0x1 << 12) +#define LCDC_HEOISR_UDONE (0x1 << 13) +#define LCDC_HEOISR_UOVR (0x1 << 14) +#define LCDC_HEOISR_VDMA (0x1 << 18) +#define LCDC_HEOISR_VDSCR (0x1 << 19) +#define LCDC_HEOISR_VADD (0x1 << 20) +#define LCDC_HEOISR_VDONE (0x1 << 21) +#define LCDC_HEOISR_VOVR (0x1 << 22) + +#define ATMEL_LCDC_HEOHEAD 0x029C + +#define ATMEL_LCDC_HEOADDR 0x02A0 + +#define ATMEL_LCDC_HEOCTRL 0x02A4 +#define LCDC_HEOCTRL_DFETCH (0x1 << 0) +#define LCDC_HEOCTRL_LFETCH (0x1 << 1) +#define LCDC_HEOCTRL_DMAIEN (0x1 << 2) +#define LCDC_HEOCTRL_DSCRIEN (0x1 << 3) +#define LCDC_HEOCTRL_ADDIEN (0x1 << 4) +#define LCDC_HEOCTRL_DONEIEN (0x1 << 5) + +#define ATMEL_LCDC_HEONEXT 0x02A8 + +#define ATMEL_LCDC_HEOUHEAD 0x02AC + +#define ATMEL_LCDC_HEOUADDR 0x02B0 + +#define ATMEL_LCDC_HEOUCTRL 0x02B4 +#define LCDC_HEOUCTRL_UDFETCH (0x1 << 0) +#define LCDC_HEOUCTRL_UDMAIEN (0x1 << 2) +#define LCDC_HEOUCTRL_UDSCRIEN (0x1 << 3) +#define LCDC_HEOUCTRL_UADDIEN (0x1 << 4) +#define LCDC_HEOUCTRL_UDONEIEN (0x1 << 5) + +#define ATMEL_LCDC_HEOUNEXT 0x02B8 + +#define ATMEL_LCDC_HEOVHEAD 0x02BC + +#define ATMEL_LCDC_HEOVADDR 0x02C0 + +#define ATMEL_LCDC_HEOVCTRL 0x02C4 +#define LCDC_HEOVCTRL_VDFETCH (0x1 << 0) +#define LCDC_HEOVCTRL_VDMAIEN (0x1 << 2) +#define LCDC_HEOVCTRL_VDSCRIEN (0x1 << 3) +#define LCDC_HEOVCTRL_VADDIEN (0x1 << 4) +#define LCDC_HEOVCTRL_VDONEIEN (0x1 << 5) + +#define ATMEL_LCDC_HEOVNEXT 0x02C8 + +#define ATMEL_LCDC_HEOCFG0 0x02CC +#define LCDC_HEOCFG0_BLEN_OFFSET 4 +#define LCDC_HEOCFG0_BLEN (0x3 << LCDC_HEOCFG0_BLEN_OFFSET) +#define LCDC_HEOCFG0_BLEN_AHB_SINGLE (0x0 << 4) +#define LCDC_HEOCFG0_BLEN_AHB_INCR4 (0x1 << 4) +#define LCDC_HEOCFG0_BLEN_AHB_INCR8 (0x2 << 4) +#define LCDC_HEOCFG0_BLEN_AHB_INCR16 (0x3 << 4) +#define LCDC_HEOCFG0_BLENUV_OFFSET 6 +#define LCDC_HEOCFG0_BLENUV (0x3 << LCDC_HEOCFG0_BLENUV_OFFSET) +#define LCDC_HEOCFG0_BLENUV_AHB_SINGLE (0x0 << 6) +#define LCDC_HEOCFG0_BLENUV_AHB_INCR4 (0x1 << 6) +#define LCDC_HEOCFG0_BLENUV_AHB_INCR8 (0x2 << 6) +#define LCDC_HEOCFG0_BLENUV_AHB_INCR16 (0x3 << 6) +#define LCDC_HEOCFG0_DLBO (0x1 << 8) +#define LCDC_HEOCFG0_ROTDIS (0x1 << 12) +#define LCDC_HEOCFG0_LOCKDIS (0x1 << 13) + +#define ATMEL_LCDC_HEOCFG1 0x02D0 +#define LCDC_HEOCFG1_CLUTEN (0x1 << 0) +#define LCDC_HEOCFG1_YUVEN (0x1 << 1) +#define LCDC_HEOCFG1_RGBMODE_OFFSET 4 +#define LCDC_HEOCFG1_RGBMODE (0xf << LCDC_HEOCFG1_RGBMODE_OFFSET) +#define LCDC_HEOCFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4) +#define LCDC_HEOCFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4) +#define LCDC_HEOCFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4) +#define LCDC_HEOCFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4) +#define LCDC_HEOCFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4) +#define LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4) +#define LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4) +#define LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4) +#define LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4) +#define LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4) +#define LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4) +#define LCDC_HEOCFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4) +#define LCDC_HEOCFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4) +#define LCDC_HEOCFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4) +#define LCDC_HEOCFG1_CLUTMODE_OFFSET 8 +#define LCDC_HEOCFG1_CLUTMODE (0x3 << LCDC_HEOCFG1_CLUTMODE_OFFSET) +#define LCDC_HEOCFG1_CLUTMODE_1BPP (0x0 << 8) +#define LCDC_HEOCFG1_CLUTMODE_2BPP (0x1 << 8) +#define LCDC_HEOCFG1_CLUTMODE_4BPP (0x2 << 8) +#define LCDC_HEOCFG1_CLUTMODE_8BPP (0x3 << 8) +#define LCDC_HEOCFG1_YUVMODE_OFFSET 12 +#define LCDC_HEOCFG1_YUVMODE (0xf << LCDC_HEOCFG1_YUVMODE_OFFSET) +#define LCDC_HEOCFG1_YUVMODE_32BPP_AYCBCR (0x0 << 12) +#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE0 (0x1 << 12) +#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE1 (0x2 << 12) +#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE2 (0x3 << 12) +#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE3 (0x4 << 12) +#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_SEMIPLANAR (0x5 << 12) +#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_PLANAR (0x6 << 12) +#define LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_SEMIPLANAR (0x7 << 12) +#define LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_PLANAR (0x8 << 12) +#define LCDC_HEOCFG1_YUV422ROT (0x1 << 16) +#define LCDC_HEOCFG1_YUV422SWP (0x1 << 17) + +#define ATMEL_LCDC_HEOCFG2 0x02D4 +#define LCDC_HEOCFG2_XOFFSET_OFFSET 0 +#define LCDC_HEOCFG2_XOFFSET (0x7ff << LCDC_HEOCFG2_XOFFSET_OFFSET) +#define LCDC_HEOCFG2_YOFFSET_OFFSET 16 +#define LCDC_HEOCFG2_YOFFSET (0x7ff << LCDC_HEOCFG2_YOFFSET_OFFSET) + +#define ATMEL_LCDC_HEOCFG3 0x02D8 +#define LCDC_HEOCFG3_XSIZE_OFFSET 0 +#define LCDC_HEOCFG3_XSIZE (0x7ff << LCDC_HEOCFG3_XSIZE_OFFSET) +#define LCDC_HEOCFG3_YSIZE_OFFSET 16 +#define LCDC_HEOCFG3_YSIZE (0x7ff << LCDC_HEOCFG3_YSIZE_OFFSET) + +#define ATMEL_LCDC_HEOCFG4 0x02DC +#define LCDC_HEOCFG4_XMEM_SIZE_OFFSET 0 +#define LCDC_HEOCFG4_XMEM_SIZE (0x7ff << LCDC_HEOCFG4_XMEM_SIZE_OFFSET) +#define LCDC_HEOCFG4_YMEM_SIZE_OFFSET 16 +#define LCDC_HEOCFG4_YMEM_SIZE (0x7ff << LCDC_HEOCFG4_YMEM_SIZE_OFFSET) + +#define ATMEL_LCDC_HEOCFG5 0x02E0 + +#define ATMEL_LCDC_HEOCFG6 0x02E4 + +#define ATMEL_LCDC_HEOCFG7 0x02E8 + +#define ATMEL_LCDC_HEOCFG8 0x02EC + +#define ATMEL_LCDC_HEOCFG9 0x02F0 +#define LCDC_HEOCFG9_BDEF_OFFSET 0 +#define LCDC_HEOCFG9_BDEF (0xff << LCDC_HEOCFG9_BDEF_OFFSET) +#define LCDC_HEOCFG9_GDEF_OFFSET 8 +#define LCDC_HEOCFG9_GDEF (0xff << LCDC_HEOCFG9_GDEF_OFFSET) +#define LCDC_HEOCFG9_RDEF_OFFSET 16 +#define LCDC_HEOCFG9_RDEF (0xff << LCDC_HEOCFG9_RDEF_OFFSET) + +#define ATMEL_LCDC_HEOCFG10 0x02F4 +#define LCDC_HEOCFG10_BKEY_OFFSET 0 +#define LCDC_HEOCFG10_BKEY (0xff << LCDC_HEOCFG10_BKEY_OFFSET) +#define LCDC_HEOCFG10_GKEY_OFFSET 8 +#define LCDC_HEOCFG10_GKEY (0xff << LCDC_HEOCFG10_GKEY_OFFSET) +#define LCDC_HEOCFG10_RKEY_OFFSET 16 +#define LCDC_HEOCFG10_RKEY (0xff << LCDC_HEOCFG10_RKEY_OFFSET) + +#define ATMEL_LCDC_HEOCFG11 0x02F8 +#define LCDC_HEOCFG11_BMASK_OFFSET 0 +#define LCDC_HEOCFG11_BMASK (0xff << LCDC_HEOCFG11_BMASK_OFFSET) +#define LCDC_HEOCFG11_GMASK_OFFSET 8 +#define LCDC_HEOCFG11_GMASK (0xff << LCDC_HEOCFG11_GMASK_OFFSET) +#define LCDC_HEOCFG11_RMASK_OFFSET 16 +#define LCDC_HEOCFG11_RMASK (0xff << LCDC_HEOCFG11_RMASK_OFFSET) + +#define ATMEL_LCDC_HEOCFG12 0x02FC +#define LCDC_HEOCFG12_CRKEY (0x1 << 0) +#define LCDC_HEOCFG12_INV (0x1 << 1) +#define LCDC_HEOCFG12_ITER2BL (0x1 << 2) +#define LCDC_HEOCFG12_ITER (0x1 << 3) +#define LCDC_HEOCFG12_REVALPHA (0x1 << 4) +#define LCDC_HEOCFG12_GAEN (0x1 << 5) +#define LCDC_HEOCFG12_LAEN (0x1 << 6) +#define LCDC_HEOCFG12_OVR (0x1 << 7) +#define LCDC_HEOCFG12_DMA (0x1 << 8) +#define LCDC_HEOCFG12_REP (0x1 << 9) +#define LCDC_HEOCFG12_DSTKEY (0x1 << 10) +#define LCDC_HEOCFG12_VIDPRI (0x1 << 12) +#define LCDC_HEOCFG12_GA_OFFSET 16 +#define LCDC_HEOCFG12_GA (0xff << LCDC_HEOCFG12_GA_OFFSET) + +#define ATMEL_LCDC_HEOCFG13 0x0300 +#define LCDC_HEOCFG13_XFACTOR_OFFSET 0 +#define LCDC_HEOCFG13_XFACTOR (0x1fff << LCDC_HEOCFG13_XFACTOR_OFFSET) +#define LCDC_HEOCFG13_YFACTOR_OFFSET 16 +#define LCDC_HEOCFG13_YFACTOR (0x1fff << LCDC_HEOCFG13_YFACTOR_OFFSET) +#define LCDC_HEOCFG13_SCALEN (0x1 << 31) + +#define ATMEL_LCDC_HEOCFG14 0x0304 +#define LCDC_HEOCFG14_CSCRY_OFFSET 0 +#define LCDC_HEOCFG14_CSCRY (0x3ff << LCDC_HEOCFG14_CSCRY_OFFSET) +#define LCDC_HEOCFG14_CSCRU_OFFSET 10 +#define LCDC_HEOCFG14_CSCRU (0x3ff << LCDC_HEOCFG14_CSCRU_OFFSET) +#define LCDC_HEOCFG14_CSCRV_OFFSET 20 +#define LCDC_HEOCFG14_CSCRV (0x3ff << LCDC_HEOCFG14_CSCRV_OFFSET) +#define LCDC_HEOCFG14_CSCYOFF (0x1 << 30) + +#define ATMEL_LCDC_HEOCFG15 0x0308 +#define LCDC_HEOCFG15_CSCGY_OFFSET 0 +#define LCDC_HEOCFG15_CSCGY (0x3ff << LCDC_HEOCFG15_CSCGY_OFFSET) +#define LCDC_HEOCFG15_CSCGU_OFFSET 10 +#define LCDC_HEOCFG15_CSCGU (0x3ff << LCDC_HEOCFG15_CSCGU_OFFSET) +#define LCDC_HEOCFG15_CSCGV_OFFSET 20 +#define LCDC_HEOCFG15_CSCGV (0x3ff << LCDC_HEOCFG15_CSCGV_OFFSET) +#define LCDC_HEOCFG15_CSCUOFF (0x1 << 30) + +#define ATMEL_LCDC_HEOCFG16 0x030C +#define LCDC_HEOCFG16_CSCBY_OFFSET 0 +#define LCDC_HEOCFG16_CSCBY (0x3ff << LCDC_HEOCFG16_CSCBY_OFFSET) +#define LCDC_HEOCFG16_CSCBU_OFFSET 10 +#define LCDC_HEOCFG16_CSCBU (0x3ff << LCDC_HEOCFG16_CSCBU_OFFSET) +#define LCDC_HEOCFG16_CSCBV_OFFSET 20 +#define LCDC_HEOCFG16_CSCBV (0x3ff << LCDC_HEOCFG16_CSCBV_OFFSET) +#define LCDC_HEOCFG16_CSCVOFF (0x1 << 30) + +#define ATMEL_LCDC_HCRCHER 0x0340 +#define LCDC_HCRCHER_CHEN (0x1 << 0) +#define LCDC_HCRCHER_UPDATEEN (0x1 << 1) +#define LCDC_HCRCHER_A2QEN (0x1 << 2) + +#define ATMEL_LCDC_HCRCHDR 0x0344 +#define LCDC_HCRCHDR_CHDIS (0x1 << 0) +#define LCDC_HCRCHDR_CHRST (0x1 << 8) + +#define ATMEL_LCDC_HCRCHSR 0x0348 +#define LCDC_HCRCHSR_CHSR (0x1 << 0) +#define LCDC_HCRCHSR_UPDATESR (0x1 << 1) +#define LCDC_HCRCHSR_A2QSR (0x1 << 2) + +#define ATMEL_LCDC_HCRIER 0x034C +#define LCDC_HCRIER_DMA (0x1 << 2) +#define LCDC_HCRIER_DSCR (0x1 << 3) +#define LCDC_HCRIER_ADD (0x1 << 4) +#define LCDC_HCRIER_DONE (0x1 << 5) +#define LCDC_HCRIER_OVR (0x1 << 6) + +#define ATMEL_LCDC_HCRIDR 0x0350 +#define LCDC_HCRIDR_DMA (0x1 << 2) +#define LCDC_HCRIDR_DSCR (0x1 << 3) +#define LCDC_HCRIDR_ADD (0x1 << 4) +#define LCDC_HCRIDR_DONE (0x1 << 5) +#define LCDC_HCRIDR_OVR (0x1 << 6) + +#define ATMEL_LCDC_HCRIMR 0x0354 +#define LCDC_HCRIMR_DMA (0x1 << 2) +#define LCDC_HCRIMR_DSCR (0x1 << 3) +#define LCDC_HCRIMR_ADD (0x1 << 4) +#define LCDC_HCRIMR_DONE (0x1 << 5) +#define LCDC_HCRIMR_OVR (0x1 << 6) + +#define ATMEL_LCDC_HCRISR 0x0358 +#define LCDC_HCRISR_DMA (0x1 << 2) +#define LCDC_HCRISR_DSCR (0x1 << 3) +#define LCDC_HCRISR_ADD (0x1 << 4) +#define LCDC_HCRISR_DONE (0x1 << 5) +#define LCDC_HCRISR_OVR (0x1 << 6) + +#define ATMEL_LCDC_HCRHEAD 0x035C + +#define ATMEL_LCDC_HCRADDR 0x0360 + +#define ATMEL_LCDC_HCRCTRL 0x0364 +#define LCDC_HCRCTRL_DFETCH (0x1 << 0) +#define LCDC_HCRCTRL_LFETCH (0x1 << 1) +#define LCDC_HCRCTRL_DMAIEN (0x1 << 2) +#define LCDC_HCRCTRL_DSCRIEN (0x1 << 3) +#define LCDC_HCRCTRL_ADDIEN (0x1 << 4) +#define LCDC_HCRCTRL_DONEIEN (0x1 << 5) + +#define ATMEL_LCDC_HCRNEXT 0x0368 + +#define ATMEL_LCDC_HCRCFG0 0x036C +#define LCDC_HCRCFG0_BLEN_OFFSET 4 +#define LCDC_HCRCFG0_BLEN (0x3 << LCDC_HCRCFG0_BLEN_OFFSET) +#define LCDC_HCRCFG0_BLEN_AHB_SINGLE (0x0 << 4) +#define LCDC_HCRCFG0_BLEN_AHB_INCR4 (0x1 << 4) +#define LCDC_HCRCFG0_BLEN_AHB_INCR8 (0x2 << 4) +#define LCDC_HCRCFG0_BLEN_AHB_INCR16 (0x3 << 4) +#define LCDC_HCRCFG0_DLBO (0x1 << 8) + +#define ATMEL_LCDC_HCRCFG1 0x0370 +#define LCDC_HCRCFG1_CLUTEN (0x1 << 0) +#define LCDC_HCRCFG1_RGBMODE_OFFSET 4 +#define LCDC_HCRCFG1_RGBMODE (0xf << LCDC_HCRCFG1_RGBMODE_OFFSET) +#define LCDC_HCRCFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4) +#define LCDC_HCRCFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4) +#define LCDC_HCRCFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4) +#define LCDC_HCRCFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4) +#define LCDC_HCRCFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4) +#define LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4) +#define LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4) +#define LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4) +#define LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4) +#define LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4) +#define LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4) +#define LCDC_HCRCFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4) +#define LCDC_HCRCFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4) +#define LCDC_HCRCFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4) +#define LCDC_HCRCFG1_CLUTMODE_OFFSET 8 +#define LCDC_HCRCFG1_CLUTMODE (0x3 << LCDC_HCRCFG1_CLUTMODE_OFFSET) +#define LCDC_HCRCFG1_CLUTMODE_1BPP (0x0 << 8) +#define LCDC_HCRCFG1_CLUTMODE_2BPP (0x1 << 8) +#define LCDC_HCRCFG1_CLUTMODE_4BPP (0x2 << 8) +#define LCDC_HCRCFG1_CLUTMODE_8BPP (0x3 << 8) + +#define ATMEL_LCDC_HCRCFG2 0x0374 +#define LCDC_HCRCFG2_XOFFSET_OFFSET 0 +#define LCDC_HCRCFG2_XOFFSET (0x7ff << LCDC_HCRCFG2_XOFFSET_OFFSET) +#define LCDC_HCRCFG2_YOFFSET_OFFSET 16 +#define LCDC_HCRCFG2_YOFFSET (0x7ff << LCDC_HCRCFG2_YOFFSET_OFFSET) + +#define ATMEL_LCDC_HCRCFG3 0x0378 +#define LCDC_HCRCFG3_XSIZE_OFFSET 0 +#define LCDC_HCRCFG3_XSIZE (0x7f << LCDC_HCRCFG3_XSIZE_OFFSET) +#define LCDC_HCRCFG3_YSIZE_OFFSET 16 +#define LCDC_HCRCFG3_YSIZE (0x7f << LCDC_HCRCFG3_YSIZE_OFFSET) + +#define ATMEL_LCDC_HCRCFG4 0x037C + +#define ATMEL_LCDC_HCRCFG6 0x0384 +#define LCDC_HCRCFG6_BDEF_OFFSET 0 +#define LCDC_HCRCFG6_BDEF (0xff << LCDC_HCRCFG6_BDEF_OFFSET) +#define LCDC_HCRCFG6_GDEF_OFFSET 8 +#define LCDC_HCRCFG6_GDEF (0xff << LCDC_HCRCFG6_GDEF_OFFSET) +#define LCDC_HCRCFG6_RDEF_OFFSET 16 +#define LCDC_HCRCFG6_RDEF (0xff << LCDC_HCRCFG6_RDEF_OFFSET) + +#define ATMEL_LCDC_HCRCFG7 0x0388 +#define LCDC_HCRCFG7_BKEY_OFFSET 0 +#define LCDC_HCRCFG7_BKEY (0xff << LCDC_HCRCFG7_BKEY_OFFSET) +#define LCDC_HCRCFG7_GKEY_OFFSET 8 +#define LCDC_HCRCFG7_GKEY (0xff << LCDC_HCRCFG7_GKEY_OFFSET) +#define LCDC_HCRCFG7_RKEY_OFFSET 16 +#define LCDC_HCRCFG7_RKEY (0xff << LCDC_HCRCFG7_RKEY_OFFSET) + +#define ATMEL_LCDC_HCRCFG8 0x038C +#define LCDC_HCRCFG8_BMASK_OFFSET 0 +#define LCDC_HCRCFG8_BMASK (0xff << LCDC_HCRCFG8_BMASK_OFFSET) +#define LCDC_HCRCFG8_GMASK_OFFSET 8 +#define LCDC_HCRCFG8_GMASK (0xff << LCDC_HCRCFG8_GMASK_OFFSET) +#define LCDC_HCRCFG8_RMASK_OFFSET 16 +#define LCDC_HCRCFG8_RMASK (0xff << LCDC_HCRCFG8_RMASK_OFFSET) + +#define ATMEL_LCDC_HCRCFG9 0x0390 +#define LCDC_HCRCFG9_CRKEY (0x1 << 0) +#define LCDC_HCRCFG9_INV (0x1 << 1) +#define LCDC_HCRCFG9_ITER2BL (0x1 << 2) +#define LCDC_HCRCFG9_ITER (0x1 << 3) +#define LCDC_HCRCFG9_REVALPHA (0x1 << 4) +#define LCDC_HCRCFG9_GAEN (0x1 << 5) +#define LCDC_HCRCFG9_LAEN (0x1 << 6) +#define LCDC_HCRCFG9_OVR (0x1 << 7) +#define LCDC_HCRCFG9_DMA (0x1 << 8) +#define LCDC_HCRCFG9_REP (0x1 << 9) +#define LCDC_HCRCFG9_DSTKEY (0x1 << 10) +#define LCDC_HCRCFG9_GA_OFFSET 16 +#define LCDC_HCRCFG9_GA_Msk (0xff << LCDC_HCRCFG9_GA_OFFSET) + +#define ATMEL_LCDC_BASECLUT 0x400 +#define ATMEL_LCDC2_BASECLUT 0x600 +#define LCDC_BASECLUT_BCLUT_OFFSET 0 +#define LCDC_BASECLUT_BCLUT (0xff << LCDC_BASECLUT_BCLUT_OFFSET) +#define LCDC_BASECLUT_GCLUT_OFFSET 8 +#define LCDC_BASECLUT_GCLUT (0xff << LCDC_BASECLUT_GCLUT_OFFSET) +#define LCDC_BASECLUT_RCLUT_OFFSET 16 +#define LCDC_BASECLUT_RCLUT (0xff << LCDC_BASECLUT_RCLUT_OFFSET) + +#define ATMEL_LCDC_OVR1CLUT 0x800 +#define ATMEL_LCDC2_OVR1CLUT 0xa00 +#define LCDC_OVR1CLUT_BCLUT_OFFSET 0 +#define LCDC_OVR1CLUT_BCLUT (0xff << LCDC_OVR1CLUT_BCLUT_OFFSET) +#define LCDC_OVR1CLUT_GCLUT_OFFSET 8 +#define LCDC_OVR1CLUT_GCLUT (0xff << LCDC_OVR1CLUT_GCLUT_OFFSET) +#define LCDC_OVR1CLUT_RCLUT_OFFSET 16 +#define LCDC_OVR1CLUT_RCLUT (0xff << LCDC_OVR1CLUT_RCLUT_OFFSET) +#define LCDC_OVR1CLUT_ACLUT_OFFSET 24 +#define LCDC_OVR1CLUT_ACLUT (0xff << LCDC_OVR1CLUT_ACLUT_OFFSET) + +#define ATMEL_LCDC_OVR2CLUT 0xe00 +#define LCDC_OVR2CLUT_BCLUT_OFFSET 0 +#define LCDC_OVR2CLUT_BCLUT (0xff << LCDC_OVR2CLUT_BCLUT_OFFSET) +#define LCDC_OVR2CLUT_GCLUT_OFFSET 8 +#define LCDC_OVR2CLUT_GCLUT (0xff << LCDC_OVR2CLUT_GCLUT_OFFSET) +#define LCDC_OVR2CLUT_RCLUT_OFFSET 16 +#define LCDC_OVR2CLUT_RCLUT (0xff << LCDC_OVR2CLUT_RCLUT_OFFSET) +#define LCDC_OVR2CLUT_ACLUT_OFFSET 24 +#define LCDC_OVR2CLUT_ACLUT (0xff << LCDC_OVR2CLUT_ACLUT_OFFSET) + +#define ATMEL_LCDC_HEOCLUT 0x1000 +#define ATMEL_LCDC2_HEOCLUT 0x1200 +#define LCDC_HEOCLUT_BCLUT_OFFSET 0 +#define LCDC_HEOCLUT_BCLUT (0xff << LCDC_HEOCLUT_BCLUT_OFFSET) +#define LCDC_HEOCLUT_GCLUT_OFFSET 8 +#define LCDC_HEOCLUT_GCLUT (0xff << LCDC_HEOCLUT_GCLUT_OFFSET) +#define LCDC_HEOCLUT_RCLUT_OFFSET 16 +#define LCDC_HEOCLUT_RCLUT (0xff << LCDC_HEOCLUT_RCLUT_OFFSET) +#define LCDC_HEOCLUT_ACLUT_OFFSET 24 +#define LCDC_HEOCLUT_ACLUT (0xff << LCDC_HEOCLUT_ACLUT_OFFSET) + +#define ATMEL_LCDC_HCRCLUT 0x1400 +#define ATMEL_LCDC2_HCRCLUT 0x1600 +#define LCDC_HCRCLUT_BCLUT_OFFSET 0 +#define LCDC_HCRCLUT_BCLUT (0xff << LCDC_HCRCLUT_BCLUT_OFFSET) +#define LCDC_HCRCLUT_GCLUT_OFFSET 8 +#define LCDC_HCRCLUT_GCLUT (0xff << LCDC_HCRCLUT_GCLUT_OFFSET) +#define LCDC_HCRCLUT_RCLUT_OFFSET 16 +#define LCDC_HCRCLUT_RCLUT (0xff << LCDC_HCRCLUT_RCLUT_OFFSET) +#define LCDC_HCRCLUT_ACLUT_OFFSET 24 +#define LCDC_HCRCLUT_ACLUT (0xff << LCDC_HCRCLUT_ACLUT_OFFSET) + +/* Base layer CLUT */ +#define ATMEL_HLCDC_LUT 0x0400 + + +#endif /* __MACH_ATMEL_HLCDC4_H__ */ diff --git a/arch/arm/mach-at91/include/mach/barebox-arm-head.h b/arch/arm/mach-at91/include/mach/barebox-arm-head.h index a9c8dd44a..7d6a009e2 100644 --- a/arch/arm/mach-at91/include/mach/barebox-arm-head.h +++ b/arch/arm/mach-at91/include/mach/barebox-arm-head.h @@ -1,7 +1,7 @@ #ifndef __MACH_ARM_HEAD_H #define __MACH_ARM_HEAD_H -#ifdef CONFIG_SHELL_NONE +#ifdef CONFIG_AT91_LOAD_BAREBOX_SRAM #define AT91_EXV6 ".word _barebox_image_size\n" #else #define AT91_EXV6 ".word _barebox_bare_init_size\n" diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h index 9a72474d7..71267e11e 100644 --- a/arch/arm/mach-at91/include/mach/board.h +++ b/arch/arm/mach-at91/include/mach/board.h @@ -24,13 +24,19 @@ #include #include #include +#include +#include