Merge branch 'for-next/pxa'
This commit is contained in:
Sascha Hauer
commit
1b95290433
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|
@ -56,6 +56,7 @@ obj-$(CONFIG_MACH_HIGHBANK) += highbank/
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|||
obj-$(CONFIG_MACH_IMX21ADS) += freescale-mx21-ads/
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obj-$(CONFIG_MACH_IMX233_OLINUXINO) += imx233-olinuxino/
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obj-$(CONFIG_MACH_IMX27ADS) += freescale-mx27-ads/
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obj-$(CONFIG_MACH_LUBBOCK) += lubbock/
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obj-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += marvell-armada-xp-gp/
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obj-$(CONFIG_MACH_MB7707) += module-mb7707/
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obj-$(CONFIG_MACH_MIOA701) += mioa701/
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@ -126,4 +127,5 @@ obj-$(CONFIG_MACH_VERSATILEPB) += versatile/
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obj-$(CONFIG_MACH_VEXPRESS) += vexpress/
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obj-$(CONFIG_MACH_VIRT2REAL) += virt2real/
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obj-$(CONFIG_MACH_ZEDBOARD) += avnet-zedboard/
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obj-$(CONFIG_MACH_ZYLONITE) += zylonite/
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obj-$(CONFIG_MACH_VARISCITE_MX6) += variscite-mx6/
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|
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@ -0,0 +1,2 @@
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obj-y += board.o
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lwl-y += lowlevel.o
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@ -0,0 +1,134 @@
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/*
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* (C) 2011 Robert Jarzmik <robert.jarzmik@free.fr>
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*
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* See file CREDITS for list of people who contributed to this
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||||
* project.
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||||
*
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||||
* This program is free software; you can redistribute it and/or
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||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
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||||
*
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||||
*/
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||||
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#include <common.h>
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#include <driver.h>
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#include <environment.h>
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#include <fs.h>
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#include <init.h>
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#include <partition.h>
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#include <led.h>
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#include <gpio.h>
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#include <pwm.h>
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#include <linux/sizes.h>
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#include <mach/devices.h>
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#include <mach/mfp-pxa27x.h>
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#include <mach/pxa-regs.h>
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#include <mach/udc_pxa2xx.h>
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#include <mach/mci_pxa2xx.h>
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#include <net/smc91111.h>
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#include <asm/armlinux.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <generated/mach-types.h>
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#define ECOR 0x8000
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#define ECOR_RESET 0x80
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#define ECOR_LEVEL_IRQ 0x40
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#define ECOR_WR_ATTRIB 0x04
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#define ECOR_ENABLE 0x01
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#define ECSR 0x8002
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#define ECSR_IOIS8 0x20
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#define ECSR_PWRDWN 0x04
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#define ECSR_INT 0x02
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static struct smc91c111_pdata smsc91x_pdata = {
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.control_setup = 0x0800,
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.config_setup = 0x10b2,
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.bus_width = 16,
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.addr_shift = 2,
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};
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static unsigned long lubbock_pin_config[] = {
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GPIO15_nCS_1, /* CS1 - Flash */
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GPIO78_nCS_2, /* CS2 - Baseboard FGPA + SRAM */
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GPIO79_nCS_3, /* CS3 - SMC ethernet */
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GPIO80_nCS_4, /* CS4 - SA1111 */
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/* LCD - 16bpp DSTN */
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GPIOxx_LCD_DSTN_16BPP,
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/* FFUART */
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GPIO34_FFUART_RXD,
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GPIO35_FFUART_CTS,
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GPIO36_FFUART_DCD,
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GPIO37_FFUART_DSR,
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GPIO38_FFUART_RI,
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GPIO39_FFUART_TXD,
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GPIO40_FFUART_DTR,
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GPIO41_FFUART_RTS,
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};
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static int lubbock_devices_init(void)
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{
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void *nor0_iospace;
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armlinux_set_architecture(MACH_TYPE_LUBBOCK);
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pxa_add_uart((void *)0x40100000, 0);
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pxa_add_pwm((void *)0x40b00000, 0);
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nor0_iospace = map_io_sections(0x0, (void *)0xe0000000, SZ_64M);
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add_cfi_flash_device(0, (ulong)nor0_iospace, SZ_64M, 0);
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add_cfi_flash_device(1, 0x04000000, SZ_64M, 0);
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devfs_add_partition("nor0", SZ_2M, SZ_256K, DEVFS_PARTITION_FIXED,
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"env0");
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add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL,
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0x0c000300, 0xff4000, IORESOURCE_MEM,
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&smsc91x_pdata);
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return 0;
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}
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device_initcall(lubbock_devices_init);
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static void smc_init(void)
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{
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/* SMC91c96 */
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void __iomem *attaddr = (void __iomem *)0x0e000000;
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writel(ECOR_RESET, attaddr + (ECOR << 2));
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mdelay(100);
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writel(0, attaddr + (ECOR << 2));
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writel(ECOR_ENABLE, attaddr + (ECOR << 2));
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/* force 16-bit mode */
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writel(0, attaddr + (ECSR << 2));
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mdelay(100);
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}
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static int lubbock_coredevice_init(void)
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{
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barebox_set_model("Lubbock PXA25x");
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barebox_set_hostname("lubbock");
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pxa2xx_mfp_config(ARRAY_AND_SIZE(lubbock_pin_config));
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smc_init();
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return 0;
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}
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coredevice_initcall(lubbock_coredevice_init);
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static int lubbock_mem_init(void)
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{
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arm_add_mem_device("ram0", 0xa0000000, SZ_64M);
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add_mem_device("sram0", 0x0a000000, SZ_1M, IORESOURCE_MEM_WRITEABLE);
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return 0;
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}
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mem_initcall(lubbock_mem_init);
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@ -0,0 +1,5 @@
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#!/bin/sh
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global.bootm.image="/dev/nor0.kernel"
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#global.bootm.oftree="/env/oftree"
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global.linux.bootargs.dyn.root="root=ubi0:linux_root ubi.mtd=nor0.root rootfstype=ubifs"
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@ -0,0 +1,11 @@
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#!/bin/sh
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if [ "$1" = menu ]; then
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init-menu-add-entry "$0" "NOR partitions"
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exit
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fi
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mtdparts="2048k@0(nor0.barebox)ro,256k(nor0.barebox-env),256k(nor0.barebox-logo),256k(nor0.barebox-logo2),5120k(nor0.kernel),-(nor0.root)"
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kernelname="application-flash"
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mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts}
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@ -0,0 +1 @@
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console=ttyS0,115200
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@ -0,0 +1,192 @@
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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#include <linux/sizes.h>
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#include <mach/pxa-regs.h>
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#include <mach/regs-ost.h>
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/*
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* Memory settings
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*/
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#define DEFAULT_MSC0_VAL 0x23d223d2
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#define DEFAULT_MSC1_VAL 0x3ff1a441
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#define DEFAULT_MSC2_VAL 0x7ff17ff1
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#define DEFAULT_MDCNFG_VAL 0x00001ac9
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#define DEFAULT_MDREFR_VAL 0x00018018
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#define DEFAULT_MDMRS_VAL 0x00000000
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#define DEFAULT_FLYCNFG_VAL 0x00000000
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#define DEFAULT_SXCNFG_VAL 0x00000000
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/*
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* PCMCIA and CF Interfaces
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*/
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#define DEFAULT_MECR_VAL 0x00000000
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#define DEFAULT_MCMEM0_VAL 0x00010504
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#define DEFAULT_MCMEM1_VAL 0x00010504
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#define DEFAULT_MCATT0_VAL 0x00010504
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#define DEFAULT_MCATT1_VAL 0x00010504
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#define DEFAULT_MCIO0_VAL 0x00004715
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#define DEFAULT_MCIO1_VAL 0x00004715
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static inline void writelrb(uint32_t val, volatile u32 __iomem *addr)
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{
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writel(val, addr);
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barrier();
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readl(addr);
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barrier();
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}
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static inline void pxa_wait_ticks(int ticks)
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{
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writel(0, &OSCR);
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while (readl(&OSCR) < ticks)
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barrier();
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}
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static inline void pxa2xx_dram_init(void)
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{
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uint32_t tmp;
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int i;
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/*
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* 1) Initialize Asynchronous static memory controller
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*/
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writelrb(DEFAULT_MSC0_VAL, &MSC0);
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writelrb(DEFAULT_MSC1_VAL, &MSC1);
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writelrb(DEFAULT_MSC2_VAL, &MSC2);
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/*
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* 2) Initialize Card Interface
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*/
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/* MECR: Memory Expansion Card Register */
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writelrb(DEFAULT_MECR_VAL, &MECR);
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/* MCMEM0: Card Interface slot 0 timing */
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writelrb(DEFAULT_MCMEM0_VAL, &MCMEM0);
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/* MCMEM1: Card Interface slot 1 timing */
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writelrb(DEFAULT_MCMEM1_VAL, &MCMEM1);
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/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
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writelrb(DEFAULT_MCATT0_VAL, &MCATT0);
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/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
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writelrb(DEFAULT_MCATT1_VAL, &MCATT1);
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/* MCIO0: Card Interface I/O Space Timing, slot 0 */
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writelrb(DEFAULT_MCIO0_VAL, &MCIO0);
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/* MCIO1: Card Interface I/O Space Timing, slot 1 */
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writelrb(DEFAULT_MCIO1_VAL, &MCIO1);
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/*
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* 3) Configure Fly-By DMA register
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*/
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writelrb(DEFAULT_FLYCNFG_VAL, &FLYCNFG);
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/*
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* 4) Initialize Timing for Sync Memory (SDCLK0)
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*/
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/*
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* Before accessing MDREFR we need a valid DRI field, so we set
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* this to power on defaults + DRI field.
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*/
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/* Read current MDREFR config and zero out DRI */
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tmp = readl(&MDREFR) & ~0xfff;
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/* Add user-specified DRI */
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tmp |= DEFAULT_MDREFR_VAL & 0xfff;
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/* Configure important bits */
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tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
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tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
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/* Write MDREFR back */
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writelrb(tmp, &MDREFR);
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/*
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* 5) Initialize Synchronous Static Memory (Flash/Peripherals)
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*/
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/* Initialize SXCNFG register. Assert the enable bits.
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||||
*
|
||||
* Write SXMRS to cause an MRS command to all enabled banks of
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||||
* synchronous static memory. Note that SXLCR need not be written
|
||||
* at this time.
|
||||
*/
|
||||
writelrb(DEFAULT_SXCNFG_VAL, &SXCNFG);
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||||
|
||||
/*
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||||
* 6) Initialize SDRAM
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||||
*/
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||||
|
||||
writelrb(DEFAULT_MDREFR_VAL & ~MDREFR_SLFRSH, &MDREFR);
|
||||
writelrb(DEFAULT_MDREFR_VAL | MDREFR_E1PIN, &MDREFR);
|
||||
|
||||
/*
|
||||
* 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
|
||||
* but not enable each SDRAM partition pair.
|
||||
*/
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||||
|
||||
writelrb(DEFAULT_MDCNFG_VAL &
|
||||
~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), &MDCNFG);
|
||||
/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
|
||||
pxa_wait_ticks(0x300);
|
||||
|
||||
/*
|
||||
* 8) Trigger a number (usually 8) refresh cycles by attempting
|
||||
* non-burst read or write accesses to disabled SDRAM, as commonly
|
||||
* specified in the power up sequence documented in SDRAM data
|
||||
* sheets. The address(es) used for this purpose must not be
|
||||
* cacheable.
|
||||
*/
|
||||
for (i = 9; i >= 0; i--) {
|
||||
writel(i, 0xa0000000);
|
||||
barrier();
|
||||
}
|
||||
/*
|
||||
* 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
|
||||
*/
|
||||
|
||||
tmp = DEFAULT_MDCNFG_VAL &
|
||||
(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
|
||||
tmp |= readl(&MDCNFG);
|
||||
writelrb(tmp, &MDCNFG);
|
||||
|
||||
/*
|
||||
* 10) Write MDMRS.
|
||||
*/
|
||||
|
||||
writelrb(DEFAULT_MDMRS_VAL, &MDMRS);
|
||||
|
||||
/*
|
||||
* 11) Enable APD
|
||||
*/
|
||||
|
||||
if (DEFAULT_MDREFR_VAL & MDREFR_APD) {
|
||||
tmp = readl(&MDREFR);
|
||||
tmp |= MDREFR_APD;
|
||||
writelrb(tmp, &MDREFR);
|
||||
}
|
||||
}
|
||||
|
||||
void __bare_init __naked barebox_arm_reset_vector(void)
|
||||
{
|
||||
unsigned long pssr = PSSR;
|
||||
unsigned long pc = get_pc();
|
||||
|
||||
arm_cpu_lowlevel_init();
|
||||
CKEN |= CKEN_OSTIMER | CKEN_MEMC | CKEN_FFUART;
|
||||
|
||||
/*
|
||||
* When not running from SDRAM, get it out of self refresh, and/or
|
||||
* initialize it.
|
||||
*/
|
||||
if (!(pc >= 0xa0000000 && pc < 0xb0000000))
|
||||
pxa2xx_dram_init();
|
||||
|
||||
if ((pssr >= 0xa0000000 && pssr < 0xb0000000) ||
|
||||
(pssr >= 0x04000000 && pssr < 0x10000000))
|
||||
asm("mov pc, %0" : : "r"(pssr) : );
|
||||
|
||||
barebox_arm_entry(0xa0000000, SZ_64M, 0);
|
||||
}
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
obj-y += board.o
|
||||
lwl-y += lowlevel.o
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* (C) 2014 Robert Jarzmik <robert.jarzmik@free.fr>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#include <driver.h>
|
||||
#include <environment.h>
|
||||
#include <fs.h>
|
||||
#include <gpio.h>
|
||||
#include <init.h>
|
||||
#include <partition.h>
|
||||
#include <led.h>
|
||||
#include <net/smc91111.h>
|
||||
#include <platform_data/mtd-nand-mrvl.h>
|
||||
#include <pwm.h>
|
||||
|
||||
#include <mach/devices.h>
|
||||
#include <mach/mfp-pxa3xx.h>
|
||||
#include <mach/pxa-regs.h>
|
||||
|
||||
#include <asm/armlinux.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <generated/mach-types.h>
|
||||
|
||||
#include "zylonite.h"
|
||||
|
||||
static struct smc91c111_pdata smsc91x_pdata;
|
||||
static struct mrvl_nand_platform_data nand_pdata = {
|
||||
.keep_config = 0,
|
||||
.flash_bbt = 1,
|
||||
};
|
||||
|
||||
static mfp_cfg_t pxa310_mfp_cfg[] = {
|
||||
/* FFUART */
|
||||
MFP_CFG_LPM(GPIO99, AF1, FLOAT), /* GPIO99_UART1_RXD */
|
||||
MFP_CFG_LPM(GPIO100, AF1, FLOAT), /* GPIO100_UART1_RXD */
|
||||
MFP_CFG_LPM(GPIO101, AF1, FLOAT), /* GPIO101_UART1_CTS */
|
||||
MFP_CFG_LPM(GPIO106, AF1, FLOAT), /* GPIO106_UART1_CTS */
|
||||
|
||||
/* Ethernet */
|
||||
MFP_CFG(GPIO2, AF1), /* GPIO2_nCS3 */
|
||||
};
|
||||
|
||||
static int zylonite_devices_init(void)
|
||||
{
|
||||
armlinux_set_architecture(MACH_TYPE_ZYLONITE);
|
||||
pxa_add_uart((void *)0x40100000, 0);
|
||||
add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL,
|
||||
0x14000300, 0x100000, IORESOURCE_MEM,
|
||||
&smsc91x_pdata);
|
||||
add_generic_device("mrvl_nand", DEVICE_ID_DYNAMIC, NULL,
|
||||
0x43100000, 0x1000, IORESOURCE_MEM, &nand_pdata);
|
||||
return 0;
|
||||
}
|
||||
device_initcall(zylonite_devices_init);
|
||||
|
||||
static int zylonite_coredevice_init(void)
|
||||
{
|
||||
barebox_set_model("Zylonite");
|
||||
barebox_set_hostname("zylonite");
|
||||
|
||||
mfp_init();
|
||||
if (cpu_is_pxa310())
|
||||
pxa3xx_mfp_config(pxa310_mfp_cfg, ARRAY_SIZE(pxa310_mfp_cfg));
|
||||
CKENA |= CKEN_NAND | CKEN_SMC | CKEN_FFUART | CKEN_GPIO;
|
||||
/*
|
||||
* Configure Ethernet controller :
|
||||
* MCS1: setup VLIO on nCS3, with 15 DF_SCLK cycles (max) for hold,
|
||||
* setup and assertion times
|
||||
* CSADRCFG3: DFI AA/D multiplexing VLIO, addr split at bit <16>, full
|
||||
* latched mode, 7 DF_SCLK cycles (max) for nLUA and nLLA.
|
||||
*/
|
||||
MSC1 = 0x7ffc0000 | (MSC1 & 0x0000ffff);
|
||||
CSADRCFG3 = 0x003e080b;
|
||||
|
||||
return 0;
|
||||
}
|
||||
coredevice_initcall(zylonite_coredevice_init);
|
||||
|
||||
static int zylonite_mem_init(void)
|
||||
{
|
||||
arm_add_mem_device("ram0", 0x80000000, 64 * 1024 * 1024);
|
||||
return 0;
|
||||
}
|
||||
mem_initcall(zylonite_mem_init);
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
#!/bin/sh
|
||||
|
||||
PATH=/env/bin
|
||||
export PATH
|
||||
|
||||
. /env/config
|
||||
addpart /dev/nand0 $mtdparts
|
||||
usbserial -s "Zylonite usb gadget"
|
||||
|
||||
# Phase1: check for MTD override
|
||||
mtd_env_override
|
||||
if [ $? = 0 ]; then
|
||||
echo "Switching to custom environment"
|
||||
/env/init
|
||||
exit
|
||||
fi
|
||||
|
||||
# Phase2: initiate network
|
||||
dhcp -H zylonite
|
||||
|
||||
# Phase3: activate netconsole, broadcast everywhere
|
||||
netconsole.ip=255.255.255.255
|
||||
netconsole.active=ioe
|
||||
netconsole.port=6666
|
||||
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
#!/bin/sh
|
||||
|
||||
loadenv /dev/nand0.barebox-env
|
||||
exit $?
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
#!/bin/sh
|
||||
|
||||
autoboot_timeout=3
|
||||
|
||||
mtdparts="128k@0(TIMH)ro,128k@128k(OBMI)ro,768k@256k(barebox),256k@1024k(barebox-env),12M@1280k(kernel),38016k@13568k(root)"
|
||||
bootargs="$bootargs mtdparts=pxa3xx_nand-0:$mtdparts ubi.mtd=5 rootfstype=ubifs root=ubi0:root ro ram=64M console=ttyS0,115200"
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
#include <common.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/barebox-arm-head.h>
|
||||
#include <asm/barebox-arm.h>
|
||||
|
||||
void __naked barebox_arm_reset_vector(void)
|
||||
{
|
||||
arm_cpu_lowlevel_init();
|
||||
barebox_arm_entry(0x80000000, SZ_64M, NULL);
|
||||
}
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* (C) 2011 Robert Jarzmik <robert.jarzmik@free.fr>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
#ifndef _ZYLONITE_H_
|
||||
#define _ZYLONITE_H_
|
||||
|
||||
|
||||
#endif /* _ZYLONITE_H */
|
||||
|
|
@ -0,0 +1,106 @@
|
|||
CONFIG_ARCH_PXA=y
|
||||
CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x100000
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_ARM_BOARD_APPEND_ATAG=y
|
||||
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
|
||||
CONFIG_ARM_UNWIND=y
|
||||
# CONFIG_BANNER is not set
|
||||
CONFIG_MMU=y
|
||||
CONFIG_TEXT_BASE=0xa3d00000
|
||||
CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0x80000
|
||||
CONFIG_MALLOC_SIZE=0x1000000
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_PROMPT="lubbock-barebox:"
|
||||
CONFIG_HUSH_FANCY_PROMPT=y
|
||||
CONFIG_CMDLINE_EDITING=y
|
||||
CONFIG_AUTO_COMPLETE=y
|
||||
CONFIG_MENU=y
|
||||
CONFIG_CONSOLE_ACTIVATE_ALL=y
|
||||
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
|
||||
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/lubbock/env"
|
||||
CONFIG_RESET_SOURCE=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_CMD_DMESG=y
|
||||
CONFIG_LONGHELP=y
|
||||
CONFIG_CMD_IOMEM=y
|
||||
CONFIG_CMD_MEMINFO=y
|
||||
CONFIG_CMD_BOOTM_SHOW_TYPE=y
|
||||
CONFIG_CMD_BOOTM_VERBOSE=y
|
||||
CONFIG_CMD_BOOTM_INITRD=y
|
||||
CONFIG_CMD_BOOTM_OFTREE=y
|
||||
CONFIG_CMD_GO=y
|
||||
CONFIG_CMD_LOADB=y
|
||||
CONFIG_CMD_LOADS=y
|
||||
CONFIG_CMD_LOADY=y
|
||||
CONFIG_CMD_RESET=y
|
||||
CONFIG_CMD_SAVES=y
|
||||
CONFIG_CMD_PARTITION=y
|
||||
CONFIG_CMD_UBIFORMAT=y
|
||||
CONFIG_CMD_EXPORT=y
|
||||
CONFIG_CMD_LOADENV=y
|
||||
CONFIG_CMD_PRINTENV=y
|
||||
CONFIG_CMD_SAVEENV=y
|
||||
CONFIG_CMD_FILETYPE=y
|
||||
CONFIG_CMD_LN=y
|
||||
CONFIG_CMD_UNCOMPRESS=y
|
||||
CONFIG_CMD_LET=y
|
||||
CONFIG_CMD_MSLEEP=y
|
||||
CONFIG_CMD_SLEEP=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_HOST=y
|
||||
CONFIG_CMD_MIITOOL=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_TFTP=y
|
||||
CONFIG_CMD_ECHO_E=y
|
||||
CONFIG_CMD_EDIT=y
|
||||
CONFIG_CMD_MENU=y
|
||||
CONFIG_CMD_MENU_MANAGEMENT=y
|
||||
CONFIG_CMD_SPLASH=y
|
||||
CONFIG_CMD_READLINE=y
|
||||
CONFIG_CMD_TIMEOUT=y
|
||||
CONFIG_CMD_CRC=y
|
||||
CONFIG_CMD_CRC_CMP=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_MM=y
|
||||
CONFIG_CMD_DETECT=y
|
||||
CONFIG_CMD_FLASH=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_LED=y
|
||||
CONFIG_CMD_POWEROFF=y
|
||||
CONFIG_CMD_LSMOD=y
|
||||
CONFIG_CMD_OF_NODE=y
|
||||
CONFIG_CMD_OF_PROPERTY=y
|
||||
CONFIG_CMD_OFTREE=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_NET_NETCONSOLE=y
|
||||
CONFIG_OFDEVICE=y
|
||||
CONFIG_OF_BAREBOX_DRIVERS=y
|
||||
CONFIG_DRIVER_SERIAL_PXA=y
|
||||
CONFIG_DRIVER_NET_SMC91111=y
|
||||
# CONFIG_SPI is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_DRIVER_CFI=y
|
||||
# CONFIG_DRIVER_CFI_AMD is not set
|
||||
CONFIG_CFI_BUFFER_WRITE=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MCI=y
|
||||
CONFIG_MCI_PXA=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
CONFIG_GENERIC_PHY=y
|
||||
CONFIG_FS_CRAMFS=y
|
||||
CONFIG_FS_EXT4=y
|
||||
CONFIG_FS_TFTP=y
|
||||
CONFIG_FS_FAT=y
|
||||
CONFIG_FS_FAT_WRITE=y
|
||||
CONFIG_FS_FAT_LFN=y
|
||||
CONFIG_FS_UBIFS=y
|
||||
CONFIG_FS_UBIFS_COMPRESSION_LZO=y
|
||||
CONFIG_FS_UBIFS_COMPRESSION_ZLIB=y
|
||||
CONFIG_BZLIB=y
|
||||
CONFIG_BMP=y
|
||||
CONFIG_PNG=y
|
||||
|
|
@ -1,5 +1,6 @@
|
|||
CONFIG_ARCH_PXA=y
|
||||
CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x100000
|
||||
CONFIG_ARCH_PXA27X=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_ARM_BOARD_APPEND_ATAG=y
|
||||
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARCH_PXA=y
|
||||
CONFIG_ARCH_PXA27X=y
|
||||
CONFIG_MACH_PCM027=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
|
||||
|
|
|
|||
|
|
@ -0,0 +1,117 @@
|
|||
CONFIG_ARCH_PXA=y
|
||||
CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x100000
|
||||
CONFIG_ARCH_PXA3XX=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_ARM_BOARD_APPEND_ATAG=y
|
||||
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
|
||||
CONFIG_ARM_UNWIND=y
|
||||
# CONFIG_BANNER is not set
|
||||
CONFIG_MMU=y
|
||||
CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0x80000
|
||||
CONFIG_MALLOC_SIZE=0x1000000
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_PROMPT="zylonite-barebox:"
|
||||
CONFIG_GLOB=y
|
||||
CONFIG_HUSH_FANCY_PROMPT=y
|
||||
CONFIG_CMDLINE_EDITING=y
|
||||
CONFIG_AUTO_COMPLETE=y
|
||||
CONFIG_MENU=y
|
||||
CONFIG_CONSOLE_ACTIVATE_ALL=y
|
||||
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/zylonite/env"
|
||||
CONFIG_RESET_SOURCE=y
|
||||
CONFIG_DEFAULT_LOGLEVEL=8
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_CMD_DMESG=y
|
||||
CONFIG_LONGHELP=y
|
||||
CONFIG_CMD_IOMEM=y
|
||||
CONFIG_CMD_MEMINFO=y
|
||||
CONFIG_FLEXIBLE_BOOTARGS=y
|
||||
CONFIG_CMD_BOOT=y
|
||||
CONFIG_CMD_BOOTM_SHOW_TYPE=y
|
||||
CONFIG_CMD_BOOTM_VERBOSE=y
|
||||
CONFIG_CMD_BOOTM_INITRD=y
|
||||
CONFIG_CMD_BOOTM_OFTREE=y
|
||||
CONFIG_CMD_GO=y
|
||||
CONFIG_CMD_LOADB=y
|
||||
CONFIG_CMD_LOADS=y
|
||||
CONFIG_CMD_LOADY=y
|
||||
CONFIG_CMD_RESET=y
|
||||
CONFIG_CMD_SAVES=y
|
||||
CONFIG_CMD_PARTITION=y
|
||||
CONFIG_CMD_AUTOMOUNT=y
|
||||
CONFIG_CMD_UBIFORMAT=y
|
||||
CONFIG_CMD_EXPORT=y
|
||||
CONFIG_CMD_GLOBAL=y
|
||||
CONFIG_CMD_LOADENV=y
|
||||
CONFIG_CMD_PRINTENV=y
|
||||
CONFIG_CMD_SAVEENV=y
|
||||
CONFIG_CMD_BASENAME=y
|
||||
CONFIG_CMD_CMP=y
|
||||
CONFIG_CMD_DIRNAME=y
|
||||
CONFIG_CMD_FILETYPE=y
|
||||
CONFIG_CMD_LN=y
|
||||
CONFIG_CMD_READLINK=y
|
||||
CONFIG_CMD_UNCOMPRESS=y
|
||||
CONFIG_CMD_LET=y
|
||||
CONFIG_CMD_MSLEEP=y
|
||||
CONFIG_CMD_SLEEP=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_HOST=y
|
||||
CONFIG_NET_CMD_IFUP=y
|
||||
CONFIG_CMD_MIITOOL=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_TFTP=y
|
||||
CONFIG_CMD_ECHO_E=y
|
||||
CONFIG_CMD_EDIT=y
|
||||
CONFIG_CMD_LOGIN=y
|
||||
CONFIG_CMD_MENU=y
|
||||
CONFIG_CMD_MENU_MANAGEMENT=y
|
||||
CONFIG_CMD_PASSWD=y
|
||||
CONFIG_CMD_SPLASH=y
|
||||
CONFIG_CMD_READLINE=y
|
||||
CONFIG_CMD_TIMEOUT=y
|
||||
CONFIG_CMD_CRC=y
|
||||
CONFIG_CMD_CRC_CMP=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_MM=y
|
||||
CONFIG_CMD_DETECT=y
|
||||
CONFIG_CMD_FLASH=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_POWEROFF=y
|
||||
CONFIG_CMD_2048=y
|
||||
CONFIG_CMD_LSMOD=y
|
||||
CONFIG_CMD_OF_NODE=y
|
||||
CONFIG_CMD_OF_PROPERTY=y
|
||||
CONFIG_CMD_OFTREE=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_NET_NETCONSOLE=y
|
||||
CONFIG_OFDEVICE=y
|
||||
CONFIG_OF_BAREBOX_DRIVERS=y
|
||||
CONFIG_DRIVER_SERIAL_PXA=y
|
||||
CONFIG_DRIVER_NET_SMC91111=y
|
||||
# CONFIG_SPI is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_NAND_MRVL_NFC=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MCI=y
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
CONFIG_PWM=y
|
||||
# CONFIG_PINCTRL is not set
|
||||
CONFIG_FS_CRAMFS=y
|
||||
CONFIG_FS_EXT4=y
|
||||
CONFIG_FS_TFTP=y
|
||||
CONFIG_FS_NFS=y
|
||||
CONFIG_FS_FAT=y
|
||||
CONFIG_FS_FAT_WRITE=y
|
||||
CONFIG_FS_FAT_LFN=y
|
||||
CONFIG_FS_UBIFS=y
|
||||
CONFIG_FS_UBIFS_COMPRESSION_LZO=y
|
||||
CONFIG_FS_UBIFS_COMPRESSION_ZLIB=y
|
||||
CONFIG_BZLIB=y
|
||||
CONFIG_BMP=y
|
||||
CONFIG_PNG=y
|
||||
CONFIG_SHA256=y
|
||||
|
|
@ -69,6 +69,12 @@ config CPU_V7
|
|||
bool
|
||||
select CPU_32v7
|
||||
|
||||
config CPU_XSC3
|
||||
bool
|
||||
select CPU_32v4T
|
||||
help
|
||||
Select code specific to PXA3xx variants
|
||||
|
||||
# Xscale PXA25x, PXA27x
|
||||
config CPU_XSCALE
|
||||
bool
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@ config ARCH_TEXT_BASE
|
|||
hex
|
||||
default 0xa0000000 if MACH_MIOA701
|
||||
default 0xa3f00000 if MACH_PCM027
|
||||
default 0x83f00000 if MACH_ZYLONITE
|
||||
|
||||
# ----------------------------------------------------------
|
||||
|
||||
|
|
@ -11,17 +12,48 @@ config ARCH_PXA2XX
|
|||
bool
|
||||
select CPU_XSCALE
|
||||
|
||||
config ARCH_PXA3XX
|
||||
bool
|
||||
select CPU_XSC3
|
||||
|
||||
config ARCH_PXA310
|
||||
bool
|
||||
|
||||
choice
|
||||
prompt "Intel/Marvell PXA Processor"
|
||||
|
||||
config ARCH_PXA25X
|
||||
bool "PXA25x"
|
||||
select ARCH_PXA2XX
|
||||
|
||||
config ARCH_PXA27X
|
||||
bool "PXA27x"
|
||||
select ARCH_PXA2XX
|
||||
|
||||
config ARCH_PXA3XX
|
||||
bool "PXA3xx"
|
||||
|
||||
endchoice
|
||||
|
||||
# ----------------------------------------------------------
|
||||
|
||||
if ARCH_PXA25X
|
||||
|
||||
choice
|
||||
prompt "PXA25x Board Type"
|
||||
bool
|
||||
|
||||
config MACH_LUBBOCK
|
||||
bool "Lubbock board"
|
||||
select PWM
|
||||
help
|
||||
Say Y here if you are using a Lubbock board
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
# ----------------------------------------------------------
|
||||
|
||||
if ARCH_PXA27X
|
||||
|
||||
choice
|
||||
|
|
@ -55,4 +87,26 @@ endif
|
|||
|
||||
# ----------------------------------------------------------
|
||||
|
||||
if ARCH_PXA3XX
|
||||
|
||||
config MACH_ZYLONITE
|
||||
bool
|
||||
|
||||
choice
|
||||
prompt "PXA3xx Board Type"
|
||||
|
||||
config MACH_ZYLONITE_PXA310
|
||||
bool "Zylonite board based on a PXA310 pxa SoC"
|
||||
help
|
||||
Say Y here if you are using a Zylonite board, based
|
||||
on a PXA31x SoC.
|
||||
select ARCH_PXA310
|
||||
select MACH_ZYLONITE
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
# ----------------------------------------------------------
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@ obj-y += gpio.o
|
|||
obj-y += devices.o
|
||||
obj-y += sleep.o
|
||||
|
||||
obj-$(CONFIG_ARCH_PXA2XX) += mfp-pxa2xx.o
|
||||
obj-$(CONFIG_ARCH_PXA2XX) += mfp-pxa2xx.o pxa2xx.o
|
||||
obj-$(CONFIG_ARCH_PXA25X) += speed-pxa25x.o
|
||||
obj-$(CONFIG_ARCH_PXA27X) += speed-pxa27x.o
|
||||
obj-$(CONFIG_RESET_SOURCE) += reset_source.o
|
||||
obj-$(CONFIG_ARCH_PXA3XX) += speed-pxa3xx.o mfp-pxa3xx.o pxa3xx.o
|
||||
|
|
|
|||
|
|
@ -27,12 +27,12 @@
|
|||
#define OWER_WME (1 << 0) /* Watch-dog Match Enable */
|
||||
#define OSSR_M3 (1 << 3) /* Match status channel 3 */
|
||||
|
||||
extern void pxa_suspend(int mode);
|
||||
extern void pxa_clear_reset_source(void);
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
/* Clear last reset source */
|
||||
RCSR = RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR;
|
||||
pxa_clear_reset_source();
|
||||
|
||||
/* Initialize the watchdog and let it fire */
|
||||
writel(OWER_WME, OWER);
|
||||
|
|
@ -41,14 +41,3 @@ void reset_cpu(ulong addr)
|
|||
|
||||
while (1);
|
||||
}
|
||||
|
||||
void __noreturn poweroff()
|
||||
{
|
||||
shutdown_barebox();
|
||||
|
||||
/* Clear last reset source */
|
||||
RCSR = RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR;
|
||||
|
||||
pxa_suspend(PWRMODE_DEEPSLEEP);
|
||||
unreachable();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
unsigned long pxa_get_uartclk(void);
|
||||
unsigned long pxa_get_mmcclk(void);
|
||||
unsigned long pxa_get_lcdclk(void);
|
||||
unsigned long pxa_get_nandclk(void);
|
||||
unsigned long pxa_get_pwmclk(void);
|
||||
|
||||
#endif /* !__MACH_CLOCK_H */
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
#ifdef CONFIG_ARCH_PXA2XX
|
||||
#define cpu_is_pxa2xx() (1)
|
||||
#else
|
||||
#define cpi_is_pxa2xx() (0)
|
||||
#define cpu_is_pxa2xx() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_PXA25X
|
||||
|
|
@ -28,6 +28,22 @@
|
|||
#define cpu_is_pxa27x() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_PXA3XX
|
||||
#define cpu_is_pxa3xx() (1)
|
||||
# ifdef CONFIG_ARCH_PXA320
|
||||
# define cpu_is_pxa320() (1)
|
||||
# else
|
||||
# define cpu_is_pxa320() (0)
|
||||
# endif
|
||||
# ifdef CONFIG_ARCH_PXA310
|
||||
# define cpu_is_pxa310() (1)
|
||||
# else
|
||||
# define cpu_is_pxa310() (0)
|
||||
# endif
|
||||
#else
|
||||
#define cpu_is_pxa3xx() (0)
|
||||
#endif
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
#define __REG(x) (x)
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,25 @@
|
|||
#ifndef __ASM_ARCH_MFP_PXA3XX_H
|
||||
#define __ASM_ARCH_MFP_PXA3XX_H
|
||||
|
||||
#include <plat/mfp.h>
|
||||
|
||||
#define MFPR_BASE (0x40e10000)
|
||||
|
||||
/* NOTE: usage of these two functions is not recommended,
|
||||
* use pxa3xx_mfp_config() instead.
|
||||
*/
|
||||
static inline unsigned long pxa3xx_mfp_read(int mfp)
|
||||
{
|
||||
return mfp_read(mfp);
|
||||
}
|
||||
|
||||
static inline void pxa3xx_mfp_write(int mfp, unsigned long val)
|
||||
{
|
||||
mfp_write(mfp, val);
|
||||
}
|
||||
|
||||
static inline void pxa3xx_mfp_config(unsigned long *mfp_cfg, int num)
|
||||
{
|
||||
mfp_config(mfp_cfg, num);
|
||||
}
|
||||
#endif /* __ASM_ARCH_MFP_PXA3XX_H */
|
||||
|
|
@ -24,8 +24,12 @@
|
|||
# include <mach/pxa2xx-regs.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_PXA27X
|
||||
#if defined(CONFIG_ARCH_PXA27X)
|
||||
# include <mach/pxa27x-regs.h>
|
||||
#elif defined(CONFIG_ARCH_PXA3XX)
|
||||
# include <mach/pxa3xx-regs.h>
|
||||
#elif defined(CONFIG_ARCH_PXA25X)
|
||||
# include <mach/pxa25x-regs.h>
|
||||
#else
|
||||
# error "unknown PXA soc type"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,6 @@
|
|||
#ifndef __MACH_PXA25X_REGS
|
||||
#define __MACH_PXA25X_REGS
|
||||
|
||||
/* this file intentionally left blank */
|
||||
|
||||
#endif /* !__MACH_PXA25X_REGS */
|
||||
|
|
@ -53,6 +53,7 @@
|
|||
#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
|
||||
#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
|
||||
#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
|
||||
#define FLYCNFG __REG(0x48000020) /* Flycnfg Register */
|
||||
#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
|
||||
#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
|
||||
#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,224 @@
|
|||
/*
|
||||
* arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
|
||||
*
|
||||
* PXA3xx specific register definitions
|
||||
*
|
||||
* Copyright (C) 2007 Marvell International Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_PXA3XX_REGS
|
||||
#define __MACH_PXA3XX_REGS
|
||||
|
||||
#include <mach/hardware.h>
|
||||
|
||||
/*
|
||||
* Oscillator Configuration Register (OSCC)
|
||||
*/
|
||||
#define OSCC __REG(0x41350000) /* Oscillator Configuration Register */
|
||||
|
||||
#define OSCC_PEN (1 << 11) /* 13MHz POUT */
|
||||
|
||||
|
||||
/*
|
||||
* Service Power Management Unit (MPMU)
|
||||
*/
|
||||
#define PMCR __REG(0x40F50000) /* Power Manager Control Register */
|
||||
#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */
|
||||
#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */
|
||||
#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */
|
||||
#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */
|
||||
#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */
|
||||
#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */
|
||||
#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */
|
||||
#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */
|
||||
#define PCMD(x) __REG(0x40F50110 + ((x) << 2))
|
||||
|
||||
/*
|
||||
* Slave Power Management Unit
|
||||
*/
|
||||
#define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */
|
||||
#define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */
|
||||
#define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */
|
||||
#define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */
|
||||
#define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */
|
||||
#define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */
|
||||
#define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */
|
||||
#define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */
|
||||
#define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */
|
||||
#define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */
|
||||
#define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */
|
||||
#define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */
|
||||
#define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */
|
||||
#define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */
|
||||
|
||||
/*
|
||||
* Application Subsystem Configuration bits.
|
||||
*/
|
||||
#define ASCR_RDH (1 << 31)
|
||||
#define ASCR_D1S (1 << 2)
|
||||
#define ASCR_D2S (1 << 1)
|
||||
#define ASCR_D3S (1 << 0)
|
||||
|
||||
/*
|
||||
* Application Reset Status bits.
|
||||
*/
|
||||
#define ARSR_GPR (1 << 3)
|
||||
#define ARSR_LPMR (1 << 2)
|
||||
#define ARSR_WDT (1 << 1)
|
||||
#define ARSR_HWR (1 << 0)
|
||||
|
||||
/*
|
||||
* Application Subsystem Wake-Up bits.
|
||||
*/
|
||||
#define ADXER_WRTC (1 << 31) /* RTC */
|
||||
#define ADXER_WOST (1 << 30) /* OS Timer */
|
||||
#define ADXER_WTSI (1 << 29) /* Touchscreen */
|
||||
#define ADXER_WUSBH (1 << 28) /* USB host */
|
||||
#define ADXER_WUSB2 (1 << 26) /* USB client 2.0 */
|
||||
#define ADXER_WMSL0 (1 << 24) /* MSL port 0*/
|
||||
#define ADXER_WDMUX3 (1 << 23) /* USB EDMUX3 */
|
||||
#define ADXER_WDMUX2 (1 << 22) /* USB EDMUX2 */
|
||||
#define ADXER_WKP (1 << 21) /* Keypad */
|
||||
#define ADXER_WUSIM1 (1 << 20) /* USIM Port 1 */
|
||||
#define ADXER_WUSIM0 (1 << 19) /* USIM Port 0 */
|
||||
#define ADXER_WOTG (1 << 16) /* USBOTG input */
|
||||
#define ADXER_MFP_WFLASH (1 << 15) /* MFP: Data flash busy */
|
||||
#define ADXER_MFP_GEN12 (1 << 14) /* MFP: MMC3/GPIO/OST inputs */
|
||||
#define ADXER_MFP_WMMC2 (1 << 13) /* MFP: MMC2 */
|
||||
#define ADXER_MFP_WMMC1 (1 << 12) /* MFP: MMC1 */
|
||||
#define ADXER_MFP_WI2C (1 << 11) /* MFP: I2C */
|
||||
#define ADXER_MFP_WSSP4 (1 << 10) /* MFP: SSP4 */
|
||||
#define ADXER_MFP_WSSP3 (1 << 9) /* MFP: SSP3 */
|
||||
#define ADXER_MFP_WMAXTRIX (1 << 8) /* MFP: matrix keypad */
|
||||
#define ADXER_MFP_WUART3 (1 << 7) /* MFP: UART3 */
|
||||
#define ADXER_MFP_WUART2 (1 << 6) /* MFP: UART2 */
|
||||
#define ADXER_MFP_WUART1 (1 << 5) /* MFP: UART1 */
|
||||
#define ADXER_MFP_WSSP2 (1 << 4) /* MFP: SSP2 */
|
||||
#define ADXER_MFP_WSSP1 (1 << 3) /* MFP: SSP1 */
|
||||
#define ADXER_MFP_WAC97 (1 << 2) /* MFP: AC97 */
|
||||
#define ADXER_WEXTWAKE1 (1 << 1) /* External Wake 1 */
|
||||
#define ADXER_WEXTWAKE0 (1 << 0) /* External Wake 0 */
|
||||
|
||||
/*
|
||||
* AD3R/AD2R/AD1R bits. R2-R5 are only defined for PXA320.
|
||||
*/
|
||||
#define ADXR_L2 (1 << 8)
|
||||
#define ADXR_R5 (1 << 5)
|
||||
#define ADXR_R4 (1 << 4)
|
||||
#define ADXR_R3 (1 << 3)
|
||||
#define ADXR_R2 (1 << 2)
|
||||
#define ADXR_R1 (1 << 1)
|
||||
#define ADXR_R0 (1 << 0)
|
||||
|
||||
/*
|
||||
* Values for PWRMODE CP15 register
|
||||
*/
|
||||
#define PXA3xx_PM_S3D4C4 0x07 /* aka deep sleep */
|
||||
#define PXA3xx_PM_S2D3C4 0x06 /* aka sleep */
|
||||
#define PXA3xx_PM_S0D2C2 0x03 /* aka standby */
|
||||
#define PXA3xx_PM_S0D1C2 0x02 /* aka LCD refresh */
|
||||
#define PXA3xx_PM_S0D0C1 0x01
|
||||
|
||||
/*
|
||||
* Application Subsystem Clock
|
||||
*/
|
||||
#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */
|
||||
#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */
|
||||
#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */
|
||||
#define CKENA __REG(0x4134000C) /* A Clock Enable Register */
|
||||
#define CKENB __REG(0x41340010) /* B Clock Enable Register */
|
||||
#define CKENC __REG(0x41340024) /* C Clock Enable Register */
|
||||
#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */
|
||||
|
||||
#define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */
|
||||
#define ACCR_SPDIS (1 << 30) /* System PLL Output Disable */
|
||||
#define ACCR_D0CS (1 << 26) /* D0 Mode Clock Select */
|
||||
#define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */
|
||||
#define ACCR_DDR_D0CS (1 << 7) /* DDR SDRAM clock frequency in D0CS (PXA31x only) */
|
||||
|
||||
#define ACCR_SMCFS_MASK (0x7 << 23) /* Static Memory Controller Frequency Select */
|
||||
#define ACCR_SFLFS_MASK (0x3 << 18) /* Frequency Select for Internal Memory Controller */
|
||||
#define ACCR_XSPCLK_MASK (0x3 << 16) /* Core Frequency during Frequency Change */
|
||||
#define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */
|
||||
#define ACCR_DMCFS_MASK (0x3 << 12) /* Dynamic Memory Controller Clock Frequency Select */
|
||||
#define ACCR_XN_MASK (0x7 << 8) /* Core PLL Turbo-Mode-to-Run-Mode Ratio */
|
||||
#define ACCR_XL_MASK (0x1f) /* Core PLL Run-Mode-to-Oscillator Ratio */
|
||||
|
||||
#define ACCR_SMCFS(x) (((x) & 0x7) << 23)
|
||||
#define ACCR_SFLFS(x) (((x) & 0x3) << 18)
|
||||
#define ACCR_XSPCLK(x) (((x) & 0x3) << 16)
|
||||
#define ACCR_HSS(x) (((x) & 0x3) << 14)
|
||||
#define ACCR_DMCFS(x) (((x) & 0x3) << 12)
|
||||
#define ACCR_XN(x) (((x) & 0x7) << 8)
|
||||
#define ACCR_XL(x) ((x) & 0x1f)
|
||||
|
||||
/*
|
||||
* Clock Enable Bit
|
||||
*/
|
||||
#define CKEN_LCD 1 /* < LCD Clock Enable */
|
||||
#define CKEN_USBH 2 /* < USB host clock enable */
|
||||
#define CKEN_CAMERA 3 /* < Camera interface clock enable */
|
||||
#define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */
|
||||
#define CKEN_USB2 6 /* < USB 2.0 client clock enable. */
|
||||
#define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */
|
||||
#define CKEN_SMC 9 /* < Static Memory Controller clock enable */
|
||||
#define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */
|
||||
#define CKEN_BOOT 11 /* < Boot rom clock enable */
|
||||
#define CKEN_MMC1 12 /* < MMC1 Clock enable */
|
||||
#define CKEN_MMC2 13 /* < MMC2 clock enable */
|
||||
#define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */
|
||||
#define CKEN_CIR 15 /* < Consumer IR Clock Enable */
|
||||
#define CKEN_USIM0 17 /* < USIM[0] Clock Enable */
|
||||
#define CKEN_USIM1 18 /* < USIM[1] Clock Enable */
|
||||
#define CKEN_TPM 19 /* < TPM clock enable */
|
||||
#define CKEN_UDC 20 /* < UDC clock enable */
|
||||
#define CKEN_BTUART 21 /* < BTUART clock enable */
|
||||
#define CKEN_FFUART 22 /* < FFUART clock enable */
|
||||
#define CKEN_STUART 23 /* < STUART clock enable */
|
||||
#define CKEN_AC97 24 /* < AC97 clock enable */
|
||||
#define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */
|
||||
#define CKEN_SSP1 26 /* < SSP1 clock enable */
|
||||
#define CKEN_SSP2 27 /* < SSP2 clock enable */
|
||||
#define CKEN_SSP3 28 /* < SSP3 clock enable */
|
||||
#define CKEN_SSP4 29 /* < SSP4 clock enable */
|
||||
#define CKEN_MSL0 30 /* < MSL0 clock enable */
|
||||
#define CKEN_PWM0 32 /* < PWM[0] clock enable */
|
||||
#define CKEN_PWM1 33 /* < PWM[1] clock enable */
|
||||
#define CKEN_I2C 36 /* < I2C clock enable */
|
||||
#define CKEN_INTC 38 /* < Interrupt controller clock enable */
|
||||
#define CKEN_GPIO 39 /* < GPIO clock enable */
|
||||
#define CKEN_1WIRE 40 /* < 1-wire clock enable */
|
||||
#define CKEN_HSIO2 41 /* < HSIO2 clock enable */
|
||||
#define CKEN_MINI_IM 48 /* < Mini-IM */
|
||||
#define CKEN_MINI_LCD 49 /* < Mini LCD */
|
||||
|
||||
#define CKEN_MMC3 5 /* < MMC3 Clock Enable */
|
||||
#define CKEN_MVED 43 /* < MVED clock enable */
|
||||
|
||||
/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
|
||||
#define CKEN_PXA300_GCU 42 /* Graphics controller clock enable */
|
||||
#define CKEN_PXA320_GCU 7 /* Graphics controller clock enable */
|
||||
|
||||
/*
|
||||
* Static Memory Controller
|
||||
*/
|
||||
#define MSC0 __REG(0x4a000008) /* Static Memory Control 0 */
|
||||
#define MSC1 __REG(0x4a00000c) /* Static Memory Control 1 */
|
||||
#define MECR __REG(0x4a000014) /* Expansion Memory Configuration */
|
||||
#define SXCNFG __REG(0x4a00001c) /* Synchronous Static Memory Control */
|
||||
#define MCMEM0 __REG(0x4a000028) /* Expansion Memory Timing */
|
||||
#define MCATT0 __REG(0x4a000030) /* Expansion Memory Timing */
|
||||
#define MCIO0 __REG(0x4a000038) /* Expansion Memory Timing */
|
||||
#define MEMCLKCFG __REG(0x4a000068) /* Clock configuration */
|
||||
#define CSADRCFG0 __REG(0x4a000080) /* CS0 address configuration */
|
||||
#define CSADRCFG1 __REG(0x4a000084) /* CS1 address configuration */
|
||||
#define CSADRCFG2 __REG(0x4a000088) /* CS2 address configuration */
|
||||
#define CSADRCFG3 __REG(0x4a00008c) /* CS3 address configuration */
|
||||
#define CSADRCFGP __REG(0x4a000090) /* CSP address configuration */
|
||||
#define CSMSADRCFG __REG(0x4a0000a0) /* CSP address configuration */
|
||||
|
||||
#endif /* !__MACH_PXA3XX_REGS */
|
||||
|
|
@ -416,7 +416,7 @@ typedef unsigned long mfp_cfg_t;
|
|||
((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
|
||||
(MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
|
||||
|
||||
#if defined(CONFIG_PXA3xx) || defined(CONFIG_ARCH_MMP)
|
||||
#if defined(CONFIG_ARCH_PXA3XX)
|
||||
/*
|
||||
* each MFP pin will have a MFPR register, since the offset of the
|
||||
* register varies between processors, the processor specific code
|
||||
|
|
@ -449,7 +449,7 @@ struct mfp_addr_map {
|
|||
|
||||
#define MFP_ADDR_END { MFP_PIN_INVALID, 0 }
|
||||
|
||||
void __init mfp_init_base(unsigned long mfpr_base);
|
||||
void __init mfp_init_base(void __iomem *mfpr_base);
|
||||
void __init mfp_init_addr(struct mfp_addr_map *map);
|
||||
|
||||
/*
|
||||
|
|
@ -463,6 +463,7 @@ void mfp_write(int mfp, unsigned long mfpr_val);
|
|||
void mfp_config(unsigned long *mfp_cfgs, int num);
|
||||
void mfp_config_run(void);
|
||||
void mfp_config_lpm(void);
|
||||
#endif /* CONFIG_PXA3xx || CONFIG_ARCH_MMP */
|
||||
void mfp_init(void);
|
||||
#endif /* CONFIG_ARCH_PXA3XX */
|
||||
|
||||
#endif /* __ASM_PLAT_MFP_H */
|
||||
|
|
|
|||
|
|
@ -169,8 +169,10 @@ static int __init pxa2xx_mfp_init(void)
|
|||
if (!cpu_is_pxa2xx())
|
||||
return 0;
|
||||
|
||||
if (cpu_is_pxa25x())
|
||||
if (cpu_is_pxa25x()) {
|
||||
pxa_init_gpio(0, 84);
|
||||
pxa25x_mfp_init();
|
||||
}
|
||||
|
||||
if (cpu_is_pxa27x()) {
|
||||
pxa_init_gpio(2, 120);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,338 @@
|
|||
/*
|
||||
* linux/arch/arm/plat-pxa/mfp.c
|
||||
*
|
||||
* Multi-Function Pin Support
|
||||
*
|
||||
* Copyright (C) 2007 Marvell Internation Ltd.
|
||||
*
|
||||
* 2007-08-21: eric miao <eric.miao@marvell.com>
|
||||
* initial version
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <io.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/mfp-pxa3xx.h>
|
||||
#include <plat/mfp.h>
|
||||
|
||||
#define MFPR_SIZE (PAGE_SIZE)
|
||||
|
||||
/* MFPR register bit definitions */
|
||||
#define MFPR_PULL_SEL (0x1 << 15)
|
||||
#define MFPR_PULLUP_EN (0x1 << 14)
|
||||
#define MFPR_PULLDOWN_EN (0x1 << 13)
|
||||
#define MFPR_SLEEP_SEL (0x1 << 9)
|
||||
#define MFPR_SLEEP_OE_N (0x1 << 7)
|
||||
#define MFPR_EDGE_CLEAR (0x1 << 6)
|
||||
#define MFPR_EDGE_FALL_EN (0x1 << 5)
|
||||
#define MFPR_EDGE_RISE_EN (0x1 << 4)
|
||||
|
||||
#define MFPR_SLEEP_DATA(x) ((x) << 8)
|
||||
#define MFPR_DRIVE(x) (((x) & 0x7) << 10)
|
||||
#define MFPR_AF_SEL(x) (((x) & 0x7) << 0)
|
||||
|
||||
#define MFPR_EDGE_NONE (0)
|
||||
#define MFPR_EDGE_RISE (MFPR_EDGE_RISE_EN)
|
||||
#define MFPR_EDGE_FALL (MFPR_EDGE_FALL_EN)
|
||||
#define MFPR_EDGE_BOTH (MFPR_EDGE_RISE | MFPR_EDGE_FALL)
|
||||
|
||||
/*
|
||||
* Table that determines the low power modes outputs, with actual settings
|
||||
* used in parentheses for don't-care values. Except for the float output,
|
||||
* the configured driven and pulled levels match, so if there is a need for
|
||||
* non-LPM pulled output, the same configuration could probably be used.
|
||||
*
|
||||
* Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel
|
||||
* (bit 7) (bit 8) (bit 14) (bit 13) (bit 15)
|
||||
*
|
||||
* Input 0 X(0) X(0) X(0) 0
|
||||
* Drive 0 0 0 0 X(1) 0
|
||||
* Drive 1 0 1 X(1) 0 0
|
||||
* Pull hi (1) 1 X(1) 1 0 0
|
||||
* Pull lo (0) 1 X(0) 0 1 0
|
||||
* Z (float) 1 X(0) 0 0 0
|
||||
*/
|
||||
#define MFPR_LPM_INPUT (0)
|
||||
#define MFPR_LPM_DRIVE_LOW (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN)
|
||||
#define MFPR_LPM_DRIVE_HIGH (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN)
|
||||
#define MFPR_LPM_PULL_LOW (MFPR_LPM_DRIVE_LOW | MFPR_SLEEP_OE_N)
|
||||
#define MFPR_LPM_PULL_HIGH (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N)
|
||||
#define MFPR_LPM_FLOAT (MFPR_SLEEP_OE_N)
|
||||
#define MFPR_LPM_MASK (0xe080)
|
||||
|
||||
/*
|
||||
* The pullup and pulldown state of the MFP pin at run mode is by default
|
||||
* determined by the selected alternate function. In case that some buggy
|
||||
* devices need to override this default behavior, the definitions below
|
||||
* indicates the setting of corresponding MFPR bits
|
||||
*
|
||||
* Definition pull_sel pullup_en pulldown_en
|
||||
* MFPR_PULL_NONE 0 0 0
|
||||
* MFPR_PULL_LOW 1 0 1
|
||||
* MFPR_PULL_HIGH 1 1 0
|
||||
* MFPR_PULL_BOTH 1 1 1
|
||||
* MFPR_PULL_FLOAT 1 0 0
|
||||
*/
|
||||
#define MFPR_PULL_NONE (0)
|
||||
#define MFPR_PULL_LOW (MFPR_PULL_SEL | MFPR_PULLDOWN_EN)
|
||||
#define MFPR_PULL_BOTH (MFPR_PULL_LOW | MFPR_PULLUP_EN)
|
||||
#define MFPR_PULL_HIGH (MFPR_PULL_SEL | MFPR_PULLUP_EN)
|
||||
#define MFPR_PULL_FLOAT (MFPR_PULL_SEL)
|
||||
|
||||
/* mfp_spin_lock is used to ensure that MFP register configuration
|
||||
* (most likely a read-modify-write operation) is atomic, and that
|
||||
* mfp_table[] is consistent
|
||||
*/
|
||||
static void __iomem *mfpr_mmio_base;
|
||||
|
||||
struct mfp_pin {
|
||||
unsigned long config; /* -1 for not configured */
|
||||
unsigned long mfpr_off; /* MFPRxx Register offset */
|
||||
unsigned long mfpr_run; /* Run-Mode Register Value */
|
||||
unsigned long mfpr_lpm; /* Low Power Mode Register Value */
|
||||
};
|
||||
|
||||
static struct mfp_pin mfp_table[MFP_PIN_MAX];
|
||||
|
||||
/* mapping of MFP_LPM_* definitions to MFPR_LPM_* register bits */
|
||||
static const unsigned long mfpr_lpm[] = {
|
||||
MFPR_LPM_INPUT,
|
||||
MFPR_LPM_DRIVE_LOW,
|
||||
MFPR_LPM_DRIVE_HIGH,
|
||||
MFPR_LPM_PULL_LOW,
|
||||
MFPR_LPM_PULL_HIGH,
|
||||
MFPR_LPM_FLOAT,
|
||||
MFPR_LPM_INPUT,
|
||||
};
|
||||
|
||||
/* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */
|
||||
static const unsigned long mfpr_pull[] = {
|
||||
MFPR_PULL_NONE,
|
||||
MFPR_PULL_LOW,
|
||||
MFPR_PULL_HIGH,
|
||||
MFPR_PULL_BOTH,
|
||||
MFPR_PULL_FLOAT,
|
||||
};
|
||||
|
||||
/* mapping of MFP_LPM_EDGE_* definitions to MFPR_EDGE_* register bits */
|
||||
static const unsigned long mfpr_edge[] = {
|
||||
MFPR_EDGE_NONE,
|
||||
MFPR_EDGE_RISE,
|
||||
MFPR_EDGE_FALL,
|
||||
MFPR_EDGE_BOTH,
|
||||
};
|
||||
|
||||
#define mfpr_readl(off) \
|
||||
__raw_readl(mfpr_mmio_base + (off))
|
||||
|
||||
#define mfpr_writel(off, val) \
|
||||
__raw_writel(val, mfpr_mmio_base + (off))
|
||||
|
||||
#define mfp_configured(p) ((p)->config != -1)
|
||||
|
||||
/*
|
||||
* perform a read-back of any valid MFPR register to make sure the
|
||||
* previous writings are finished
|
||||
*/
|
||||
static unsigned long mfpr_off_readback;
|
||||
#define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + mfpr_off_readback)
|
||||
|
||||
static inline void __mfp_config_run(struct mfp_pin *p)
|
||||
{
|
||||
if (mfp_configured(p))
|
||||
mfpr_writel(p->mfpr_off, p->mfpr_run);
|
||||
}
|
||||
|
||||
static inline void __mfp_config_lpm(struct mfp_pin *p)
|
||||
{
|
||||
if (mfp_configured(p)) {
|
||||
unsigned long mfpr_clr =
|
||||
(p->mfpr_run & ~MFPR_EDGE_BOTH) | MFPR_EDGE_CLEAR;
|
||||
|
||||
if (mfpr_clr != p->mfpr_run)
|
||||
mfpr_writel(p->mfpr_off, mfpr_clr);
|
||||
if (p->mfpr_lpm != mfpr_clr)
|
||||
mfpr_writel(p->mfpr_off, p->mfpr_lpm);
|
||||
}
|
||||
}
|
||||
|
||||
void mfp_config(unsigned long *mfp_cfgs, int num)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < num; i++, mfp_cfgs++) {
|
||||
unsigned long tmp, c = *mfp_cfgs;
|
||||
struct mfp_pin *p;
|
||||
int pin, af, drv, lpm, edge, pull;
|
||||
|
||||
pin = MFP_PIN(c);
|
||||
BUG_ON(pin >= MFP_PIN_MAX);
|
||||
p = &mfp_table[pin];
|
||||
|
||||
af = MFP_AF(c);
|
||||
drv = MFP_DS(c);
|
||||
lpm = MFP_LPM_STATE(c);
|
||||
edge = MFP_LPM_EDGE(c);
|
||||
pull = MFP_PULL(c);
|
||||
|
||||
/* run-mode pull settings will conflict with MFPR bits of
|
||||
* low power mode state, calculate mfpr_run and mfpr_lpm
|
||||
* individually if pull != MFP_PULL_NONE
|
||||
*/
|
||||
tmp = MFPR_AF_SEL(af) | MFPR_DRIVE(drv);
|
||||
|
||||
if (likely(pull == MFP_PULL_NONE)) {
|
||||
p->mfpr_run = tmp | mfpr_lpm[lpm] | mfpr_edge[edge];
|
||||
p->mfpr_lpm = p->mfpr_run;
|
||||
} else {
|
||||
p->mfpr_lpm = tmp | mfpr_lpm[lpm] | mfpr_edge[edge];
|
||||
p->mfpr_run = tmp | mfpr_pull[pull];
|
||||
}
|
||||
|
||||
p->config = c; __mfp_config_run(p);
|
||||
}
|
||||
|
||||
mfpr_sync();
|
||||
}
|
||||
|
||||
unsigned long mfp_read(int mfp)
|
||||
{
|
||||
unsigned long val;
|
||||
|
||||
BUG_ON(mfp < 0 || mfp >= MFP_PIN_MAX);
|
||||
|
||||
val = mfpr_readl(mfp_table[mfp].mfpr_off);
|
||||
return val;
|
||||
}
|
||||
|
||||
void mfp_write(int mfp, unsigned long val)
|
||||
{
|
||||
BUG_ON(mfp < 0 || mfp >= MFP_PIN_MAX);
|
||||
|
||||
mfpr_writel(mfp_table[mfp].mfpr_off, val);
|
||||
mfpr_sync();
|
||||
}
|
||||
|
||||
void __init mfp_init_base(void __iomem *mfpr_base)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* initialize the table with default - unconfigured */
|
||||
for (i = 0; i < ARRAY_SIZE(mfp_table); i++)
|
||||
mfp_table[i].config = -1;
|
||||
|
||||
mfpr_mmio_base = mfpr_base;
|
||||
}
|
||||
|
||||
void __init mfp_init_addr(struct mfp_addr_map *map)
|
||||
{
|
||||
struct mfp_addr_map *p;
|
||||
unsigned long offset;
|
||||
int i;
|
||||
|
||||
/* mfp offset for readback */
|
||||
mfpr_off_readback = map[0].offset;
|
||||
|
||||
for (p = map; p->start != MFP_PIN_INVALID; p++) {
|
||||
offset = p->offset;
|
||||
i = p->start;
|
||||
|
||||
do {
|
||||
mfp_table[i].mfpr_off = offset;
|
||||
mfp_table[i].mfpr_run = 0;
|
||||
mfp_table[i].mfpr_lpm = 0;
|
||||
offset += 4; i++;
|
||||
} while ((i <= p->end) && (p->end != -1));
|
||||
}
|
||||
}
|
||||
|
||||
void mfp_config_lpm(void)
|
||||
{
|
||||
struct mfp_pin *p = &mfp_table[0];
|
||||
int pin;
|
||||
|
||||
for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++)
|
||||
__mfp_config_lpm(p);
|
||||
}
|
||||
|
||||
void mfp_config_run(void)
|
||||
{
|
||||
struct mfp_pin *p = &mfp_table[0];
|
||||
int pin;
|
||||
|
||||
for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++)
|
||||
__mfp_config_run(p);
|
||||
}
|
||||
|
||||
static struct mfp_addr_map pxa300_mfp_addr_map[] __initdata = {
|
||||
|
||||
MFP_ADDR_X(GPIO0, GPIO2, 0x00b4),
|
||||
MFP_ADDR_X(GPIO3, GPIO26, 0x027c),
|
||||
MFP_ADDR_X(GPIO27, GPIO98, 0x0400),
|
||||
MFP_ADDR_X(GPIO99, GPIO127, 0x0600),
|
||||
MFP_ADDR_X(GPIO0_2, GPIO1_2, 0x0674),
|
||||
MFP_ADDR_X(GPIO2_2, GPIO6_2, 0x02dc),
|
||||
|
||||
MFP_ADDR(nBE0, 0x0204),
|
||||
MFP_ADDR(nBE1, 0x0208),
|
||||
|
||||
MFP_ADDR(nLUA, 0x0244),
|
||||
MFP_ADDR(nLLA, 0x0254),
|
||||
|
||||
MFP_ADDR(DF_CLE_nOE, 0x0240),
|
||||
MFP_ADDR(DF_nRE_nOE, 0x0200),
|
||||
MFP_ADDR(DF_ALE_nWE, 0x020C),
|
||||
MFP_ADDR(DF_INT_RnB, 0x00C8),
|
||||
MFP_ADDR(DF_nCS0, 0x0248),
|
||||
MFP_ADDR(DF_nCS1, 0x0278),
|
||||
MFP_ADDR(DF_nWE, 0x00CC),
|
||||
|
||||
MFP_ADDR(DF_ADDR0, 0x0210),
|
||||
MFP_ADDR(DF_ADDR1, 0x0214),
|
||||
MFP_ADDR(DF_ADDR2, 0x0218),
|
||||
MFP_ADDR(DF_ADDR3, 0x021C),
|
||||
|
||||
MFP_ADDR(DF_IO0, 0x0220),
|
||||
MFP_ADDR(DF_IO1, 0x0228),
|
||||
MFP_ADDR(DF_IO2, 0x0230),
|
||||
MFP_ADDR(DF_IO3, 0x0238),
|
||||
MFP_ADDR(DF_IO4, 0x0258),
|
||||
MFP_ADDR(DF_IO5, 0x0260),
|
||||
MFP_ADDR(DF_IO6, 0x0268),
|
||||
MFP_ADDR(DF_IO7, 0x0270),
|
||||
MFP_ADDR(DF_IO8, 0x0224),
|
||||
MFP_ADDR(DF_IO9, 0x022C),
|
||||
MFP_ADDR(DF_IO10, 0x0234),
|
||||
MFP_ADDR(DF_IO11, 0x023C),
|
||||
MFP_ADDR(DF_IO12, 0x025C),
|
||||
MFP_ADDR(DF_IO13, 0x0264),
|
||||
MFP_ADDR(DF_IO14, 0x026C),
|
||||
MFP_ADDR(DF_IO15, 0x0274),
|
||||
|
||||
MFP_ADDR_END,
|
||||
};
|
||||
|
||||
/* override pxa300 MFP register addresses */
|
||||
static struct mfp_addr_map pxa310_mfp_addr_map[] __initdata = {
|
||||
MFP_ADDR_X(GPIO30, GPIO98, 0x0418),
|
||||
MFP_ADDR_X(GPIO7_2, GPIO12_2, 0x052C),
|
||||
|
||||
MFP_ADDR(ULPI_STP, 0x040C),
|
||||
MFP_ADDR(ULPI_NXT, 0x0410),
|
||||
MFP_ADDR(ULPI_DIR, 0x0414),
|
||||
|
||||
MFP_ADDR_END,
|
||||
};
|
||||
|
||||
void mfp_init(void)
|
||||
{
|
||||
mfp_init_base((void __iomem *)MFPR_BASE);
|
||||
mfp_init_addr(pxa300_mfp_addr_map);
|
||||
if (cpu_is_pxa310())
|
||||
mfp_init_addr(pxa310_mfp_addr_map);
|
||||
}
|
||||
|
|
@ -15,8 +15,11 @@
|
|||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <reset_source.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/pxa-regs.h>
|
||||
|
||||
extern void pxa_suspend(int mode);
|
||||
|
||||
static int pxa_detect_reset_source(void)
|
||||
{
|
||||
u32 reg = RCSR;
|
||||
|
|
@ -38,4 +41,19 @@ static int pxa_detect_reset_source(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void pxa_clear_reset_source(void)
|
||||
{
|
||||
RCSR = RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR;
|
||||
}
|
||||
|
||||
device_initcall(pxa_detect_reset_source);
|
||||
|
||||
void __noreturn poweroff(void)
|
||||
{
|
||||
shutdown_barebox();
|
||||
|
||||
/* Clear last reset source */
|
||||
pxa_clear_reset_source();
|
||||
pxa_suspend(PWRMODE_DEEPSLEEP);
|
||||
unreachable();
|
||||
}
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* (C) Copyright 2015 Robert Jarzmik <robert.jarzmik@free.fr>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <reset_source.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/pxa-regs.h>
|
||||
|
||||
extern void pxa3xx_suspend(int mode);
|
||||
|
||||
static int pxa_detect_reset_source(void)
|
||||
{
|
||||
u32 reg = ARSR;
|
||||
|
||||
/*
|
||||
* Order is important, as many bits can be set together
|
||||
*/
|
||||
if (reg & ARSR_GPR)
|
||||
reset_source_set(RESET_RST);
|
||||
else if (reg & ARSR_WDT)
|
||||
reset_source_set(RESET_WDG);
|
||||
else if (reg & ARSR_HWR)
|
||||
reset_source_set(RESET_POR);
|
||||
else if (reg & ARSR_LPMR)
|
||||
reset_source_set(RESET_WKE);
|
||||
else
|
||||
reset_source_set(RESET_UKWN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void pxa_clear_reset_source(void)
|
||||
{
|
||||
ARSR = ARSR_GPR | ARSR_LPMR | ARSR_WDT | ARSR_HWR;
|
||||
}
|
||||
|
||||
device_initcall(pxa_detect_reset_source);
|
||||
|
||||
void __noreturn poweroff(void)
|
||||
{
|
||||
shutdown_barebox();
|
||||
|
||||
/* Clear last reset source */
|
||||
pxa_clear_reset_source();
|
||||
pxa3xx_suspend(PXA3xx_PM_S3D4C4);
|
||||
unreachable();
|
||||
}
|
||||
|
|
@ -21,7 +21,7 @@
|
|||
#define UNCACHED_PHYS_0 0
|
||||
.text
|
||||
|
||||
#ifdef CONFIG_ARCH_PXA27X
|
||||
#if (defined CONFIG_ARCH_PXA27X || defined CONFIG_ARCH_PXA25X)
|
||||
/*
|
||||
* pxa27x_finish_suspend()
|
||||
*
|
||||
|
|
@ -79,3 +79,10 @@ pxa_cpu_do_suspend:
|
|||
@ enter sleep mode
|
||||
mcr p14, 0, r1, c7, c0, 0 @ PWRMODE
|
||||
20: b 20b @ loop waiting for sleep
|
||||
|
||||
/*
|
||||
* pxa3xx_finish_suspend() - forces CPU into sleep state
|
||||
*/
|
||||
ENTRY(pxa3xx_suspend)
|
||||
mcr p14, 0, r0, c7, c0, 0 @ enter sleep
|
||||
20: b 20b @ waiting for sleep
|
||||
|
|
|
|||
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* clock.h - implementation of the PXA clock functions
|
||||
*
|
||||
* Copyright (C) 2014 Robert Jarzmik <robert.jarzmik@free.fr>
|
||||
*
|
||||
* This file is released under the GPLv2
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mach/clock.h>
|
||||
#include <mach/pxa-regs.h>
|
||||
|
||||
/* Crystal clock: 13MHz */
|
||||
#define BASE_CLK 13000000
|
||||
|
||||
unsigned long pxa_get_uartclk(void)
|
||||
{
|
||||
return 14857000;
|
||||
}
|
||||
|
||||
unsigned long pxa_get_mmcclk(void)
|
||||
{
|
||||
return 19500000;
|
||||
}
|
||||
|
||||
/*
|
||||
* Return the current LCD clock frequency in units of 10kHz as
|
||||
*/
|
||||
static unsigned int pxa_get_lcdclk_10khz(void)
|
||||
{
|
||||
unsigned long ccsr;
|
||||
unsigned int l, L, k, K;
|
||||
|
||||
ccsr = CCSR;
|
||||
|
||||
l = ccsr & 0x1f;
|
||||
k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
|
||||
|
||||
L = l * BASE_CLK;
|
||||
K = L / k;
|
||||
|
||||
return (K / 10000);
|
||||
}
|
||||
|
||||
unsigned long pxa_get_lcdclk(void)
|
||||
{
|
||||
return pxa_get_lcdclk_10khz() * 10000;
|
||||
}
|
||||
|
||||
unsigned long pxa_get_pwmclk(void)
|
||||
{
|
||||
return BASE_CLK;
|
||||
}
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* clock.h - implementation of the PXA clock functions
|
||||
*
|
||||
* Copyright (C) 2014 by Robert Jarzmik <robert.jarzmik@free.fr>
|
||||
*
|
||||
* This file is released under the GPLv2
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mach/clock.h>
|
||||
#include <mach/pxa-regs.h>
|
||||
|
||||
/* Crystal clock: 13MHz */
|
||||
#define BASE_CLK 13000000
|
||||
|
||||
unsigned long pxa_get_uartclk(void)
|
||||
{
|
||||
return 14857000;
|
||||
}
|
||||
|
||||
unsigned long pxa_get_pwmclk(void)
|
||||
{
|
||||
return BASE_CLK;
|
||||
}
|
||||
|
||||
unsigned long pxa_get_nandclk(void)
|
||||
{
|
||||
if (cpu_is_pxa320())
|
||||
return 104000000;
|
||||
else
|
||||
return 156000000;
|
||||
}
|
||||
|
|
@ -97,6 +97,13 @@ config NAND_ORION
|
|||
help
|
||||
Support for the Orion NAND controller, present in Kirkwood SoCs.
|
||||
|
||||
config NAND_MRVL_NFC
|
||||
bool
|
||||
prompt "Marvell NAND driver"
|
||||
depends on ARCH_PXA3XX
|
||||
help
|
||||
Support for the PXA3xx NAND controller, present in pxa3xx SoCs.
|
||||
|
||||
config NAND_ATMEL
|
||||
bool
|
||||
prompt "Atmel (AT91SAM9xxx) NAND driver"
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@ obj-$(CONFIG_NAND_IMX) += nand_imx.o
|
|||
obj-$(CONFIG_NAND_IMX_BBM) += nand_imx_bbm.o
|
||||
obj-$(CONFIG_NAND_OMAP_GPMC) += nand_omap_gpmc.o nand_omap_bch_decoder.o
|
||||
obj-$(CONFIG_NAND_ORION) += nand_orion.o
|
||||
obj-$(CONFIG_NAND_MRVL_NFC) += nand_mrvl_nfc.o
|
||||
obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
|
||||
obj-$(CONFIG_NAND_S3C24XX) += nand_s3c24xx.o
|
||||
pbl-$(CONFIG_NAND_S3C24XX) += nand_s3c24xx.o
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -435,14 +435,14 @@
|
|||
#define MEMORY_WAIT_TIME 16
|
||||
|
||||
struct accessors {
|
||||
void (*ob)(unsigned, void __iomem *);
|
||||
void (*ow)(unsigned, void __iomem *);
|
||||
void (*ol)(unsigned long, void __iomem *);
|
||||
void (*osl)(void __iomem *, const void *, int);
|
||||
unsigned (*ib)(void __iomem *);
|
||||
unsigned (*iw)(void __iomem *);
|
||||
unsigned long (*il)(void __iomem *);
|
||||
void (*isl)(void __iomem *, void*, int);
|
||||
void (*ob)(unsigned, void __iomem *, unsigned, unsigned);
|
||||
void (*ow)(unsigned, void __iomem *, unsigned, unsigned);
|
||||
void (*ol)(unsigned long, void __iomem *, unsigned, unsigned);
|
||||
void (*osl)(void __iomem *, unsigned, const void *, int, unsigned);
|
||||
unsigned (*ib)(void __iomem *, unsigned, unsigned);
|
||||
unsigned (*iw)(void __iomem *, unsigned, unsigned);
|
||||
unsigned long (*il)(void __iomem *, unsigned, unsigned);
|
||||
void (*isl)(void __iomem *, unsigned, void*, int, unsigned);
|
||||
};
|
||||
|
||||
struct smc91c111_priv {
|
||||
|
|
@ -450,6 +450,11 @@ struct smc91c111_priv {
|
|||
struct accessors a;
|
||||
void __iomem *base;
|
||||
int qemu_fixup;
|
||||
unsigned shift;
|
||||
int version;
|
||||
int revision;
|
||||
unsigned int control_setup;
|
||||
unsigned int config_setup;
|
||||
};
|
||||
|
||||
#if (SMC_DEBUG > 2 )
|
||||
|
|
@ -479,109 +484,176 @@ struct smc91c111_priv {
|
|||
|
||||
#define ETH_ZLEN 60
|
||||
|
||||
static void a_outb(unsigned value, void __iomem *offset)
|
||||
static void a8_outb(unsigned value, void __iomem *base, unsigned int offset,
|
||||
unsigned shift)
|
||||
{
|
||||
writeb(value, offset);
|
||||
writeb(value, base + (offset << shift));
|
||||
}
|
||||
|
||||
static void a_outw(unsigned value, void __iomem *offset)
|
||||
static void a16_outw(unsigned value, void __iomem *base, unsigned int offset,
|
||||
unsigned shift)
|
||||
{
|
||||
writew(value, offset);
|
||||
writew(value, base + (offset << shift));
|
||||
}
|
||||
|
||||
static void a_outl(unsigned long value, void __iomem *offset)
|
||||
static void a32_outl(unsigned long value, void __iomem *base,
|
||||
unsigned int offset, unsigned shift)
|
||||
{
|
||||
writel(value, offset);
|
||||
writel(value, base + (offset << shift));
|
||||
}
|
||||
|
||||
static void a_outsl(void __iomem *offset, const void *data, int count)
|
||||
static void a16_outsl(void __iomem *base, unsigned int offset,
|
||||
const void *data, int count, unsigned shift)
|
||||
{
|
||||
writesl(offset, data, count);
|
||||
writesw(base + (offset << shift), data, count * 2);
|
||||
}
|
||||
|
||||
static unsigned a_inb(void __iomem *offset)
|
||||
static void a16_outl(unsigned long value, void __iomem *base,
|
||||
unsigned int offset, unsigned shift)
|
||||
{
|
||||
return readb(offset);
|
||||
writew(value & 0xffff, base + (offset << shift));
|
||||
writew(value >> 16, base + ((offset + 2) << shift));
|
||||
}
|
||||
|
||||
static unsigned a_inw(void __iomem *offset)
|
||||
static void a32_outsl(void __iomem *base, unsigned int offset,
|
||||
const void *data, int count, unsigned shift)
|
||||
{
|
||||
return readw(offset);
|
||||
writesw(base + (offset << shift), data, count * 2);
|
||||
}
|
||||
|
||||
static unsigned long a_inl(void __iomem *offset)
|
||||
static unsigned a8_inb(void __iomem *base, unsigned int offset, unsigned shift)
|
||||
{
|
||||
return readl(offset);
|
||||
return readb(base + (offset << shift));
|
||||
}
|
||||
|
||||
static inline void a_insl(void __iomem *offset, void *data, int count)
|
||||
static unsigned a16_inw(void __iomem *base, unsigned int offset, unsigned shift)
|
||||
{
|
||||
readsl(offset, data, count);
|
||||
return readw(base + (offset << shift));
|
||||
}
|
||||
|
||||
static unsigned long a16_inl(void __iomem *base, unsigned int offset,
|
||||
unsigned shift)
|
||||
{
|
||||
u32 value;
|
||||
|
||||
value = readw(base + (offset << shift));
|
||||
value |= readw(base + (offset << shift)) << 16;
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static inline void a16_insl(void __iomem *base, unsigned int offset, void *data,
|
||||
int count, unsigned shift)
|
||||
{
|
||||
readsw(base + (offset << shift), data, count * 2);
|
||||
}
|
||||
|
||||
static unsigned long a32_inl(void __iomem *base, unsigned int offset,
|
||||
unsigned shift)
|
||||
{
|
||||
return readl(base + (offset << shift));
|
||||
}
|
||||
|
||||
static inline void a32_insl(void __iomem *base, unsigned int offset, void *data,
|
||||
int count, unsigned shift)
|
||||
{
|
||||
readsl(base + (offset << shift), data, count);
|
||||
}
|
||||
|
||||
static const struct accessors access_via_16bit = {
|
||||
.ob = a8_outb,
|
||||
.ow = a16_outw,
|
||||
.ol = a16_outl,
|
||||
.osl = a16_outsl,
|
||||
.ib = a8_inb,
|
||||
.iw = a16_inw,
|
||||
.il = a16_inl,
|
||||
.isl = a16_insl,
|
||||
};
|
||||
|
||||
/* access happens via a 32 bit bus */
|
||||
static const struct accessors access_via_32bit = {
|
||||
.ob = a_outb,
|
||||
.ow = a_outw,
|
||||
.ol = a_outl,
|
||||
.osl = a_outsl,
|
||||
.ib = a_inb,
|
||||
.iw = a_inw,
|
||||
.il = a_inl,
|
||||
.isl = a_insl,
|
||||
.ob = a8_outb,
|
||||
.ow = a16_outw,
|
||||
.ol = a32_outl,
|
||||
.osl = a32_outsl,
|
||||
.ib = a8_inb,
|
||||
.iw = a16_inw,
|
||||
.il = a32_inl,
|
||||
.isl = a32_insl,
|
||||
};
|
||||
|
||||
/* ------------------------------------------------------------------------ */
|
||||
|
||||
static inline void SMC_outb(struct smc91c111_priv *p, unsigned value,
|
||||
unsigned offset)
|
||||
{
|
||||
(p->a.ob)(value, p->base + offset);
|
||||
}
|
||||
static unsigned last_bank;
|
||||
#define SMC_outb(p, value, offset) \
|
||||
do { \
|
||||
PRINTK3("\t%s:%d outb: %s[%1d:0x%04x] = 0x%02x\n", \
|
||||
__func__, __LINE__, #offset, last_bank, \
|
||||
(offset), (value)); \
|
||||
((p)->a.ob)((value), (p)->base, (offset), (p)->shift); \
|
||||
} while (0)
|
||||
|
||||
static inline void SMC_outw(struct smc91c111_priv *p, unsigned value,
|
||||
unsigned offset)
|
||||
{
|
||||
(p->a.ow)(value, p->base + offset);
|
||||
}
|
||||
#define SMC_outw(p, value, offset) \
|
||||
do { \
|
||||
PRINTK3("\t%s:%d outw: %s[%1d:0x%04x] = 0x%04x\n", \
|
||||
__func__, __LINE__, #offset, last_bank, \
|
||||
(offset), (value)); \
|
||||
((p)->a.ow)((value), (p)->base, (offset), (p)->shift); \
|
||||
} while (0)
|
||||
|
||||
static inline void SMC_outl(struct smc91c111_priv *p, unsigned long value,
|
||||
unsigned offset)
|
||||
{
|
||||
(p->a.ol)(value, p->base + offset);
|
||||
}
|
||||
#define SMC_outl(p, value, offset) \
|
||||
do { \
|
||||
PRINTK3("\t%s:%d outl: %s[%1d:0x%04x] = 0x%08lx\n", \
|
||||
__func__, __LINE__, #offset, last_bank, \
|
||||
(offset), (unsigned long)(value)); \
|
||||
((p)->a.ol)((value), (p)->base, (offset), (p)->shift); \
|
||||
} while (0)
|
||||
|
||||
static inline void SMC_outsl(struct smc91c111_priv *p, unsigned offset,
|
||||
const void *data, int count)
|
||||
{
|
||||
(p->a.osl)(p->base + offset, data, count);
|
||||
}
|
||||
#define SMC_outsl(p, offset, data, count)\
|
||||
do { \
|
||||
PRINTK3("\t%s:%d outsl: %5d@%p -> [%1d:0x%04x]\n", \
|
||||
__func__, __LINE__, (count) * 4, data, \
|
||||
last_bank, (offset)); \
|
||||
((p)->a.osl)((p)->base, (offset), data, (count), \
|
||||
(p)->shift); \
|
||||
} while (0)
|
||||
|
||||
static inline unsigned SMC_inb(struct smc91c111_priv *p, unsigned offset)
|
||||
{
|
||||
return (p->a.ib)(p->base + offset);
|
||||
}
|
||||
#define SMC_inb(p, offset) \
|
||||
({ \
|
||||
unsigned _v = ((p)->a.ib)((p)->base, (offset), \
|
||||
(p)->shift); \
|
||||
PRINTK3("\t%s:%d inb: %s[%1d:0x%04x] -> 0x%02x\n", \
|
||||
__func__, __LINE__, #offset, last_bank, \
|
||||
(offset), _v); \
|
||||
_v; })
|
||||
|
||||
static inline unsigned SMC_inw(struct smc91c111_priv *p, unsigned offset)
|
||||
{
|
||||
return (p->a.iw)(p->base + offset);
|
||||
}
|
||||
#define SMC_inw(p, offset) \
|
||||
({ \
|
||||
unsigned _v = ((p)->a.iw)((p)->base, (offset), \
|
||||
(p)->shift); \
|
||||
PRINTK3("\t%s:%d inw: %s[%1d:0x%04x] -> 0x%04x\n", \
|
||||
__func__, __LINE__, #offset, last_bank, \
|
||||
(offset), _v); \
|
||||
_v; })
|
||||
|
||||
static inline unsigned long SMC_inl(struct smc91c111_priv *p, unsigned offset)
|
||||
{
|
||||
return (p->a.il)(p->base + offset);
|
||||
}
|
||||
#define SMC_inl(p, offset) \
|
||||
({ \
|
||||
unsigned long _v = ((p)->a.il)((p)->base, (offset), \
|
||||
(p)->shift); \
|
||||
PRINTK3("\t%s:%d inl: %s[%1d:0x%04x] -> 0x%08lx\n", \
|
||||
__func__, __LINE__, #offset, last_bank, \
|
||||
(offset), _v); \
|
||||
_v; })
|
||||
|
||||
static inline void SMC_insl(struct smc91c111_priv *p, unsigned offset,
|
||||
void *data, int count)
|
||||
{
|
||||
(p->a.isl)(p->base + offset, data, count);
|
||||
}
|
||||
#define SMC_insl(p, offset, data, count) \
|
||||
((p)->a.isl)((p)->base, (offset), data, (count), (p)->shift)
|
||||
|
||||
static inline void SMC_SELECT_BANK(struct smc91c111_priv *p, int bank)
|
||||
{
|
||||
SMC_outw(p, bank, BANK_SELECT);
|
||||
}
|
||||
#define SMC_SELECT_BANK(p, bank) \
|
||||
do { \
|
||||
SMC_outw(p, bank & 0xf, BANK_SELECT); \
|
||||
last_bank = bank & 0xf; \
|
||||
} while (0)
|
||||
|
||||
#if SMC_DEBUG > 2
|
||||
static void print_packet( unsigned char * buf, int length )
|
||||
|
|
@ -863,6 +935,7 @@ static int smc91c111_phy_read(struct mii_bus *bus, int phyaddr, int phyreg)
|
|||
static void smc91c111_reset(struct eth_device *edev)
|
||||
{
|
||||
struct smc91c111_priv *priv = (struct smc91c111_priv *)edev->priv;
|
||||
int rev_vers;
|
||||
|
||||
/* This resets the registers mostly to defaults, but doesn't
|
||||
affect EEPROM. That seems unnecessary */
|
||||
|
|
@ -878,8 +951,11 @@ static void smc91c111_reset(struct eth_device *edev)
|
|||
|
||||
/* Release from possible power-down state */
|
||||
/* Configuration register is not affected by Soft Reset */
|
||||
SMC_outw(priv, SMC_inw(priv, CONFIG_REG) | CONFIG_EPH_POWER_EN,
|
||||
CONFIG_REG);
|
||||
if (priv->config_setup)
|
||||
SMC_outw(priv, priv->config_setup, CONFIG_REG);
|
||||
else
|
||||
SMC_outw(priv, SMC_inw(priv, CONFIG_REG) | CONFIG_EPH_POWER_EN,
|
||||
CONFIG_REG);
|
||||
|
||||
SMC_SELECT_BANK(priv, 0);
|
||||
|
||||
|
|
@ -892,7 +968,10 @@ static void smc91c111_reset(struct eth_device *edev)
|
|||
|
||||
/* set the control register */
|
||||
SMC_SELECT_BANK(priv, 1);
|
||||
SMC_outw(priv, CTL_DEFAULT, CTL_REG);
|
||||
if (priv->control_setup)
|
||||
SMC_outw(priv, priv->control_setup, CTL_REG);
|
||||
else
|
||||
SMC_outw(priv, CTL_DEFAULT, CTL_REG);
|
||||
|
||||
/* Reset the MMU */
|
||||
SMC_SELECT_BANK(priv, 2);
|
||||
|
|
@ -908,6 +987,14 @@ static void smc91c111_reset(struct eth_device *edev)
|
|||
|
||||
/* Disable all interrupts */
|
||||
SMC_outb(priv, 0, IM_REG);
|
||||
|
||||
/* Check chip revision (91c94, 91c96, 91c100, ...) */
|
||||
SMC_SELECT_BANK(priv, 3);
|
||||
rev_vers = SMC_inb(priv, REV_REG);
|
||||
priv->revision = (rev_vers >> 4) & 0xf;
|
||||
priv->version = rev_vers & 0xf;
|
||||
dev_info(edev->parent, "chip is revision=%2d, version=%2d\n",
|
||||
priv->revision, priv->version);
|
||||
}
|
||||
|
||||
static void smc91c111_enable(struct eth_device *edev)
|
||||
|
|
@ -927,10 +1014,16 @@ static int smc91c111_eth_open(struct eth_device *edev)
|
|||
|
||||
/* Configure the Receive/Phy Control register */
|
||||
SMC_SELECT_BANK(priv, 0);
|
||||
SMC_outw(priv, RPC_DEFAULT, RPC_REG);
|
||||
if (priv->revision > 4)
|
||||
SMC_outw(priv, RPC_DEFAULT, RPC_REG);
|
||||
|
||||
smc91c111_enable(edev);
|
||||
|
||||
if (priv->revision <= 4) {
|
||||
dev_info(edev->parent, "force link at 10Mpbs on internal phy\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
ret = phy_device_connect(edev, &priv->miibus, 0, NULL,
|
||||
0, PHY_INTERFACE_MODE_NA);
|
||||
|
||||
|
|
@ -1333,15 +1426,19 @@ static int smc91c111_probe(struct device_d *dev)
|
|||
edev->priv = (struct smc91c111_priv *)(edev + 1);
|
||||
|
||||
priv = edev->priv;
|
||||
priv->a = access_via_32bit;
|
||||
|
||||
if (dev->platform_data) {
|
||||
struct smc91c111_pdata *pdata = dev->platform_data;
|
||||
|
||||
priv->qemu_fixup = pdata->qemu_fixup;
|
||||
priv->shift = pdata->addr_shift;
|
||||
if (pdata->bus_width == 16)
|
||||
priv->a = access_via_16bit;
|
||||
pdata->config_setup = pdata->config_setup;
|
||||
pdata->control_setup = pdata->control_setup;
|
||||
}
|
||||
|
||||
priv->a = access_via_32bit;
|
||||
|
||||
edev->init = smc91c111_init_dev;
|
||||
edev->open = smc91c111_eth_open;
|
||||
edev->send = smc91c111_eth_send;
|
||||
|
|
@ -1361,7 +1458,8 @@ static int smc91c111_probe(struct device_d *dev)
|
|||
|
||||
smc91c111_reset(edev);
|
||||
|
||||
mdiobus_register(&priv->miibus);
|
||||
if (priv->revision > 4)
|
||||
mdiobus_register(&priv->miibus);
|
||||
eth_register(edev);
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -9,6 +9,10 @@
|
|||
|
||||
struct smc91c111_pdata {
|
||||
int qemu_fixup;
|
||||
int addr_shift;
|
||||
int bus_width;
|
||||
int config_setup;
|
||||
int control_setup;
|
||||
};
|
||||
|
||||
#endif /* __SMC91111_H__ */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Robert Jarzmik
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Taken from linux kernel mostly.
|
||||
*/
|
||||
#ifndef __MRVL_NAND_H
|
||||
#define __MRVL_NAND_H
|
||||
|
||||
struct mrvl_nand_timing {
|
||||
uint16_t id; /* NAND id code (READID) */
|
||||
unsigned int tCH; /* Enable signal hold time */
|
||||
unsigned int tCS; /* Enable signal setup time */
|
||||
unsigned int tWH; /* ND_nWE high duration */
|
||||
unsigned int tWP; /* ND_nWE pulse time */
|
||||
unsigned int tRH; /* ND_nRE high duration */
|
||||
unsigned int tRP; /* ND_nRE pulse width */
|
||||
unsigned int tR; /* ND_nWE high to ND_nRE low for read */
|
||||
unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */
|
||||
unsigned int tAR; /* ND_ALE low to ND_nRE low delay */
|
||||
};
|
||||
|
||||
struct mrvl_nand_flash {
|
||||
char *name;
|
||||
uint32_t chip_id;
|
||||
unsigned int page_per_block; /* Pages per block (PG_PER_BLK) */
|
||||
unsigned int page_size; /* Page size in bytes (PAGE_SZ) */
|
||||
unsigned int flash_width; /* Flash memory width (DWIDTH_M) */
|
||||
unsigned int dfc_width; /* Flash controller width (DWIDTH_C) */
|
||||
unsigned int num_blocks; /* Number of physical blocks in Flash */
|
||||
|
||||
struct mrvl_nand_timing *timing; /* NAND Flash timing */
|
||||
};
|
||||
|
||||
/*
|
||||
* Current pxa3xx_nand controller has two chip select which
|
||||
* both be workable.
|
||||
*
|
||||
* Notice should be taken that:
|
||||
* When you want to use this feature, you should not enable the
|
||||
* keep configuration feature, for two chip select could be
|
||||
* attached with different nand chip. The different page size
|
||||
* and timing requirement make the keep configuration impossible.
|
||||
*/
|
||||
|
||||
/* The max num of chip select current support */
|
||||
#define NUM_CHIP_SELECT (2)
|
||||
struct mrvl_nand_platform_data {
|
||||
/* the data flash bus is shared between the Static Memory
|
||||
* Controller and the Data Flash Controller, the arbiter
|
||||
* controls the ownership of the bus
|
||||
*/
|
||||
int dwidth_c;
|
||||
int dwidth_m;
|
||||
|
||||
/* allow platform code to keep OBM/bootloader defined NFC config */
|
||||
int keep_config;
|
||||
|
||||
/* indicate how many chip selects will be used */
|
||||
int num_cs;
|
||||
|
||||
/* use an flash-based bad block table */
|
||||
bool flash_bbt;
|
||||
|
||||
/* requested ECC strength and ECC step size */
|
||||
int ecc_strength, ecc_step_size;
|
||||
|
||||
const struct mtd_partition *parts[NUM_CHIP_SELECT];
|
||||
unsigned int nr_parts[NUM_CHIP_SELECT];
|
||||
|
||||
const struct mrvl_nand_flash *flash;
|
||||
size_t num_flash;
|
||||
};
|
||||
|
||||
extern void mrvl_set_nand_info(struct mrvl_nand_platform_data *info);
|
||||
#endif /* __MRVL_NAND_H */
|
||||
Loading…
Reference in New Issue