davinci_nand: add support for the NAND controller
This driver is based on the Linux driver (v4.0). Signed-off-by: Jan Luebbe <jluebbe@debian.org>
This commit is contained in:
parent
562fa20935
commit
1b9e345d6e
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@ -140,4 +140,11 @@ config MTD_NAND_NOMADIK
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help
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Driver for the NAND flash controller on the Nomadik, with ECC.
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config MTD_NAND_DAVINCI
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tristate "Support NAND on DaVinci"
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depends on ARCH_DAVINCI
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help
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Enable the driver for NAND flash chips on Texas Instruments
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DaVinci processors.
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endif
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@ -7,6 +7,7 @@ obj-$(CONFIG_NAND) += nand_base.o nand-bb.o
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obj-$(CONFIG_NAND_BBT) += nand_bbt.o
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obj-$(CONFIG_MTD_NAND_NOMADIK) += nomadik_nand.o
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obj-$(CONFIG_MTD_NAND_DAVINCI) += davinci_nand.o
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obj-$(CONFIG_NAND_IMX) += nand_imx.o
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obj-$(CONFIG_NAND_IMX_BBM) += nand_imx_bbm.o
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obj-$(CONFIG_NAND_OMAP_GPMC) += nand_omap_gpmc.o nand_omap_bch_decoder.o
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@ -0,0 +1,866 @@
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/*
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* davinci_nand.c - NAND Flash Driver for DaVinci family chips
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*
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* Copyright © 2006 Texas Instruments.
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*
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* Port to 2.6.23 Copyright © 2008 by:
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* Sander Huijsen <Shuijsen@optelecom-nkf.com>
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* Troy Kisky <troy.kisky@boundarydevices.com>
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* Dirk Behme <Dirk.Behme@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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//#define DEBUG
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#include <common.h>
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#include <io.h>
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#include <malloc.h>
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#include <driver.h>
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#include <init.h>
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#include <clock.h>
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#include <of.h>
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#include <of_mtd.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/mtd/nand.h>
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#define NANDFCR_OFFSET 0x60
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#define NANDFSR_OFFSET 0x64
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#define NANDF1ECC_OFFSET 0x70
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/* 4-bit ECC syndrome registers */
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#define NAND_4BIT_ECC_LOAD_OFFSET 0xbc
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#define NAND_4BIT_ECC1_OFFSET 0xc0
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#define NAND_4BIT_ECC2_OFFSET 0xc4
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#define NAND_4BIT_ECC3_OFFSET 0xc8
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#define NAND_4BIT_ECC4_OFFSET 0xcc
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#define NAND_ERR_ADD1_OFFSET 0xd0
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#define NAND_ERR_ADD2_OFFSET 0xd4
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#define NAND_ERR_ERRVAL1_OFFSET 0xd8
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#define NAND_ERR_ERRVAL2_OFFSET 0xdc
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/* NOTE: boards don't need to use these address bits
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* for ALE/CLE unless they support booting from NAND.
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* They're used unless platform data overrides them.
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*/
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#define MASK_ALE 0x08
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#define MASK_CLE 0x10
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struct davinci_nand_pdata { /* platform_data */
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uint32_t chipsel;
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uint32_t mask_ale;
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uint32_t mask_cle;
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/* for packages using two chipselects */
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uint32_t mask_chipsel;
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/* board's default static partition info */
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struct mtd_partition *parts;
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unsigned nr_parts;
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/* none == NAND_ECC_NONE (strongly *not* advised!!)
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* soft == NAND_ECC_SOFT
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* else == NAND_ECC_HW, according to ecc_bits
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*
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* All DaVinci-family chips support 1-bit hardware ECC.
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* Newer ones also support 4-bit ECC, but are awkward
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* using it with large page chips.
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*/
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nand_ecc_modes_t ecc_mode;
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u8 ecc_bits;
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/* e.g. NAND_BUSWIDTH_16 */
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unsigned options;
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/* e.g. NAND_BBT_USE_FLASH */
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unsigned bbt_options;
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/* Main and mirror bbt descriptor overrides */
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struct nand_bbt_descr *bbt_td;
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struct nand_bbt_descr *bbt_md;
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/* Access timings */
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//struct davinci_aemif_timing *timing;
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};
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#define NRCSR_OFFSET 0x00
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#define AWCCR_OFFSET 0x04
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#define A1CR_OFFSET 0x10
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#define ACR_ASIZE_MASK 0x3
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#define ACR_EW_MASK BIT(30)
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#define ACR_SS_MASK BIT(31)
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/*
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* This is a device driver for the NAND flash controller found on the
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* various DaVinci family chips. It handles up to four SoC chipselects,
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* and some flavors of secondary chipselect (e.g. based on A12) as used
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* with multichip packages.
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*
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* The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
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* available on chips like the DM355 and OMAP-L137 and needed with the
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* more error-prone MLC NAND chips.
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*
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* This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
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* outputs in a "wire-AND" configuration, with no per-chip signals.
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*/
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struct davinci_nand_info {
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struct mtd_info mtd;
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struct nand_chip chip;
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struct nand_ecclayout ecclayout;
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struct device_d *dev;
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struct clk *clk;
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bool is_readmode;
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void __iomem *base;
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void __iomem *vaddr;
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uint32_t ioaddr;
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uint32_t current_cs;
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uint32_t mask_chipsel;
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uint32_t mask_ale;
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uint32_t mask_cle;
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uint32_t core_chipsel;
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//struct davinci_aemif_timing *timing;
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};
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static bool ecc4_busy;
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#define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd)
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static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
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int offset)
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{
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return __raw_readl(info->base + offset);
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}
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static inline void davinci_nand_writel(struct davinci_nand_info *info,
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int offset, unsigned long value)
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{
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__raw_writel(value, info->base + offset);
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}
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/*----------------------------------------------------------------------*/
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/*
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* Access to hardware control lines: ALE, CLE, secondary chipselect.
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*/
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static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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uint32_t addr = info->current_cs;
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struct nand_chip *nand = mtd->priv;
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/* Did the control lines change? */
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if (ctrl & NAND_CTRL_CHANGE) {
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if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE)
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addr |= info->mask_cle;
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else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE)
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addr |= info->mask_ale;
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nand->IO_ADDR_W = (void __iomem __force *)addr;
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}
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if (cmd != NAND_CMD_NONE)
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iowrite8(cmd, nand->IO_ADDR_W);
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}
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static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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uint32_t addr = info->ioaddr;
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/* maybe kick in a second chipselect */
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if (chip > 0)
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addr |= info->mask_chipsel;
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info->current_cs = addr;
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info->chip.IO_ADDR_W = (void __iomem __force *)addr;
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info->chip.IO_ADDR_R = info->chip.IO_ADDR_W;
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}
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/*----------------------------------------------------------------------*/
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/*
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* 1-bit hardware ECC ... context maintained for each core chipselect
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*/
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static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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dev_dbg(info->dev, "%s\n", __func__);
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return davinci_nand_readl(info, NANDF1ECC_OFFSET
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+ 4 * info->core_chipsel);
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}
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static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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uint32_t nandcfr;
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dev_dbg(info->dev, "%s\n", __func__);
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/* Reset ECC hardware */
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nand_davinci_readecc_1bit(mtd);
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/* Restart ECC hardware */
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nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
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nandcfr |= BIT(8 + info->core_chipsel);
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davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr);
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}
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/*
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* Read hardware ECC value and pack into three bytes
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*/
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static int nand_davinci_calculate_1bit(struct mtd_info *mtd,
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const u_char *dat, u_char *ecc_code)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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unsigned int ecc_val = nand_davinci_readecc_1bit(mtd);
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unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4);
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dev_dbg(info->dev, "%s\n", __func__);
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/* invert so that erased block ecc is correct */
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ecc24 = ~ecc24;
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ecc_code[0] = (u_char)(ecc24);
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ecc_code[1] = (u_char)(ecc24 >> 8);
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ecc_code[2] = (u_char)(ecc24 >> 16);
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return 0;
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}
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static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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struct nand_chip *chip = mtd->priv;
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uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) |
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(read_ecc[2] << 16);
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uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) |
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(calc_ecc[2] << 16);
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uint32_t diff = eccCalc ^ eccNand;
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dev_dbg(info->dev, "%s nand=0x%x calc=0x%x\n", __func__, eccNand, eccCalc);
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if (diff) {
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if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
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/* Correctable error */
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if ((diff >> (12 + 3)) < chip->ecc.size) {
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dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7);
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return 1;
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} else {
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return -1;
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}
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} else if (!(diff & (diff - 1))) {
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/* Single bit ECC error in the ECC itself,
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* nothing to fix */
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return 1;
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} else {
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/* Uncorrectable error */
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return -1;
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}
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}
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return 0;
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}
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/*----------------------------------------------------------------------*/
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/*
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* 4-bit hardware ECC ... context maintained over entire AEMIF
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*
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* This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME
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* since that forces use of a problematic "infix OOB" layout.
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* Among other things, it trashes manufacturer bad block markers.
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* Also, and specific to this hardware, it ECC-protects the "prepad"
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* in the OOB ... while having ECC protection for parts of OOB would
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* seem useful, the current MTD stack sometimes wants to update the
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* OOB without recomputing ECC.
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*/
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static void nand_davinci_hwctl_4bit(struct mtd_info *mtd, int mode)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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u32 val;
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/* Start 4-bit ECC calculation for read/write */
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val = davinci_nand_readl(info, NANDFCR_OFFSET);
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val &= ~(0x03 << 4);
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val |= (info->core_chipsel << 4) | BIT(12);
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davinci_nand_writel(info, NANDFCR_OFFSET, val);
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info->is_readmode = (mode == NAND_ECC_READ);
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}
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/* Read raw ECC code after writing to NAND. */
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static void
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nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4])
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{
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const u32 mask = 0x03ff03ff;
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code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask;
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code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask;
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code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask;
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code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask;
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}
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/* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
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static int nand_davinci_calculate_4bit(struct mtd_info *mtd,
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const u_char *dat, u_char *ecc_code)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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u32 raw_ecc[4], *p;
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unsigned i;
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/* After a read, terminate ECC calculation by a dummy read
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* of some 4-bit ECC register. ECC covers everything that
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* was read; correct() just uses the hardware state, so
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* ecc_code is not needed.
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*/
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if (info->is_readmode) {
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davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
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return 0;
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}
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/* Pack eight raw 10-bit ecc values into ten bytes, making
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* two passes which each convert four values (in upper and
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* lower halves of two 32-bit words) into five bytes. The
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* ROM boot loader uses this same packing scheme.
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*/
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nand_davinci_readecc_4bit(info, raw_ecc);
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for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
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*ecc_code++ = p[0] & 0xff;
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*ecc_code++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
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*ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
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*ecc_code++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
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*ecc_code++ = (p[1] >> 18) & 0xff;
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}
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return 0;
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}
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/* Correct up to 4 bits in data we just read, using state left in the
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* hardware plus the ecc_code computed when it was first written.
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*/
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static int nand_davinci_correct_4bit(struct mtd_info *mtd,
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u_char *data, u_char *ecc_code, u_char *null)
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{
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int i;
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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unsigned short ecc10[8];
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unsigned short *ecc16;
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u32 syndrome[4];
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unsigned num_errors, corrected;
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/* All bytes 0xff? It's an erased page; ignore its ECC. */
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for (i = 0; i < 10; i++) {
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if (ecc_code[i] != 0xff)
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goto compare;
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}
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return 0;
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compare:
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/* Unpack ten bytes into eight 10 bit values. We know we're
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* little-endian, and use type punning for less shifting/masking.
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*/
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if (WARN_ON(0x01 & (unsigned) ecc_code))
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return -EINVAL;
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ecc16 = (unsigned short *)ecc_code;
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ecc10[0] = (ecc16[0] >> 0) & 0x3ff;
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ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0);
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ecc10[2] = (ecc16[1] >> 4) & 0x3ff;
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ecc10[3] = ((ecc16[1] >> 14) & 0x3) | ((ecc16[2] << 2) & 0x3fc);
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ecc10[4] = (ecc16[2] >> 8) | ((ecc16[3] << 8) & 0x300);
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ecc10[5] = (ecc16[3] >> 2) & 0x3ff;
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ecc10[6] = ((ecc16[3] >> 12) & 0xf) | ((ecc16[4] << 4) & 0x3f0);
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ecc10[7] = (ecc16[4] >> 6) & 0x3ff;
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/* Tell ECC controller about the expected ECC codes. */
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for (i = 7; i >= 0; i--)
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davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]);
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/* Allow time for syndrome calculation ... then read it.
|
||||
* A syndrome of all zeroes 0 means no detected errors.
|
||||
*/
|
||||
davinci_nand_readl(info, NANDFSR_OFFSET);
|
||||
nand_davinci_readecc_4bit(info, syndrome);
|
||||
if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3]))
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* Clear any previous address calculation by doing a dummy read of an
|
||||
* error address register.
|
||||
*/
|
||||
davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET);
|
||||
|
||||
/* Start address calculation, and wait for it to complete.
|
||||
* We _could_ start reading more data while this is working,
|
||||
* to speed up the overall page read.
|
||||
*/
|
||||
davinci_nand_writel(info, NANDFCR_OFFSET,
|
||||
davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));
|
||||
|
||||
/*
|
||||
* ECC_STATE field reads 0x3 (Error correction complete) immediately
|
||||
* after setting the 4BITECC_ADD_CALC_START bit. So if you immediately
|
||||
* begin trying to poll for the state, you may fall right out of your
|
||||
* loop without any of the correction calculations having taken place.
|
||||
* The recommendation from the hardware team is to initially delay as
|
||||
* long as ECC_STATE reads less than 4. After that, ECC HW has entered
|
||||
* correction state.
|
||||
*/
|
||||
wait_on_timeout(100 * USECOND,
|
||||
((davinci_nand_readl(info, NANDFSR_OFFSET) >> 8) & 0x0f)
|
||||
< 4);
|
||||
|
||||
for (;;) {
|
||||
u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET);
|
||||
|
||||
switch ((fsr >> 8) & 0x0f) {
|
||||
case 0: /* no error, should not happen */
|
||||
davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
|
||||
return 0;
|
||||
case 1: /* five or more errors detected */
|
||||
davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
|
||||
return -EIO;
|
||||
case 2: /* error addresses computed */
|
||||
case 3:
|
||||
num_errors = 1 + ((fsr >> 16) & 0x03);
|
||||
goto correct;
|
||||
default: /* still working on it */
|
||||
//cpu_relax();
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
correct:
|
||||
/* correct each error */
|
||||
for (i = 0, corrected = 0; i < num_errors; i++) {
|
||||
int error_address, error_value;
|
||||
|
||||
if (i > 1) {
|
||||
error_address = davinci_nand_readl(info,
|
||||
NAND_ERR_ADD2_OFFSET);
|
||||
error_value = davinci_nand_readl(info,
|
||||
NAND_ERR_ERRVAL2_OFFSET);
|
||||
} else {
|
||||
error_address = davinci_nand_readl(info,
|
||||
NAND_ERR_ADD1_OFFSET);
|
||||
error_value = davinci_nand_readl(info,
|
||||
NAND_ERR_ERRVAL1_OFFSET);
|
||||
}
|
||||
|
||||
if (i & 1) {
|
||||
error_address >>= 16;
|
||||
error_value >>= 16;
|
||||
}
|
||||
error_address &= 0x3ff;
|
||||
error_address = (512 + 7) - error_address;
|
||||
|
||||
if (error_address < 512) {
|
||||
data[error_address] ^= error_value;
|
||||
corrected++;
|
||||
}
|
||||
}
|
||||
|
||||
return corrected;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* NOTE: NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
|
||||
* how these chips are normally wired. This translates to both 8 and 16
|
||||
* bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
|
||||
*
|
||||
* For now we assume that configuration, or any other one which ignores
|
||||
* the two LSBs for NAND access ... so we can issue 32-bit reads/writes
|
||||
* and have that transparently morphed into multiple NAND operations.
|
||||
*/
|
||||
static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
|
||||
{
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
struct davinci_nand_info *info = to_davinci_nand(mtd);
|
||||
|
||||
dev_dbg(info->dev, "%s\n", __func__);
|
||||
|
||||
|
||||
if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
|
||||
readsl(chip->IO_ADDR_R, buf, len >> 2);
|
||||
else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
|
||||
readsw(chip->IO_ADDR_R, buf, len >> 1);
|
||||
else
|
||||
readsb(chip->IO_ADDR_R, buf, len);
|
||||
}
|
||||
|
||||
static void nand_davinci_write_buf(struct mtd_info *mtd,
|
||||
const uint8_t *buf, int len)
|
||||
{
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
struct davinci_nand_info *info = to_davinci_nand(mtd);
|
||||
|
||||
dev_dbg(info->dev, "%s\n", __func__);
|
||||
|
||||
|
||||
if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
|
||||
writesl(chip->IO_ADDR_R, buf, len >> 2);
|
||||
else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
|
||||
writesw(chip->IO_ADDR_R, buf, len >> 1);
|
||||
else
|
||||
writesb(chip->IO_ADDR_R, buf, len);
|
||||
}
|
||||
|
||||
/*
|
||||
* Check hardware register for wait status. Returns 1 if device is ready,
|
||||
* 0 if it is still busy.
|
||||
*/
|
||||
static int nand_davinci_dev_ready(struct mtd_info *mtd)
|
||||
{
|
||||
struct davinci_nand_info *info = to_davinci_nand(mtd);
|
||||
|
||||
return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
/* An ECC layout for using 4-bit ECC with small-page flash, storing
|
||||
* ten ECC bytes plus the manufacturer's bad block marker byte, and
|
||||
* and not overlapping the default BBT markers.
|
||||
*/
|
||||
static struct nand_ecclayout hwecc4_small = {
|
||||
.eccbytes = 10,
|
||||
.eccpos = { 0, 1, 2, 3, 4,
|
||||
/* offset 5 holds the badblock marker */
|
||||
6, 7,
|
||||
13, 14, 15, },
|
||||
.oobfree = {
|
||||
{.offset = 8, .length = 5, },
|
||||
{.offset = 16, },
|
||||
},
|
||||
};
|
||||
|
||||
/* An ECC layout for using 4-bit ECC with large-page (2048bytes) flash,
|
||||
* storing ten ECC bytes plus the manufacturer's bad block marker byte,
|
||||
* and not overlapping the default BBT markers.
|
||||
*/
|
||||
static struct nand_ecclayout hwecc4_2048 = {
|
||||
.eccbytes = 40,
|
||||
.eccpos = {
|
||||
/* at the end of spare sector */
|
||||
24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
|
||||
34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
|
||||
44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
|
||||
54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
|
||||
},
|
||||
.oobfree = {
|
||||
/* 2 bytes at offset 0 hold manufacturer badblock markers */
|
||||
{.offset = 2, .length = 22, },
|
||||
/* 5 bytes at offset 8 hold BBT markers */
|
||||
/* 8 bytes at offset 16 hold JFFS2 clean markers */
|
||||
},
|
||||
};
|
||||
|
||||
static struct of_device_id davinci_nand_of_match[] = {
|
||||
{.compatible = "ti,davinci-nand", },
|
||||
{.compatible = "ti,keystone-nand", },
|
||||
{},
|
||||
};
|
||||
|
||||
static struct davinci_nand_pdata
|
||||
*nand_davinci_get_pdata(struct device_d *dev)
|
||||
{
|
||||
struct davinci_nand_pdata *pdata;
|
||||
const char *mode;
|
||||
u32 prop;
|
||||
|
||||
pdata = kzalloc(sizeof(struct davinci_nand_pdata),
|
||||
GFP_KERNEL);
|
||||
if (!pdata)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
if (!of_property_read_u32(dev->device_node,
|
||||
"ti,davinci-chipselect", &prop))
|
||||
pdata->chipsel = prop;
|
||||
else
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
if (!of_property_read_u32(dev->device_node,
|
||||
"ti,davinci-mask-ale", &prop))
|
||||
pdata->mask_ale = prop;
|
||||
if (!of_property_read_u32(dev->device_node,
|
||||
"ti,davinci-mask-cle", &prop))
|
||||
pdata->mask_cle = prop;
|
||||
if (!of_property_read_u32(dev->device_node,
|
||||
"ti,davinci-mask-chipsel", &prop))
|
||||
pdata->mask_chipsel = prop;
|
||||
if (!of_property_read_string(dev->device_node,
|
||||
"nand-ecc-mode", &mode) ||
|
||||
!of_property_read_string(dev->device_node,
|
||||
"ti,davinci-ecc-mode", &mode)) {
|
||||
if (!strncmp("none", mode, 4))
|
||||
pdata->ecc_mode = NAND_ECC_NONE;
|
||||
if (!strncmp("soft", mode, 4))
|
||||
pdata->ecc_mode = NAND_ECC_SOFT;
|
||||
if (!strncmp("hw", mode, 2))
|
||||
pdata->ecc_mode = NAND_ECC_HW;
|
||||
}
|
||||
if (!of_property_read_u32(dev->device_node,
|
||||
"ti,davinci-ecc-bits", &prop))
|
||||
pdata->ecc_bits = prop;
|
||||
|
||||
prop = of_get_nand_bus_width(dev->device_node);
|
||||
if (0 < prop || !of_property_read_u32(dev->device_node,
|
||||
"ti,davinci-nand-buswidth", &prop))
|
||||
if (prop == 16)
|
||||
pdata->options |= NAND_BUSWIDTH_16;
|
||||
if (of_property_read_bool(dev->device_node,
|
||||
"nand-on-flash-bbt") ||
|
||||
of_property_read_bool(dev->device_node,
|
||||
"ti,davinci-nand-use-bbt"))
|
||||
pdata->bbt_options = NAND_BBT_USE_FLASH;
|
||||
|
||||
if (of_device_is_compatible(dev->device_node,
|
||||
"ti,keystone-nand")) {
|
||||
pdata->options |= NAND_NO_SUBPAGE_WRITE;
|
||||
}
|
||||
return pdata;
|
||||
}
|
||||
|
||||
static int nand_davinci_probe(struct device_d *dev)
|
||||
{
|
||||
struct davinci_nand_pdata *pdata;
|
||||
struct davinci_nand_info *info;
|
||||
int ret;
|
||||
uint32_t val;
|
||||
nand_ecc_modes_t ecc_mode;
|
||||
|
||||
pdata = nand_davinci_get_pdata(dev);
|
||||
|
||||
/* insist on board-specific configuration */
|
||||
if (!pdata)
|
||||
return -ENODEV;
|
||||
|
||||
/* which external chipselect will we be managing? */
|
||||
if (pdata->chipsel < 0 || pdata->chipsel > 3)
|
||||
return -ENODEV;
|
||||
|
||||
info = kzalloc(sizeof(*info), GFP_KERNEL);
|
||||
if (!info)
|
||||
return -ENOMEM;
|
||||
|
||||
//platform_set_drvdata(pdev, info);
|
||||
|
||||
info->dev = dev;
|
||||
info->base = dev_request_mem_region(dev, 1);
|
||||
info->vaddr = dev_request_mem_region(dev, 0);
|
||||
|
||||
val = davinci_nand_readl(info, NRCSR_OFFSET);
|
||||
dev_info(dev, "controller rev. %d.%d\n",
|
||||
(val >> 8) & 0xff, val & 0xff);
|
||||
|
||||
info->mtd.priv = &info->chip;
|
||||
info->mtd.name = dev_name(dev);
|
||||
info->mtd.parent = dev;
|
||||
|
||||
info->chip.IO_ADDR_R = info->vaddr;
|
||||
info->chip.IO_ADDR_W = info->vaddr;
|
||||
info->chip.chip_delay = 0;
|
||||
info->chip.select_chip = nand_davinci_select_chip;
|
||||
|
||||
/* options such as NAND_BBT_USE_FLASH */
|
||||
info->chip.bbt_options = pdata->bbt_options;
|
||||
/* options such as 16-bit widths */
|
||||
info->chip.options = pdata->options;
|
||||
info->chip.bbt_td = pdata->bbt_td;
|
||||
info->chip.bbt_md = pdata->bbt_md;
|
||||
//info->timing = pdata->timing;
|
||||
|
||||
info->ioaddr = (uint32_t __force) info->vaddr;
|
||||
|
||||
info->current_cs = info->ioaddr;
|
||||
info->core_chipsel = pdata->chipsel;
|
||||
info->mask_chipsel = pdata->mask_chipsel;
|
||||
|
||||
/* use nandboot-capable ALE/CLE masks by default */
|
||||
info->mask_ale = pdata->mask_ale ? : MASK_ALE;
|
||||
info->mask_cle = pdata->mask_cle ? : MASK_CLE;
|
||||
|
||||
/* Set address of hardware control function */
|
||||
info->chip.cmd_ctrl = nand_davinci_hwcontrol;
|
||||
info->chip.dev_ready = nand_davinci_dev_ready;
|
||||
|
||||
/* Speed up buffer I/O */
|
||||
info->chip.read_buf = nand_davinci_read_buf;
|
||||
info->chip.write_buf = nand_davinci_write_buf;
|
||||
|
||||
/* Use board-specific ECC config */
|
||||
ecc_mode = pdata->ecc_mode;
|
||||
|
||||
ret = -EINVAL;
|
||||
switch (ecc_mode) {
|
||||
case NAND_ECC_NONE:
|
||||
case NAND_ECC_SOFT:
|
||||
pdata->ecc_bits = 0;
|
||||
break;
|
||||
case NAND_ECC_HW:
|
||||
if (pdata->ecc_bits == 4) {
|
||||
/* No sanity checks: CPUs must support this,
|
||||
* and the chips may not use NAND_BUSWIDTH_16.
|
||||
*/
|
||||
|
||||
/* No sharing 4-bit hardware between chipselects yet */
|
||||
if (ecc4_busy)
|
||||
ret = -EBUSY;
|
||||
else
|
||||
ecc4_busy = true;
|
||||
|
||||
if (ret == -EBUSY)
|
||||
return ret;
|
||||
|
||||
info->chip.ecc.calculate = nand_davinci_calculate_4bit;
|
||||
info->chip.ecc.correct = nand_davinci_correct_4bit;
|
||||
info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
|
||||
info->chip.ecc.bytes = 10;
|
||||
} else {
|
||||
info->chip.ecc.calculate = nand_davinci_calculate_1bit;
|
||||
info->chip.ecc.correct = nand_davinci_correct_1bit;
|
||||
info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
|
||||
info->chip.ecc.bytes = 3;
|
||||
}
|
||||
info->chip.ecc.size = 512;
|
||||
info->chip.ecc.strength = pdata->ecc_bits;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
info->chip.ecc.mode = ecc_mode;
|
||||
|
||||
info->clk = clk_get(dev, "aemif");
|
||||
if (IS_ERR(info->clk)) {
|
||||
ret = PTR_ERR(info->clk);
|
||||
dev_dbg(dev, "unable to get AEMIF clock, err %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_enable(info->clk);
|
||||
if (ret < 0) {
|
||||
dev_dbg(dev, "unable to enable AEMIF clock, err %d\n",
|
||||
ret);
|
||||
goto err_clk_enable;
|
||||
}
|
||||
|
||||
/* put CSxNAND into NAND mode */
|
||||
val = davinci_nand_readl(info, NANDFCR_OFFSET);
|
||||
val |= BIT(info->core_chipsel);
|
||||
davinci_nand_writel(info, NANDFCR_OFFSET, val);
|
||||
|
||||
/* Scan to find existence of the device(s) */
|
||||
ret = nand_scan_ident(&info->mtd, pdata->mask_chipsel ? 2 : 1, NULL);
|
||||
if (ret < 0) {
|
||||
dev_dbg(dev, "no NAND chip(s) found\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* Update ECC layout if needed ... for 1-bit HW ECC, the default
|
||||
* is OK, but it allocates 6 bytes when only 3 are needed (for
|
||||
* each 512 bytes). For the 4-bit HW ECC, that default is not
|
||||
* usable: 10 bytes are needed, not 6.
|
||||
*/
|
||||
if (pdata->ecc_bits == 4) {
|
||||
int chunks = info->mtd.writesize / 512;
|
||||
|
||||
if (!chunks || info->mtd.oobsize < 16) {
|
||||
dev_dbg(dev, "too small\n");
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* For small page chips, preserve the manufacturer's
|
||||
* badblock marking data ... and make sure a flash BBT
|
||||
* table marker fits in the free bytes.
|
||||
*/
|
||||
if (chunks == 1) {
|
||||
info->ecclayout = hwecc4_small;
|
||||
info->ecclayout.oobfree[1].length =
|
||||
info->mtd.oobsize - 16;
|
||||
goto syndrome_done;
|
||||
}
|
||||
if (chunks == 4) {
|
||||
info->ecclayout = hwecc4_2048;
|
||||
info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
|
||||
goto syndrome_done;
|
||||
}
|
||||
|
||||
/* 4KiB page chips are not yet supported. The eccpos from
|
||||
* nand_ecclayout cannot hold 80 bytes and change to eccpos[]
|
||||
* breaks userspace ioctl interface with mtd-utils. Once we
|
||||
* resolve this issue, NAND_ECC_HW_OOB_FIRST mode can be used
|
||||
* for the 4KiB page chips.
|
||||
*
|
||||
* TODO: Note that nand_ecclayout has now been expanded and can
|
||||
* hold plenty of OOB entries.
|
||||
*/
|
||||
dev_warn(dev, "no 4-bit ECC support yet "
|
||||
"for 4KiB-page NAND\n");
|
||||
ret = -EIO;
|
||||
goto err;
|
||||
|
||||
syndrome_done:
|
||||
info->chip.ecc.layout = &info->ecclayout;
|
||||
}
|
||||
|
||||
ret = nand_scan_tail(&info->mtd);
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
|
||||
add_mtd_nand_device(&info->mtd, "nand");
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
clk_disable(info->clk);
|
||||
|
||||
err_clk_enable:
|
||||
if (ecc_mode == NAND_ECC_HW_SYNDROME)
|
||||
ecc4_busy = false;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct driver_d nand_davinci_driver = {
|
||||
.name = "davinci_nand",
|
||||
.probe = nand_davinci_probe,
|
||||
.of_compatible = DRV_OF_COMPAT(davinci_nand_of_match),
|
||||
};
|
||||
device_platform_driver(nand_davinci_driver);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Texas Instruments");
|
||||
MODULE_DESCRIPTION("Davinci NAND flash driver");
|
||||
|
Loading…
Reference in New Issue