dts: update to v4.0-rc4
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
38504401da
commit
1c1bf62c58
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@ -22,6 +22,8 @@ Optional Properties:
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- pclkN, clkN: Pairs of parent of input clock and input clock to the
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devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
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are supported currently.
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- power-domains: phandle pointing to the parent power domain, for more details
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see Documentation/devicetree/bindings/power/power_domain.txt
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Node of a device using power domains must have a power-domains property
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defined with a phandle to respective power domain.
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@ -13,6 +13,10 @@ Boards with the ST STiH407 SoC shall have the following properties:
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Required root node property:
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compatible = "st,stih407";
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Boards with the ST STiH410 SoC shall have the following properties:
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Required root node property:
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compatible = "st,stih410";
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Boards with the ST STiH418 SoC shall have the following properties:
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Required root node property:
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compatible = "st,stih418";
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@ -4,7 +4,10 @@ Ethernet nodes are defined to describe on-chip ethernet interfaces in
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APM X-Gene SoC.
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Required properties for all the ethernet interfaces:
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- compatible: Should be "apm,xgene-enet"
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- compatible: Should state binding information from the following list,
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- "apm,xgene-enet": RGMII based 1G interface
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- "apm,xgene1-sgenet": SGMII based 1G interface
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- "apm,xgene1-xgenet": XFI based 10G interface
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- reg: Address and length of the register set for the device. It contains the
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information of registers in the same order as described by reg-names
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- reg-names: Should contain the register set names
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@ -19,6 +19,16 @@ Required properties:
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providing multiple PM domains (e.g. power controllers), but can be any value
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as specified by device tree binding documentation of particular provider.
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Optional properties:
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- power-domains : A phandle and PM domain specifier as defined by bindings of
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the power controller specified by phandle.
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Some power domains might be powered from another power domain (or have
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other hardware specific dependencies). For representing such dependency
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a standard PM domain consumer binding is used. When provided, all domains
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created by the given provider should be subdomains of the domain
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specified by this binding. More details about power domain specifier are
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available in the next section.
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Example:
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power: power-controller@12340000 {
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@ -30,6 +40,25 @@ Example:
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The node above defines a power controller that is a PM domain provider and
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expects one cell as its phandle argument.
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Example 2:
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parent: power-controller@12340000 {
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compatible = "foo,power-controller";
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reg = <0x12340000 0x1000>;
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#power-domain-cells = <1>;
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};
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child: power-controller@12340000 {
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compatible = "foo,power-controller";
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reg = <0x12341000 0x1000>;
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power-domains = <&parent 0>;
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#power-domain-cells = <1>;
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};
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The nodes above define two power controllers: 'parent' and 'child'.
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Domains created by the 'child' power controller are subdomains of '0' power
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domain provided by the 'parent' power controller.
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==PM domain consumers==
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Required properties:
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@ -0,0 +1,19 @@
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ETRAX FS UART
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Required properties:
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- compatible : "axis,etraxfs-uart"
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- reg: offset and length of the register set for the device.
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- interrupts: device interrupt
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Optional properties:
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- {dtr,dsr,ri,cd}-gpios: specify a GPIO for DTR/DSR/RI/CD
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line respectively.
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Example:
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serial@b00260000 {
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compatible = "axis,etraxfs-uart";
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reg = <0xb0026000 0x1000>;
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interrupts = <68>;
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status = "disabled";
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};
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@ -12,6 +12,9 @@ I. For patch submitters
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devicetree@vger.kernel.org
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and Cc: the DT maintainers. Use scripts/get_maintainer.pl to identify
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all of the DT maintainers.
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3) The Documentation/ portion of the patch should come in the series before
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the code implementing the binding.
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@ -20,6 +20,7 @@ amlogic Amlogic, Inc.
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ams AMS AG
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amstaos AMS-Taos Inc.
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apm Applied Micro Circuits Corporation (APM)
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arasan Arasan Chip Systems
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arm ARM Ltd.
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armadeus ARMadeus Systems SARL
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asahi-kasei Asahi Kasei Corp.
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@ -27,6 +28,7 @@ atmel Atmel Corporation
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auo AU Optronics Corporation
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avago Avago Technologies
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avic Shanghai AVIC Optoelectronics Co., Ltd.
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axis Axis Communications AB
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bosch Bosch Sensortec GmbH
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brcm Broadcom Corporation
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buffalo Buffalo, Inc.
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@ -26,6 +26,11 @@ Optional properties:
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- atmel,disable : Should be present if you want to disable the watchdog.
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- atmel,idle-halt : Should be present if you want to stop the watchdog when
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entering idle state.
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CAUTION: This property should be used with care, it actually makes the
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watchdog not counting when the CPU is in idle state, therefore the
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watchdog reset time depends on mean CPU usage and will not reset at all
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if the CPU stop working while it is in idle state, which is probably
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not what you want.
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- atmel,dbg-halt : Should be present if you want to stop the watchdog when
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entering debug state.
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@ -13,7 +13,8 @@
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#define PULL_DISABLE (1 << 3)
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#define INPUT_EN (1 << 5)
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#define SLEWCTRL_FAST (1 << 6)
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#define SLEWCTRL_SLOW (1 << 6)
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#define SLEWCTRL_FAST 0
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/* update macro depending on INPUT_EN and PULL_ENA */
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#undef PIN_OUTPUT
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@ -18,7 +18,8 @@
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#define PULL_DISABLE (1 << 16)
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#define PULL_UP (1 << 17)
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#define INPUT_EN (1 << 18)
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#define SLEWCTRL_FAST (1 << 19)
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#define SLEWCTRL_SLOW (1 << 19)
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#define SLEWCTRL_FAST 0
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#define DS0_PULL_UP_DOWN_EN (1 << 27)
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#define PIN_OUTPUT (PULL_DISABLE)
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@ -301,3 +301,11 @@
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cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
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cd-inverted;
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};
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&aes {
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status = "okay";
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};
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&sham {
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status = "okay";
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};
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@ -24,11 +24,3 @@
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&mmc1 {
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vmmc-supply = <&ldo3_reg>;
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};
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&sham {
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status = "okay";
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};
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&aes {
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status = "okay";
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};
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@ -328,6 +328,10 @@
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dual_emac_res_vlan = <3>;
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};
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&phy_sel {
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rmii-clock-ext;
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};
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&mac {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&cpsw_default>;
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@ -99,7 +99,7 @@
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ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_per_m2_ck>;
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clocks = <&l4ls_gclk>;
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ti,bit-shift = <0>;
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reg = <0x0664>;
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};
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@ -107,7 +107,7 @@
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ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_per_m2_ck>;
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clocks = <&l4ls_gclk>;
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ti,bit-shift = <1>;
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reg = <0x0664>;
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};
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@ -115,7 +115,7 @@
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ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_per_m2_ck>;
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clocks = <&l4ls_gclk>;
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ti,bit-shift = <2>;
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reg = <0x0664>;
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};
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@ -107,7 +107,7 @@
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ehrpwm0_tbclk: ehrpwm0_tbclk {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_per_m2_ck>;
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clocks = <&l4ls_gclk>;
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ti,bit-shift = <0>;
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reg = <0x0664>;
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};
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@ -115,7 +115,7 @@
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ehrpwm1_tbclk: ehrpwm1_tbclk {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_per_m2_ck>;
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clocks = <&l4ls_gclk>;
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ti,bit-shift = <1>;
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reg = <0x0664>;
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};
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@ -123,7 +123,7 @@
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ehrpwm2_tbclk: ehrpwm2_tbclk {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_per_m2_ck>;
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clocks = <&l4ls_gclk>;
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ti,bit-shift = <2>;
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reg = <0x0664>;
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};
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@ -131,7 +131,7 @@
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ehrpwm3_tbclk: ehrpwm3_tbclk {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_per_m2_ck>;
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clocks = <&l4ls_gclk>;
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ti,bit-shift = <4>;
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reg = <0x0664>;
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};
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@ -139,7 +139,7 @@
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ehrpwm4_tbclk: ehrpwm4_tbclk {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_per_m2_ck>;
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clocks = <&l4ls_gclk>;
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ti,bit-shift = <5>;
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reg = <0x0664>;
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};
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@ -147,7 +147,7 @@
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ehrpwm5_tbclk: ehrpwm5_tbclk {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_per_m2_ck>;
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clocks = <&l4ls_gclk>;
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ti,bit-shift = <6>;
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reg = <0x0664>;
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};
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@ -494,12 +494,12 @@
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pinctrl_usart3_rts: usart3_rts-0 {
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atmel,pins =
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<AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC8 periph B */
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<AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
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};
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pinctrl_usart3_cts: usart3_cts-0 {
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atmel,pins =
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<AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC10 periph B */
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<AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
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};
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};
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@ -853,7 +853,7 @@
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};
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usb1: gadget@fffa4000 {
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compatible = "atmel,at91rm9200-udc";
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compatible = "atmel,at91sam9260-udc";
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reg = <0xfffa4000 0x4000>;
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interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&udc_clk>, <&udpck>;
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@ -976,7 +976,6 @@
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atmel,watchdog-type = "hardware";
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atmel,reset-type = "all";
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atmel,dbg-halt;
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atmel,idle-halt;
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status = "disabled";
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};
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@ -124,11 +124,12 @@
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};
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usb1: gadget@fffa4000 {
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compatible = "atmel,at91rm9200-udc";
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compatible = "atmel,at91sam9261-udc";
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reg = <0xfffa4000 0x4000>;
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interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&usb>, <&udc_clk>, <&udpck>;
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clock-names = "usb_clk", "udc_clk", "udpck";
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clocks = <&udc_clk>, <&udpck>;
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clock-names = "pclk", "hclk";
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atmel,matrix = <&matrix>;
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status = "disabled";
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};
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@ -262,7 +263,7 @@
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};
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matrix: matrix@ffffee00 {
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compatible = "atmel,at91sam9260-bus-matrix";
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compatible = "atmel,at91sam9260-bus-matrix", "syscon";
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reg = <0xffffee00 0x200>;
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};
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@ -69,7 +69,7 @@
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sram1: sram@00500000 {
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compatible = "mmio-sram";
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reg = <0x00300000 0x4000>;
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reg = <0x00500000 0x4000>;
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};
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ahb {
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@ -856,7 +856,7 @@
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};
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usb1: gadget@fff78000 {
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compatible = "atmel,at91rm9200-udc";
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compatible = "atmel,at91sam9263-udc";
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reg = <0xfff78000 0x4000>;
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interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&udc_clk>, <&udpck>;
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@ -905,7 +905,6 @@
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atmel,watchdog-type = "hardware";
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atmel,reset-type = "all";
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atmel,dbg-halt;
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atmel,idle-halt;
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status = "disabled";
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};
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@ -1116,7 +1116,6 @@
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atmel,watchdog-type = "hardware";
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atmel,reset-type = "all";
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atmel,dbg-halt;
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atmel,idle-halt;
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status = "disabled";
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};
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@ -1301,7 +1300,7 @@
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compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
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reg = <0x00800000 0x100000>;
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interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
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clocks = <&utmi>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
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clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck";
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status = "disabled";
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};
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@ -894,7 +894,6 @@
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atmel,watchdog-type = "hardware";
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atmel,reset-type = "all";
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atmel,dbg-halt;
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atmel,idle-halt;
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status = "disabled";
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};
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@ -1066,7 +1066,7 @@
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reg = <0x00500000 0x80000
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0xf803c000 0x400>;
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interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&usb>, <&udphs_clk>;
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clocks = <&utmi>, <&udphs_clk>;
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clock-names = "hclk", "pclk";
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status = "disabled";
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@ -1130,7 +1130,6 @@
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atmel,watchdog-type = "hardware";
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atmel,reset-type = "all";
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atmel,dbg-halt;
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atmel,idle-halt;
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status = "disabled";
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};
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@ -1186,7 +1185,7 @@
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compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
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reg = <0x00700000 0x100000>;
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interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
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clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
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clock-names = "usb_clk", "ehci_clk", "uhpck";
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status = "disabled";
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};
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@ -263,17 +263,15 @@
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dcan1_pins_default: dcan1_pins_default {
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pinctrl-single,pins = <
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0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */
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0x3d4 (MUX_MODE15) /* dcan1_rx.off */
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0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
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0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
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0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
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>;
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};
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dcan1_pins_sleep: dcan1_pins_sleep {
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pinctrl-single,pins = <
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0x3d0 (MUX_MODE15) /* dcan1_tx.off */
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0x3d4 (MUX_MODE15) /* dcan1_rx.off */
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0x418 (MUX_MODE15) /* wakeup0.off */
|
||||
0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
|
||||
0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -119,17 +119,15 @@
|
|||
|
||||
dcan1_pins_default: dcan1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */
|
||||
0x3d4 (MUX_MODE15) /* dcan1_rx.off */
|
||||
0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
|
||||
0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
|
||||
0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
|
||||
>;
|
||||
};
|
||||
|
||||
dcan1_pins_sleep: dcan1_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x3d0 (MUX_MODE15) /* dcan1_tx.off */
|
||||
0x3d4 (MUX_MODE15) /* dcan1_rx.off */
|
||||
0x418 (MUX_MODE15) /* wakeup0.off */
|
||||
0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
|
||||
0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -243,10 +243,18 @@
|
|||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_core_byp_mux: dpll_core_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x012c>;
|
||||
};
|
||||
|
||||
dpll_core_ck: dpll_core_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-core-clock";
|
||||
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
|
||||
clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
|
||||
reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
|
||||
};
|
||||
|
||||
|
|
@ -309,10 +317,18 @@
|
|||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll_dsp_byp_mux: dpll_dsp_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x0240>;
|
||||
};
|
||||
|
||||
dpll_dsp_ck: dpll_dsp_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-clock";
|
||||
clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
|
||||
clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
|
||||
reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
|
||||
};
|
||||
|
||||
|
|
@ -335,10 +351,18 @@
|
|||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll_iva_byp_mux: dpll_iva_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x01ac>;
|
||||
};
|
||||
|
||||
dpll_iva_ck: dpll_iva_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-clock";
|
||||
clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
|
||||
clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
|
||||
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
|
||||
};
|
||||
|
||||
|
|
@ -361,10 +385,18 @@
|
|||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll_gpu_byp_mux: dpll_gpu_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x02e4>;
|
||||
};
|
||||
|
||||
dpll_gpu_ck: dpll_gpu_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-clock";
|
||||
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
|
||||
clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
|
||||
reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
|
||||
};
|
||||
|
||||
|
|
@ -398,10 +430,18 @@
|
|||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll_ddr_byp_mux: dpll_ddr_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x021c>;
|
||||
};
|
||||
|
||||
dpll_ddr_ck: dpll_ddr_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-clock";
|
||||
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
|
||||
clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
|
||||
reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
|
||||
};
|
||||
|
||||
|
|
@ -416,10 +456,18 @@
|
|||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_gmac_byp_mux: dpll_gmac_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x02b4>;
|
||||
};
|
||||
|
||||
dpll_gmac_ck: dpll_gmac_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-clock";
|
||||
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
|
||||
clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
|
||||
reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
|
||||
};
|
||||
|
||||
|
|
@ -482,10 +530,18 @@
|
|||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll_eve_byp_mux: dpll_eve_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x0290>;
|
||||
};
|
||||
|
||||
dpll_eve_ck: dpll_eve_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-clock";
|
||||
clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
|
||||
clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
|
||||
reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
|
||||
};
|
||||
|
||||
|
|
@ -1249,10 +1305,18 @@
|
|||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll_per_byp_mux: dpll_per_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x014c>;
|
||||
};
|
||||
|
||||
dpll_per_ck: dpll_per_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-clock";
|
||||
clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
|
||||
clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
|
||||
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
|
||||
};
|
||||
|
||||
|
|
@ -1275,10 +1339,18 @@
|
|||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll_usb_byp_mux: dpll_usb_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x018c>;
|
||||
};
|
||||
|
||||
dpll_usb_ck: dpll_usb_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-j-type-clock";
|
||||
clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
|
||||
clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
|
||||
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include "exynos4-cpu-thermal.dtsi"
|
||||
#include <dt-bindings/clock/exynos3250.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -193,6 +194,7 @@
|
|||
interrupts = <0 216 0>;
|
||||
clocks = <&cmu CLK_TMU_APBIF>;
|
||||
clock-names = "tmu_apbif";
|
||||
#include "exynos4412-tmu-sensor-conf.dtsi"
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Device tree sources for Exynos4 thermal zone
|
||||
*
|
||||
* Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
thermal-sensors = <&tmu 0>;
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
trips {
|
||||
cpu_alert0: cpu-alert-0 {
|
||||
temperature = <70000>; /* millicelsius */
|
||||
hysteresis = <10000>; /* millicelsius */
|
||||
type = "active";
|
||||
};
|
||||
cpu_alert1: cpu-alert-1 {
|
||||
temperature = <95000>; /* millicelsius */
|
||||
hysteresis = <10000>; /* millicelsius */
|
||||
type = "active";
|
||||
};
|
||||
cpu_alert2: cpu-alert-2 {
|
||||
temperature = <110000>; /* millicelsius */
|
||||
hysteresis = <10000>; /* millicelsius */
|
||||
type = "active";
|
||||
};
|
||||
cpu_crit0: cpu-crit-0 {
|
||||
temperature = <120000>; /* millicelsius */
|
||||
hysteresis = <0>; /* millicelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu_alert0>;
|
||||
};
|
||||
map1 {
|
||||
trip = <&cpu_alert1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -38,6 +38,7 @@
|
|||
i2c5 = &i2c_5;
|
||||
i2c6 = &i2c_6;
|
||||
i2c7 = &i2c_7;
|
||||
i2c8 = &i2c_8;
|
||||
csis0 = &csis_0;
|
||||
csis1 = &csis_1;
|
||||
fimc0 = &fimc_0;
|
||||
|
|
@ -104,6 +105,7 @@
|
|||
compatible = "samsung,exynos4210-pd";
|
||||
reg = <0x10023C20 0x20>;
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&pd_lcd0>;
|
||||
};
|
||||
|
||||
pd_cam: cam-power-domain@10023C00 {
|
||||
|
|
@ -554,6 +556,22 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c_8: i2c@138E0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,s3c2440-hdmiphy-i2c";
|
||||
reg = <0x138E0000 0x100>;
|
||||
interrupts = <0 93 0>;
|
||||
clocks = <&clock CLK_I2C_HDMI>;
|
||||
clock-names = "i2c";
|
||||
status = "disabled";
|
||||
|
||||
hdmi_i2c_phy: hdmiphy@38 {
|
||||
compatible = "exynos4210-hdmiphy";
|
||||
reg = <0x38>;
|
||||
};
|
||||
};
|
||||
|
||||
spi_0: spi@13920000 {
|
||||
compatible = "samsung,exynos4210-spi";
|
||||
reg = <0x13920000 0x100>;
|
||||
|
|
@ -663,6 +681,33 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu: tmu@100C0000 {
|
||||
#include "exynos4412-tmu-sensor-conf.dtsi"
|
||||
};
|
||||
|
||||
hdmi: hdmi@12D00000 {
|
||||
compatible = "samsung,exynos4210-hdmi";
|
||||
reg = <0x12D00000 0x70000>;
|
||||
interrupts = <0 92 0>;
|
||||
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
|
||||
"mout_hdmi";
|
||||
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
|
||||
<&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
|
||||
<&clock CLK_MOUT_HDMI>;
|
||||
phy = <&hdmi_i2c_phy>;
|
||||
power-domains = <&pd_tv>;
|
||||
samsung,syscon-phandle = <&pmu_system_controller>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mixer: mixer@12C10000 {
|
||||
compatible = "samsung,exynos4210-mixer";
|
||||
interrupts = <0 91 0>;
|
||||
reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
|
||||
power-domains = <&pd_tv>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppmu_dmc0: ppmu_dmc0@106a0000 {
|
||||
compatible = "samsung,exynos-ppmu";
|
||||
reg = <0x106a0000 0x2000>;
|
||||
|
|
|
|||
|
|
@ -426,6 +426,25 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
tmu@100C0000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
cooling-maps {
|
||||
map0 {
|
||||
/* Corresponds to 800MHz at freq_table */
|
||||
cooling-device = <&cpu0 2 2>;
|
||||
};
|
||||
map1 {
|
||||
/* Corresponds to 200MHz at freq_table */
|
||||
cooling-device = <&cpu0 4 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
camera {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <>;
|
||||
|
|
|
|||
|
|
@ -505,6 +505,63 @@
|
|||
assigned-clock-rates = <0>, <160000000>;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi_en: voltage-regulator-hdmi-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "HDMI_5V";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpe0 1 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
hdmi_ddc: i2c-ddc {
|
||||
compatible = "i2c-gpio";
|
||||
gpios = <&gpe4 2 0 &gpe4 3 0>;
|
||||
i2c-gpio,delay-us = <100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pinctrl-0 = <&i2c_ddc_bus>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mixer@12C10000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
hdmi@12D00000 {
|
||||
hpd-gpio = <&gpx3 7 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_hpd>;
|
||||
hdmi-en-supply = <&hdmi_en>;
|
||||
vdd-supply = <&ldo3_reg>;
|
||||
vdd_osc-supply = <&ldo4_reg>;
|
||||
vdd_pll-supply = <&ldo3_reg>;
|
||||
ddc = <&hdmi_ddc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@138E0000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_1 {
|
||||
hdmi_hpd: hdmi-hpd {
|
||||
samsung,pins = "gpx3-7";
|
||||
samsung,pin-pud = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_0 {
|
||||
i2c_ddc_bus: i2c-ddc-bus {
|
||||
samsung,pins = "gpe4-2", "gpe4-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdma1 {
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
|
||||
#include "exynos4.dtsi"
|
||||
#include "exynos4210-pinctrl.dtsi"
|
||||
#include "exynos4-cpu-thermal.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "samsung,exynos4210", "samsung,exynos4";
|
||||
|
|
@ -35,10 +36,13 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@900 {
|
||||
cpu0: cpu@900 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0x900>;
|
||||
cooling-min-level = <4>;
|
||||
cooling-max-level = <2>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
cpu@901 {
|
||||
|
|
@ -153,16 +157,38 @@
|
|||
reg = <0x03860000 0x1000>;
|
||||
};
|
||||
|
||||
tmu@100C0000 {
|
||||
tmu: tmu@100C0000 {
|
||||
compatible = "samsung,exynos4210-tmu";
|
||||
interrupt-parent = <&combiner>;
|
||||
reg = <0x100C0000 0x100>;
|
||||
interrupts = <2 4>;
|
||||
clocks = <&clock CLK_TMU_APBIF>;
|
||||
clock-names = "tmu_apbif";
|
||||
samsung,tmu_gain = <15>;
|
||||
samsung,tmu_reference_voltage = <7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&tmu 0>;
|
||||
|
||||
trips {
|
||||
cpu_alert0: cpu-alert-0 {
|
||||
temperature = <85000>; /* millicelsius */
|
||||
};
|
||||
cpu_alert1: cpu-alert-1 {
|
||||
temperature = <100000>; /* millicelsius */
|
||||
};
|
||||
cpu_alert2: cpu-alert-2 {
|
||||
temperature = <110000>; /* millicelsius */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
g2d@12800000 {
|
||||
compatible = "samsung,s5pv210-g2d";
|
||||
reg = <0x12800000 0x1000>;
|
||||
|
|
@ -203,6 +229,14 @@
|
|||
};
|
||||
};
|
||||
|
||||
mixer: mixer@12C10000 {
|
||||
clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
|
||||
"sclk_mixer";
|
||||
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
|
||||
<&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
|
||||
<&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
|
||||
};
|
||||
|
||||
ppmu_lcd1: ppmu_lcd1@12240000 {
|
||||
compatible = "samsung,exynos-ppmu";
|
||||
reg = <0x12240000 0x2000>;
|
||||
|
|
|
|||
|
|
@ -26,10 +26,13 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@A00 {
|
||||
cpu0: cpu@A00 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0xA00>;
|
||||
cooling-min-level = <13>;
|
||||
cooling-max-level = <7>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
cpu@A01 {
|
||||
|
|
|
|||
|
|
@ -249,6 +249,20 @@
|
|||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo8_reg: ldo@8 {
|
||||
regulator-compatible = "LDO8";
|
||||
regulator-name = "VDD10_HDMI_1.0V";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
};
|
||||
|
||||
ldo10_reg: ldo@10 {
|
||||
regulator-compatible = "LDO10";
|
||||
regulator-name = "VDDQ_MIPIHSI_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
ldo11_reg: LDO11 {
|
||||
regulator-name = "VDD18_ABB1_1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
|
|
@ -411,6 +425,51 @@
|
|||
ehci: ehci@12580000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tmu@100C0000 {
|
||||
vtmu-supply = <&ldo10_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
cooling-maps {
|
||||
map0 {
|
||||
/* Corresponds to 800MHz at freq_table */
|
||||
cooling-device = <&cpu0 7 7>;
|
||||
};
|
||||
map1 {
|
||||
/* Corresponds to 200MHz at freq_table */
|
||||
cooling-device = <&cpu0 13 13>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mixer: mixer@12C10000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
hdmi@12D00000 {
|
||||
hpd-gpio = <&gpx3 7 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_hpd>;
|
||||
vdd-supply = <&ldo8_reg>;
|
||||
vdd_osc-supply = <&ldo10_reg>;
|
||||
vdd_pll-supply = <&ldo8_reg>;
|
||||
ddc = <&hdmi_ddc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
hdmi_ddc: i2c@13880000 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_bus>;
|
||||
};
|
||||
|
||||
i2c@138E0000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_1 {
|
||||
|
|
@ -425,4 +484,9 @@
|
|||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
hdmi_hpd: hdmi-hpd {
|
||||
samsung,pins = "gpx3-7";
|
||||
samsung,pin-pud = <1>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* Device tree sources for Exynos4412 TMU sensor configuration
|
||||
*
|
||||
* Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/thermal/thermal_exynos.h>
|
||||
|
||||
#thermal-sensor-cells = <0>;
|
||||
samsung,tmu_gain = <8>;
|
||||
samsung,tmu_reference_voltage = <16>;
|
||||
samsung,tmu_noise_cancel_mode = <4>;
|
||||
samsung,tmu_efuse_value = <55>;
|
||||
samsung,tmu_min_efuse_value = <40>;
|
||||
samsung,tmu_max_efuse_value = <100>;
|
||||
samsung,tmu_first_point_trim = <25>;
|
||||
samsung,tmu_second_point_trim = <85>;
|
||||
samsung,tmu_default_temp_offset = <50>;
|
||||
samsung,tmu_cal_type = <TYPE_ONE_POINT_TRIMMING>;
|
||||
|
|
@ -927,6 +927,21 @@
|
|||
pulldown-ohm = <100000>; /* 100K */
|
||||
io-channels = <&adc 2>; /* Battery temperature */
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
cooling-maps {
|
||||
map0 {
|
||||
/* Corresponds to 800MHz at freq_table */
|
||||
cooling-device = <&cpu0 7 7>;
|
||||
};
|
||||
map1 {
|
||||
/* Corresponds to 200MHz at freq_table */
|
||||
cooling-device = <&cpu0 13 13>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_system_controller {
|
||||
|
|
|
|||
|
|
@ -26,10 +26,13 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@A00 {
|
||||
cpu0: cpu@A00 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0xA00>;
|
||||
cooling-min-level = <13>;
|
||||
cooling-max-level = <7>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
cpu@A01 {
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
|
||||
#include "exynos4.dtsi"
|
||||
#include "exynos4x12-pinctrl.dtsi"
|
||||
#include "exynos4-cpu-thermal.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
|
|
@ -297,4 +298,15 @@
|
|||
clock-names = "tmu_apbif";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hdmi: hdmi@12D00000 {
|
||||
compatible = "samsung,exynos4212-hdmi";
|
||||
};
|
||||
|
||||
mixer: mixer@12C10000 {
|
||||
compatible = "samsung,exynos4212-mixer";
|
||||
clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
|
||||
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
|
||||
<&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@
|
|||
#include <dt-bindings/clock/exynos5250.h>
|
||||
#include "exynos5.dtsi"
|
||||
#include "exynos5250-pinctrl.dtsi"
|
||||
|
||||
#include "exynos4-cpu-thermal.dtsi"
|
||||
#include <dt-bindings/clock/exynos-audss-clk.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -58,11 +58,14 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0>;
|
||||
clock-frequency = <1700000000>;
|
||||
cooling-min-level = <15>;
|
||||
cooling-max-level = <9>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
|
|
@ -102,6 +105,12 @@
|
|||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_disp1: disp1-power-domain@100440A0 {
|
||||
compatible = "samsung,exynos4210-pd";
|
||||
reg = <0x100440A0 0x20>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
clock: clock-controller@10010000 {
|
||||
compatible = "samsung,exynos5250-clock";
|
||||
reg = <0x10010000 0x30000>;
|
||||
|
|
@ -235,12 +244,32 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu@10060000 {
|
||||
tmu: tmu@10060000 {
|
||||
compatible = "samsung,exynos5250-tmu";
|
||||
reg = <0x10060000 0x100>;
|
||||
interrupts = <0 65 0>;
|
||||
clocks = <&clock CLK_TMU>;
|
||||
clock-names = "tmu_apbif";
|
||||
#include "exynos4412-tmu-sensor-conf.dtsi"
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&tmu 0>;
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
/* Corresponds to 800MHz at freq_table */
|
||||
cooling-device = <&cpu0 9 9>;
|
||||
};
|
||||
map1 {
|
||||
/* Corresponds to 200MHz at freq_table */
|
||||
cooling-device = <&cpu0 15 15>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial@12C00000 {
|
||||
|
|
@ -719,6 +748,7 @@
|
|||
hdmi: hdmi {
|
||||
compatible = "samsung,exynos4212-hdmi";
|
||||
reg = <0x14530000 0x70000>;
|
||||
power-domains = <&pd_disp1>;
|
||||
interrupts = <0 95 0>;
|
||||
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
|
||||
<&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
|
||||
|
|
@ -731,9 +761,11 @@
|
|||
mixer {
|
||||
compatible = "samsung,exynos5250-mixer";
|
||||
reg = <0x14450000 0x10000>;
|
||||
power-domains = <&pd_disp1>;
|
||||
interrupts = <0 94 0>;
|
||||
clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
|
||||
clock-names = "mixer", "sclk_hdmi";
|
||||
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
|
||||
<&clock CLK_SCLK_HDMI>;
|
||||
clock-names = "mixer", "hdmi", "sclk_hdmi";
|
||||
};
|
||||
|
||||
dp_phy: video-phy@10040720 {
|
||||
|
|
@ -743,6 +775,7 @@
|
|||
};
|
||||
|
||||
dp: dp-controller@145B0000 {
|
||||
power-domains = <&pd_disp1>;
|
||||
clocks = <&clock CLK_DP>;
|
||||
clock-names = "dp";
|
||||
phys = <&dp_phy>;
|
||||
|
|
@ -750,6 +783,7 @@
|
|||
};
|
||||
|
||||
fimd: fimd@14400000 {
|
||||
power-domains = <&pd_disp1>;
|
||||
clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
|
||||
clock-names = "sclk_fimd", "fimd";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* Device tree sources for default Exynos5420 thermal zone definition
|
||||
*
|
||||
* Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
trips {
|
||||
cpu-alert-0 {
|
||||
temperature = <85000>; /* millicelsius */
|
||||
hysteresis = <10000>; /* millicelsius */
|
||||
type = "active";
|
||||
};
|
||||
cpu-alert-1 {
|
||||
temperature = <103000>; /* millicelsius */
|
||||
hysteresis = <10000>; /* millicelsius */
|
||||
type = "active";
|
||||
};
|
||||
cpu-alert-2 {
|
||||
temperature = <110000>; /* millicelsius */
|
||||
hysteresis = <10000>; /* millicelsius */
|
||||
type = "active";
|
||||
};
|
||||
cpu-crit-0 {
|
||||
temperature = <1200000>; /* millicelsius */
|
||||
hysteresis = <0>; /* millicelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
|
@ -740,8 +740,9 @@
|
|||
compatible = "samsung,exynos5420-mixer";
|
||||
reg = <0x14450000 0x10000>;
|
||||
interrupts = <0 94 0>;
|
||||
clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
|
||||
clock-names = "mixer", "sclk_hdmi";
|
||||
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
|
||||
<&clock CLK_SCLK_HDMI>;
|
||||
clock-names = "mixer", "hdmi", "sclk_hdmi";
|
||||
power-domains = <&disp_pd>;
|
||||
};
|
||||
|
||||
|
|
@ -782,6 +783,7 @@
|
|||
interrupts = <0 65 0>;
|
||||
clocks = <&clock CLK_TMU>;
|
||||
clock-names = "tmu_apbif";
|
||||
#include "exynos4412-tmu-sensor-conf.dtsi"
|
||||
};
|
||||
|
||||
tmu_cpu1: tmu@10064000 {
|
||||
|
|
@ -790,6 +792,7 @@
|
|||
interrupts = <0 183 0>;
|
||||
clocks = <&clock CLK_TMU>;
|
||||
clock-names = "tmu_apbif";
|
||||
#include "exynos4412-tmu-sensor-conf.dtsi"
|
||||
};
|
||||
|
||||
tmu_cpu2: tmu@10068000 {
|
||||
|
|
@ -798,6 +801,7 @@
|
|||
interrupts = <0 184 0>;
|
||||
clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
|
||||
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
||||
#include "exynos4412-tmu-sensor-conf.dtsi"
|
||||
};
|
||||
|
||||
tmu_cpu3: tmu@1006c000 {
|
||||
|
|
@ -806,6 +810,7 @@
|
|||
interrupts = <0 185 0>;
|
||||
clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
|
||||
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
||||
#include "exynos4412-tmu-sensor-conf.dtsi"
|
||||
};
|
||||
|
||||
tmu_gpu: tmu@100a0000 {
|
||||
|
|
@ -814,6 +819,30 @@
|
|||
interrupts = <0 215 0>;
|
||||
clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
|
||||
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
||||
#include "exynos4412-tmu-sensor-conf.dtsi"
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu0_thermal: cpu0-thermal {
|
||||
thermal-sensors = <&tmu_cpu0>;
|
||||
#include "exynos5420-trip-points.dtsi"
|
||||
};
|
||||
cpu1_thermal: cpu1-thermal {
|
||||
thermal-sensors = <&tmu_cpu1>;
|
||||
#include "exynos5420-trip-points.dtsi"
|
||||
};
|
||||
cpu2_thermal: cpu2-thermal {
|
||||
thermal-sensors = <&tmu_cpu2>;
|
||||
#include "exynos5420-trip-points.dtsi"
|
||||
};
|
||||
cpu3_thermal: cpu3-thermal {
|
||||
thermal-sensors = <&tmu_cpu3>;
|
||||
#include "exynos5420-trip-points.dtsi"
|
||||
};
|
||||
gpu_thermal: gpu-thermal {
|
||||
thermal-sensors = <&tmu_gpu>;
|
||||
#include "exynos5420-trip-points.dtsi"
|
||||
};
|
||||
};
|
||||
|
||||
watchdog: watchdog@101D0000 {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* Device tree sources for Exynos5440 TMU sensor configuration
|
||||
*
|
||||
* Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/thermal/thermal_exynos.h>
|
||||
|
||||
#thermal-sensor-cells = <0>;
|
||||
samsung,tmu_gain = <5>;
|
||||
samsung,tmu_reference_voltage = <16>;
|
||||
samsung,tmu_noise_cancel_mode = <4>;
|
||||
samsung,tmu_efuse_value = <0x5d2d>;
|
||||
samsung,tmu_min_efuse_value = <16>;
|
||||
samsung,tmu_max_efuse_value = <76>;
|
||||
samsung,tmu_first_point_trim = <25>;
|
||||
samsung,tmu_second_point_trim = <70>;
|
||||
samsung,tmu_default_temp_offset = <25>;
|
||||
samsung,tmu_cal_type = <TYPE_ONE_POINT_TRIMMING>;
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Device tree sources for default Exynos5440 thermal zone definition
|
||||
*
|
||||
* Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
trips {
|
||||
cpu-alert-0 {
|
||||
temperature = <100000>; /* millicelsius */
|
||||
hysteresis = <0>; /* millicelsius */
|
||||
type = "active";
|
||||
};
|
||||
cpu-crit-0 {
|
||||
temperature = <1050000>; /* millicelsius */
|
||||
hysteresis = <0>; /* millicelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
|
@ -219,6 +219,7 @@
|
|||
interrupts = <0 58 0>;
|
||||
clocks = <&clock CLK_B_125>;
|
||||
clock-names = "tmu_apbif";
|
||||
#include "exynos5440-tmu-sensor-conf.dtsi"
|
||||
};
|
||||
|
||||
tmuctrl_1: tmuctrl@16011C {
|
||||
|
|
@ -227,6 +228,7 @@
|
|||
interrupts = <0 58 0>;
|
||||
clocks = <&clock CLK_B_125>;
|
||||
clock-names = "tmu_apbif";
|
||||
#include "exynos5440-tmu-sensor-conf.dtsi"
|
||||
};
|
||||
|
||||
tmuctrl_2: tmuctrl@160120 {
|
||||
|
|
@ -235,6 +237,22 @@
|
|||
interrupts = <0 58 0>;
|
||||
clocks = <&clock CLK_B_125>;
|
||||
clock-names = "tmu_apbif";
|
||||
#include "exynos5440-tmu-sensor-conf.dtsi"
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu0_thermal: cpu0-thermal {
|
||||
thermal-sensors = <&tmuctrl_0>;
|
||||
#include "exynos5440-trip-points.dtsi"
|
||||
};
|
||||
cpu1_thermal: cpu1-thermal {
|
||||
thermal-sensors = <&tmuctrl_1>;
|
||||
#include "exynos5440-trip-points.dtsi"
|
||||
};
|
||||
cpu2_thermal: cpu2-thermal {
|
||||
thermal-sensors = <&tmuctrl_2>;
|
||||
#include "exynos5440-trip-points.dtsi"
|
||||
};
|
||||
};
|
||||
|
||||
sata@210000 {
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@
|
|||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio3 22 0>;
|
||||
enable-active-high;
|
||||
vin-supply = <&swbst_reg>;
|
||||
};
|
||||
|
||||
reg_usb_h1_vbus: regulator@1 {
|
||||
|
|
@ -45,6 +46,7 @@
|
|||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 29 0>;
|
||||
enable-active-high;
|
||||
vin-supply = <&swbst_reg>;
|
||||
};
|
||||
|
||||
reg_audio: regulator@2 {
|
||||
|
|
|
|||
|
|
@ -52,6 +52,7 @@
|
|||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio4 0 0>;
|
||||
enable-active-high;
|
||||
vin-supply = <&swbst_reg>;
|
||||
};
|
||||
|
||||
reg_usb_otg2_vbus: regulator@1 {
|
||||
|
|
@ -62,6 +63,7 @@
|
|||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio4 2 0>;
|
||||
enable-active-high;
|
||||
vin-supply = <&swbst_reg>;
|
||||
};
|
||||
|
||||
reg_aud3v: regulator@2 {
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
|
||||
core_thermal: core_thermal {
|
||||
polling-delay-passive = <250>; /* milliseconds */
|
||||
polling-delay = <1000>; /* milliseconds */
|
||||
polling-delay = <500>; /* milliseconds */
|
||||
|
||||
/* sensor ID */
|
||||
thermal-sensors = <&bandgap 2>;
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
|
||||
gpu_thermal: gpu_thermal {
|
||||
polling-delay-passive = <250>; /* milliseconds */
|
||||
polling-delay = <1000>; /* milliseconds */
|
||||
polling-delay = <500>; /* milliseconds */
|
||||
|
||||
/* sensor ID */
|
||||
thermal-sensors = <&bandgap 1>;
|
||||
|
|
|
|||
|
|
@ -1079,4 +1079,8 @@
|
|||
};
|
||||
};
|
||||
|
||||
&cpu_thermal {
|
||||
polling-delay = <500>; /* milliseconds */
|
||||
};
|
||||
|
||||
/include/ "omap54xx-clocks.dtsi"
|
||||
|
|
|
|||
|
|
@ -167,10 +167,18 @@
|
|||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_core_byp_mux: dpll_core_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x012c>;
|
||||
};
|
||||
|
||||
dpll_core_ck: dpll_core_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-core-clock";
|
||||
clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
|
||||
clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
|
||||
reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
|
||||
};
|
||||
|
||||
|
|
@ -294,10 +302,18 @@
|
|||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll_iva_byp_mux: dpll_iva_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x01ac>;
|
||||
};
|
||||
|
||||
dpll_iva_ck: dpll_iva_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-clock";
|
||||
clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
|
||||
clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
|
||||
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
|
||||
};
|
||||
|
||||
|
|
@ -599,10 +615,19 @@
|
|||
};
|
||||
};
|
||||
&cm_core_clocks {
|
||||
|
||||
dpll_per_byp_mux: dpll_per_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x014c>;
|
||||
};
|
||||
|
||||
dpll_per_ck: dpll_per_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-clock";
|
||||
clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
|
||||
clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
|
||||
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
|
||||
};
|
||||
|
||||
|
|
@ -714,10 +739,18 @@
|
|||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_usb_byp_mux: dpll_usb_byp_mux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x018c>;
|
||||
};
|
||||
|
||||
dpll_usb_ck: dpll_usb_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap4-dpll-j-type-clock";
|
||||
clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
|
||||
clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
|
||||
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1248,7 +1248,6 @@
|
|||
atmel,watchdog-type = "hardware";
|
||||
atmel,reset-type = "all";
|
||||
atmel,dbg-halt;
|
||||
atmel,idle-halt;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1416,7 +1415,7 @@
|
|||
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
|
||||
reg = <0x00700000 0x100000>;
|
||||
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
|
||||
clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
|
||||
clock-names = "usb_clk", "ehci_clk", "uhpck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -66,6 +66,7 @@
|
|||
gpio4 = &pioE;
|
||||
tcb0 = &tcb0;
|
||||
tcb1 = &tcb1;
|
||||
i2c0 = &i2c0;
|
||||
i2c2 = &i2c2;
|
||||
};
|
||||
cpus {
|
||||
|
|
@ -259,7 +260,7 @@
|
|||
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
|
||||
reg = <0x00600000 0x100000>;
|
||||
interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
|
||||
clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
|
||||
clock-names = "usb_clk", "ehci_clk", "uhpck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -461,8 +462,8 @@
|
|||
|
||||
lcdck: lcdck {
|
||||
#clock-cells = <0>;
|
||||
reg = <4>;
|
||||
clocks = <&smd>;
|
||||
reg = <3>;
|
||||
clocks = <&mck>;
|
||||
};
|
||||
|
||||
smdck: smdck {
|
||||
|
|
@ -770,7 +771,7 @@
|
|||
reg = <50>;
|
||||
};
|
||||
|
||||
lcd_clk: lcd_clk {
|
||||
lcdc_clk: lcdc_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <51>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -713,6 +713,9 @@
|
|||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
dmas = <&pdma 28>,
|
||||
<&pdma 29>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
uart1: serial1@ffc03000 {
|
||||
|
|
@ -722,6 +725,9 @@
|
|||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
dmas = <&pdma 30>,
|
||||
<&pdma 31>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
rst: rstmgr@ffd05000 {
|
||||
|
|
|
|||
|
|
@ -622,7 +622,7 @@
|
|||
};
|
||||
|
||||
sgenet0: ethernet@1f210000 {
|
||||
compatible = "apm,xgene-enet";
|
||||
compatible = "apm,xgene1-sgenet";
|
||||
status = "disabled";
|
||||
reg = <0x0 0x1f210000 0x0 0xd100>,
|
||||
<0x0 0x1f200000 0x0 0Xc300>,
|
||||
|
|
@ -636,7 +636,7 @@
|
|||
};
|
||||
|
||||
xgenet: ethernet@1f610000 {
|
||||
compatible = "apm,xgene-enet";
|
||||
compatible = "apm,xgene1-xgenet";
|
||||
status = "disabled";
|
||||
reg = <0x0 0x1f610000 0x0 0xd100>,
|
||||
<0x0 0x1f600000 0x0 0Xc300>,
|
||||
|
|
|
|||
Loading…
Reference in New Issue