spi: add controller driver for Atheros AR7XXX/AR9XXX SoCs
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Antony Pavlov
Sascha Hauer
parent
33e0b3f973
commit
20d70daf48
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@ -10,6 +10,10 @@ config DRIVER_SPI_ALTERA
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bool "Altera SPI Master driver"
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depends on NIOS2
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config DRIVER_SPI_ATH79
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bool "Atheros AR71XX/AR724X/AR913X/AR933X SPI controller driver"
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depends on MACH_MIPS_ATH79
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config DRIVER_SPI_ATMEL
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bool "Atmel (AT91) SPI Master driver"
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depends on ARCH_AT91
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@ -1,4 +1,5 @@
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obj-$(CONFIG_SPI) += spi.o
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obj-$(CONFIG_DRIVER_SPI_ATH79) += ath79_spi.o
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obj-$(CONFIG_DRIVER_SPI_IMX) += imx_spi.o
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obj-$(CONFIG_DRIVER_SPI_MVEBU) += mvebu_spi.o
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obj-$(CONFIG_DRIVER_SPI_MXS) += mxs_spi.o
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@ -0,0 +1,299 @@
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/*
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* Copyright (C) 2013, 2014 Antony Pavlov <antonynpavlov@gmail.com>
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*
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* This file is part of barebox.
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* See file CREDITS for list of people who contributed to this project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <driver.h>
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#include <spi/spi.h>
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#include <io.h>
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#include <clock.h>
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struct ath79_spi {
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struct spi_master master;
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void __iomem *regs;
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u32 val;
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u32 reg_ctrl;
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};
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#define AR71XX_SPI_REG_FS 0x00 /* Function Select */
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#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
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#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */
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#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */
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#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
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#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
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#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
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#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
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#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0)
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#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1)
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#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2)
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#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \
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AR71XX_SPI_IOC_CS2)
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static inline u32 ath79_spi_rr(struct ath79_spi *sp, int reg)
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{
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return cpu_readl(sp->regs + reg);
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}
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static inline void ath79_spi_wr(struct ath79_spi *sp, u32 val, int reg)
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{
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cpu_writel(val, sp->regs + reg);
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}
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static inline void setbits(struct ath79_spi *sp, int bits, int on)
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{
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/*
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* We are the only user of SCSPTR so no locking is required.
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* Reading bit 2 and 0 in SCSPTR gives pin state as input.
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* Writing the same bits sets the output value.
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* This makes regular read-modify-write difficult so we
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* use sp->val to keep track of the latest register value.
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*/
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if (on)
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sp->val |= bits;
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else
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sp->val &= ~bits;
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ath79_spi_wr(sp, sp->val, AR71XX_SPI_REG_IOC);
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}
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static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
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{
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return container_of(spi->master, struct ath79_spi, master);
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}
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static inline void setsck(struct spi_device *spi, int on)
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{
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struct ath79_spi *sc = ath79_spidev_to_sp(spi);
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setbits(sc, AR71XX_SPI_IOC_CLK, on);
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}
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static inline void setmosi(struct spi_device *spi, int on)
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{
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struct ath79_spi *sc = ath79_spidev_to_sp(spi);
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setbits(sc, AR71XX_SPI_IOC_DO, on);
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}
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static inline u32 getmiso(struct spi_device *spi)
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{
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struct ath79_spi *sc = ath79_spidev_to_sp(spi);
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return !!((ath79_spi_rr(sc, AR71XX_SPI_REG_RDS) & 1));
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}
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#include "spi-bitbang-txrx.h"
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static inline void ath79_spi_chipselect(struct ath79_spi *sp, int chipselect)
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{
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int off_bits;
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off_bits = 0xffffffff;
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switch (chipselect) {
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case 0:
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off_bits &= ~AR71XX_SPI_IOC_CS0;
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break;
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case 1:
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off_bits &= ~AR71XX_SPI_IOC_CS1;
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break;
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case 2:
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off_bits &= ~AR71XX_SPI_IOC_CS2;
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break;
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case 3:
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break;
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}
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/* by default inactivate chip selects */
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sp->val |= AR71XX_SPI_IOC_CS_ALL;
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sp->val &= off_bits;
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ath79_spi_wr(sp, sp->val, AR71XX_SPI_REG_IOC);
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}
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static int ath79_spi_setup(struct spi_device *spi)
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{
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struct spi_master *master = spi->master;
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struct device_d spi_dev = spi->dev;
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if (spi->bits_per_word != 8) {
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dev_err(master->dev, "master doesn't support %d bits per word requested by %s\n",
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spi->bits_per_word, spi_dev.name);
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return -EINVAL;
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}
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if ((spi->mode & (SPI_CPHA | SPI_CPOL)) != SPI_MODE_0) {
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dev_err(master->dev, "master doesn't support SPI_MODE%d requested by %s\n",
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spi->mode & (SPI_CPHA | SPI_CPOL), spi_dev.name);
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return -EINVAL;
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}
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return 0;
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}
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static int ath79_spi_read(struct spi_device *spi, void *buf, size_t nbyte)
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{
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ssize_t cnt = 0;
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u8 *rxf_buf = buf;
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while (cnt < nbyte) {
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*rxf_buf = bitbang_txrx_be_cpha1(spi, 1000, 1, 0, 8);
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rxf_buf++;
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cnt++;
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}
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return cnt;
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}
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static int ath79_spi_write(struct spi_device *spi,
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const void *buf, size_t nbyte)
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{
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ssize_t cnt = 0;
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const u8 *txf_buf = buf;
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while (cnt < nbyte) {
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bitbang_txrx_be_cpha1(spi, 1000, 1, (u32)*txf_buf, 8);
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txf_buf++;
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cnt++;
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}
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return 0;
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}
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static int ath79_spi_transfer(struct spi_device *spi, struct spi_message *mesg)
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{
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struct ath79_spi *sc = ath79_spidev_to_sp(spi);
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struct spi_transfer *t;
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mesg->actual_length = 0;
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/* activate chip select signal */
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ath79_spi_chipselect(sc, spi->chip_select);
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list_for_each_entry(t, &mesg->transfers, transfer_list) {
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if (t->tx_buf)
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ath79_spi_write(spi, t->tx_buf, t->len);
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if (t->rx_buf)
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ath79_spi_read(spi, t->rx_buf, t->len);
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mesg->actual_length += t->len;
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}
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/* inactivate chip select signal */
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ath79_spi_chipselect(sc, -1);
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return 0;
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}
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static void ath79_spi_enable(struct ath79_spi *sp)
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{
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/* enable GPIO mode */
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ath79_spi_wr(sp, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
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/* save CTRL register */
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sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
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sp->val = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
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/* TODO: setup speed? */
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ath79_spi_wr(sp, 0x43, AR71XX_SPI_REG_CTRL);
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}
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static void ath79_spi_disable(struct ath79_spi *sp)
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{
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/* restore CTRL register */
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ath79_spi_wr(sp, sp->reg_ctrl, AR71XX_SPI_REG_CTRL);
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/* disable GPIO mode */
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ath79_spi_wr(sp, 0, AR71XX_SPI_REG_FS);
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}
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static int ath79_spi_probe(struct device_d *dev)
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{
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struct spi_master *master;
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struct ath79_spi *ath79_spi;
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ath79_spi = xzalloc(sizeof(*ath79_spi));
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dev->priv = ath79_spi;
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master = &ath79_spi->master;
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master->dev = dev;
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master->bus_num = dev->id;
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master->setup = ath79_spi_setup;
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master->transfer = ath79_spi_transfer;
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master->num_chipselect = 3;
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if (IS_ENABLED(CONFIG_OFDEVICE)) {
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struct device_node *node = dev->device_node;
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u32 num_cs;
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int ret;
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ret = of_property_read_u32(node, "num-chipselects", &num_cs);
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if (ret)
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num_cs = 3;
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if (num_cs > 3) {
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dev_err(dev, "master doesn't support num-chipselects > 3\n");
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}
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master->num_chipselect = num_cs;
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}
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ath79_spi->regs = dev_request_mem_region(dev, 0);
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/* enable gpio mode */
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ath79_spi_enable(ath79_spi);
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/* inactivate chip select signal */
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ath79_spi_chipselect(ath79_spi, -1);
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spi_register_master(master);
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return 0;
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}
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static void ath79_spi_remove(struct device_d *dev)
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{
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struct ath79_spi *sp = dev->priv;
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ath79_spi_disable(sp);
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}
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static __maybe_unused struct of_device_id ath79_spi_dt_ids[] = {
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{
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.compatible = "qca,ath79-spi",
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},
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{
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/* sentinel */
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}
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};
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static struct driver_d ath79_spi_driver = {
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.name = "ath79-spi",
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.probe = ath79_spi_probe,
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.remove = ath79_spi_remove,
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.of_compatible = DRV_OF_COMPAT(ath79_spi_dt_ids),
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};
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device_platform_driver(ath79_spi_driver);
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