This patch adds support for Beagle Board.
Beagle board from TI is a development platform based on TI's OMAP3530 silicon. You can find more about Beagle Board here: www.beagleboard.org More on OMAP3530 (including documentation can be found here): http://focus.ti.com/docs/prod/folders/print/omap3530.html Signed-off-by: Raghavendra KH <r-khandenahally@ti.com>
This commit is contained in:
Raghavendra KH
Sascha Hauer
parent
24d376bd79
commit
23ec85feeb
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@ -0,0 +1,185 @@
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#
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# Automatically generated make config: don't edit
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# U-Boot version: 2.0.0-rc5-git
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# Tue Jun 24 02:22:41 2008
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#
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CONFIG_ARCH_TEXT_BASE=0x80e80000
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CONFIG_BOARDINFO="Texas Instrument's Beagle"
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# CONFIG_BOARD_LINKER_SCRIPT is not set
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CONFIG_GENERIC_LINKER_SCRIPT=y
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CONFIG_ARM=y
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CONFIG_ARMCORTEXA8=y
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CONFIG_ARCH_OMAP=y
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# CONFIG_MACH_MX1ADS is not set
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# CONFIG_MACH_SCB9328 is not set
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# CONFIG_MACH_PCM038 is not set
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# CONFIG_MACH_IMX27ADS is not set
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# CONFIG_MACH_ECO920 is not set
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# CONFIG_MACH_NXDB500 is not set
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# CONFIG_MACH_PCM037 is not set
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CONFIG_MACH_OMAP=y
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# CONFIG_MACH_AT91SAM9260_EK is not set
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#
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# OMAP Features
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#
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CONFIG_ARCH_OMAP3=y
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CONFIG_OMAP_CONFIG_STACKSIZE=0x00008000
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CONFIG_OMAP_MALLOC_LEN=0x00008000
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CONFIG_OMAP_CLOCK_ALL=y
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CONFIG_OMAP_CLOCK_SOURCE_S32K=y
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CONFIG_OMAP3_CLOCK_CONFIG=y
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# CONFIG_OMAP3_COPY_CLOCK_SRAM is not set
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#
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# OMAP Platform Features
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#
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# CONFIG_MACH_OMAP343xSDP is not set
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CONFIG_MACH_BEAGLE=y
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#
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# Arm specific settings
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#
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# CONFIG_CMDLINE_TAG is not set
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# CONFIG_SETUP_MEMORY_TAGS is not set
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# CONFIG_INITRD_TAG is not set
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# CONFIG_ARMCORTEXA8_DCACHE_SKIP is not set
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CONFIG_HAS_KALLSYMS=y
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CONFIG_HAS_MODULES=y
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# CONFIG_CMD_MEMORY is not set
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#
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# General Settings
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#
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#
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# memory layout
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#
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CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y
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CONFIG_TEXT_BASE=0x40200000
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CONFIG_HAVE_CONFIGURABLE_MEMORY_LAYOUT=y
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# CONFIG_MEMORY_LAYOUT_DEFAULT is not set
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CONFIG_MEMORY_LAYOUT_FIXED=y
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CONFIG_STACK_BASE=0x87BF7F10
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CONFIG_STACK_SIZE=0x8000
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CONFIG_MALLOC_BASE=0x87BFFF10
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CONFIG_MALLOC_SIZE=0x400000
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# CONFIG_BROKEN is not set
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# CONFIG_EXPERIMENTAL is not set
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CONFIG_MACH_HAS_LOWLEVEL_INIT=y
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CONFIG_MACH_DO_LOWLEVEL_INIT=y
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CONFIG_ARCH_HAS_LOWLEVEL_INIT=y
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CONFIG_PROMPT="X-load Beagle>"
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CONFIG_BAUDRATE=115200
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# CONFIG_CMDLINE_EDITING is not set
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CONFIG_SIMPLE_READLINE=y
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CONFIG_LONGHELP=y
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CONFIG_CBSIZE=1024
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CONFIG_MAXARGS=16
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# CONFIG_SHELL_HUSH is not set
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CONFIG_SHELL_SIMPLE=y
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# CONFIG_ERRNO_MESSAGES is not set
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# CONFIG_TIMESTAMP is not set
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CONFIG_CONSOLE_ACTIVATE_FIRST=y
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# CONFIG_OF_FLAT_TREE is not set
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# CONFIG_PARTITION is not set
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# CONFIG_DEFAULT_ENVIRONMENT is not set
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#
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# Debugging
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#
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# CONFIG_DEBUG_INFO is not set
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# CONFIG_ENABLE_FLASH_NOISE is not set
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# CONFIG_ENABLE_PARTITION_NOISE is not set
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# CONFIG_ENABLE_DEVICE_NOISE is not set
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#
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# Commands
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#
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#
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# scripting
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#
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# CONFIG_CMD_EDIT is not set
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# CONFIG_CMD_EXEC is not set
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# CONFIG_CMD_SLEEP is not set
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# CONFIG_CMD_SAVEENV is not set
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# CONFIG_CMD_LOADENV is not set
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# CONFIG_CMD_EXPORT is not set
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# CONFIG_CMD_PRINTENV is not set
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# CONFIG_CMD_HELP is not set
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# CONFIG_CMD_READLINE is not set
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#
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# file commands
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#
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# CONFIG_CMD_LS is not set
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# CONFIG_CMD_RM is not set
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# CONFIG_CMD_CAT is not set
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# CONFIG_CMD_MKDIR is not set
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# CONFIG_CMD_RMDIR is not set
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# CONFIG_CMD_CP is not set
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# CONFIG_CMD_PWD is not set
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# CONFIG_CMD_CD is not set
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# CONFIG_CMD_MOUNT is not set
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# CONFIG_CMD_UMOUNT is not set
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#
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# console
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#
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# CONFIG_CMD_CLEAR is not set
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# CONFIG_CMD_ECHO is not set
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#
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# memory
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#
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CONFIG_CMD_LOADB=y
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# CONFIG_CMD_MEMINFO is not set
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# CONFIG_CMD_CRC is not set
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# CONFIG_CMD_MTEST is not set
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#
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# flash
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#
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_NAND is not set
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#
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# booting
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#
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# CONFIG_CMD_BOOTM is not set
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# CONFIG_CMD_RESET is not set
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CONFIG_CMD_GO=y
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# CONFIG_CMD_TIMEOUT is not set
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# CONFIG_CMD_PARTITION is not set
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# CONFIG_NET is not set
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#
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# Drivers
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#
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#
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# serial drivers
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#
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CONFIG_DRIVER_SERIAL_NS16550=y
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CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
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#
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# SPI drivers
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#
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# CONFIG_SPI is not set
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#
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# flash drivers
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#
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# CONFIG_DRIVER_CFI is not set
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# CONFIG_DRIVER_CFI_OLD is not set
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# CONFIG_NAND is not set
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#
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# Filesystem support
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#
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# CONFIG_FS_CRAMFS is not set
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CONFIG_FS_RAMFS=y
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CONFIG_FS_DEVFS=y
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CONFIG_CRC16=y
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@ -18,6 +18,7 @@ This document highlights some of the factors for supporting Texas Instrument's O
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@section omap_boards Boards using OMAP processors
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@li @subpage board/omap/board-sdp343x.c
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@li @subpage board/omap/board-beagle.c
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@section omap_arch Documentation for OMAP Architectures files
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@ -23,12 +23,14 @@
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config ARCH_TEXT_BASE
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hex
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default 0x80e80000 if MACH_OMAP343xSDP
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default 0x80e80000 if MACH_BEAGLE
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menu "OMAP Platform Features"
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depends on MACH_OMAP
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config BOARDINFO
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default "Texas Instrument's SDP343x" if MACH_OMAP343xSDP
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default "Texas Instrument's Beagle" if MACH_BEAGLE
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choice
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prompt "Select OMAP platform"
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@ -39,6 +41,14 @@ config MACH_OMAP343xSDP
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select OMAP_CLOCK_ALL
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help
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Say Y here if you are using SDP343x platform
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config MACH_BEAGLE
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bool "Texas Instrument's Beagle Board"
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select MACH_HAS_LOWLEVEL_INIT
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select OMAP_CLOCK_ALL
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help
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Say Y here if you are using Beagle Board
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endchoice
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config MACH_OMAP_ADVANCED_MUX
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@ -22,4 +22,5 @@
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obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += platform.o
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obj-$(CONFIG_MACH_OMAP343xSDP) += board-sdp343x.o
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obj-$(CONFIG_MACH_BEAGLE) += board-beagle.o
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@ -0,0 +1,276 @@
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/**
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* @file
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* @brief Beagle Specific Board Initialization routines
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*
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* FileName: board/omap/board-beagle.c
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*
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* Beagle Board from Texas Instruments as described here:
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* http://www.beagleboard.org
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*
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* This board is based on OMAP3530.
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* More on OMAP3530 (including documentation can be found here):
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* http://focus.ti.com/docs/prod/folders/print/omap3530.html
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*
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* This file provides initialization in two stages:
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* @li boot time initialization - do basics required to get SDRAM working.
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* This is run from SRAM - so no case constructs and global vars can be used.
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* @li run time initialization - this is for the rest of the initializations
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* such as flash, uart etc.
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*
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* Boot time initialization includes:
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* @li SDRAM initialization.
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* @li Pin Muxing relevant for Beagle.
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*
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* Run time initialization includes
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* @li serial @ref serial_ns16550.c driver device definition
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*
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* Originally from board/omap/board-sdp343x.c
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*/
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/*
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* (C) Copyright 2008
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* Texas Instruments, <www.ti.com>
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* Raghavendra KH <r-khandenahally@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <console.h>
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#include <init.h>
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#include <driver.h>
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#include <asm/io.h>
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#include <ns16550.h>
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#include <asm/arch/silicon.h>
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#include <asm/arch/sdrc.h>
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#include <asm/arch/sys_info.h>
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#include <asm/arch/syslib.h>
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#include <asm/arch/control.h>
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#include <asm/arch/omap3-mux.h>
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#include "board.h"
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/******************** Board Boot Time *******************/
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/**
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* @brief Do the SDRC initialization for 128Meg Micron DDR for CS0
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*
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* @return void
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*/
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static void sdrc_init(void)
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{
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/* SDRAM software reset */
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/* No idle ack and RESET enable */
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__raw_writel(0x1A, SDRC_REG(SYSCONFIG));
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sdelay(100);
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/* No idle ack and RESET disable */
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__raw_writel(0x18, SDRC_REG(SYSCONFIG));
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/* SDRC Sharing register */
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/* 32-bit SDRAM on data lane [31:0] - CS0 */
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/* pin tri-stated = 1 */
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__raw_writel(0x00000100, SDRC_REG(SHARING));
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/* ----- SDRC Registers Configuration --------- */
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/* SDRC_MCFG0 register */
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__raw_writel(0x02584099, SDRC_REG(MCFG_0));
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/* SDRC_RFR_CTRL0 register */
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__raw_writel(0x54601, SDRC_REG(RFR_CTRL_0));
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/* SDRC_ACTIM_CTRLA0 register */
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__raw_writel(0xA29DB4C6, SDRC_REG(ACTIM_CTRLA_0));
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/* SDRC_ACTIM_CTRLB0 register */
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__raw_writel(0x12214, SDRC_REG(ACTIM_CTRLB_0));
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/* Disble Power Down of CKE due to 1 CKE on combo part */
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__raw_writel(0x00000081, SDRC_REG(POWER));
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/* SDRC_MANUAL command register */
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/* NOP command */
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__raw_writel(0x00000000, SDRC_REG(MANUAL_0));
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/* Precharge command */
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__raw_writel(0x00000001, SDRC_REG(MANUAL_0));
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/* Auto-refresh command */
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__raw_writel(0x00000002, SDRC_REG(MANUAL_0));
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/* Auto-refresh command */
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__raw_writel(0x00000002, SDRC_REG(MANUAL_0));
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/* SDRC MR0 register Burst length=4 */
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__raw_writel(0x00000032, SDRC_REG(MR_0));
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/* SDRC DLLA control register */
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__raw_writel(0x0000000A, SDRC_REG(DLLA_CTRL));
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return;
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}
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/**
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* @brief Do the pin muxing required for Board operation.
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* We enable ONLY the pins we require to set. OMAP provides pins which do not
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* have alternate modes. Such pins done need to be set.
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*
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* See @ref MUX_VAL for description of the muxing mode.
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*
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* @return void
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*/
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static void mux_config(void)
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{
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/* SDRC_D0 - SDRC_D31 default mux mode is mode0 */
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/* GPMC */
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MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0));
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/* D0-D7 default mux mode is mode0 */
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MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0));
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/* GPMC_NADV_ALE default mux mode is mode0 */
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/* GPMC_NOE default mux mode is mode0 */
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/* GPMC_NWE default mux mode is mode0 */
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/* GPMC_NBE0_CLE default mux mode is mode0 */
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MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
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/* GPMC_WAIT0 default mux mode is mode0 */
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MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
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/* SERIAL INTERFACE */
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MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
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MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0));
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/* I2C1_SCL default mux mode is mode0 */
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/* I2C1_SDA default mux mode is mode0 */
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}
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/**
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* @brief The basic entry point for board initialization.
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*
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* This is called as part of machine init (after arch init).
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* This is again called with stack in SRAM, so not too many
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* constructs possible here.
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*
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* @return void
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*/
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void board_init(void)
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{
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int in_sdram = running_in_sdram();
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mux_config();
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/* Dont reconfigure SDRAM while running in SDRAM! */
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if (!in_sdram)
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sdrc_init();
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}
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|
||||
/******************** Board Run Time *******************/
|
||||
|
||||
#ifdef CONFIG_DRIVER_SERIAL_NS16550
|
||||
|
||||
static struct NS16550_plat serial_plat = {
|
||||
.clock = 48000000, /* 48MHz (APLL96/2) */
|
||||
.f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR,
|
||||
.reg_read = omap_uart_read,
|
||||
.reg_write = omap_uart_write,
|
||||
};
|
||||
|
||||
static struct device_d beagle_serial_device = {
|
||||
.name = "serial_ns16550",
|
||||
.id = "uart3",
|
||||
.map_base = OMAP_UART3_BASE,
|
||||
.size = 1024,
|
||||
.platform_data = (void *)&serial_plat,
|
||||
.type = DEVICE_TYPE_CONSOLE,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief UART serial port initialization - remember to enable COM clocks in
|
||||
* arch
|
||||
*
|
||||
* @return result of device registration
|
||||
*/
|
||||
static int beagle_console_init(void)
|
||||
{
|
||||
/* Register the serial port */
|
||||
return register_device(&beagle_serial_device);
|
||||
}
|
||||
console_initcall(beagle_console_init);
|
||||
#endif /* CONFIG_DRIVER_SERIAL_NS16550 */
|
||||
|
||||
static struct device_d sdram_dev = {
|
||||
.name = "ram",
|
||||
.id = "ram0",
|
||||
|
||||
.map_base = 0x80000000,
|
||||
.size = 128 * 1024 * 1024,
|
||||
|
||||
.type = DEVICE_TYPE_DRAM,
|
||||
};
|
||||
|
||||
#ifndef CONFIG_CMD_MEMORY
|
||||
static struct driver_d ram_drv = {
|
||||
.name = "ram",
|
||||
.probe = dummy_probe,
|
||||
.open = dev_open_default,
|
||||
.close = dev_close_default,
|
||||
.read = mem_read,
|
||||
.write = mem_write,
|
||||
.lseek = dev_lseek_default,
|
||||
.type = DEVICE_TYPE_DRAM,
|
||||
};
|
||||
#endif
|
||||
|
||||
static int beagle_devices_init(void)
|
||||
{
|
||||
int ret;
|
||||
ret = register_device(&sdram_dev);
|
||||
if (ret)
|
||||
goto failed;
|
||||
#ifndef CONFIG_CMD_MEMORY
|
||||
ret = register_driver(&ram_drv);
|
||||
if (ret)
|
||||
goto failed;
|
||||
#endif
|
||||
failed:
|
||||
return ret;
|
||||
}
|
||||
device_initcall(beagle_devices_init);
|
||||
Loading…
Reference in New Issue