ARM: socfpga: update sdram calibration to 14.0
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
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24532c33fc
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@ -1,29 +1,30 @@
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/*
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Copyright (c) 2012, Altera Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Altera Corporation nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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* Copyright Altera Corporation (C) 2012-2014. All rights reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Altera Corporation nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <common.h>
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#include <io.h>
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@ -1160,32 +1161,29 @@ static void rw_mgr_mem_initialize (void)
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/* start with memory RESET activated */
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/* tINIT = 200us */
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/*
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* 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
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* If a and b are the number of iteration in 2 nested loops
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* it takes the following number of cycles to complete the operation:
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* number_of_cycles = ((2 + n) * a + 2) * b
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* where n is the number of instruction in the inner loop
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* One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
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* b = 6A
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/* tINIT is typically 200us (but can be adjusted in the GUI)
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* The total number of cycles required for this nested counter structure to
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* complete is defined by:
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* num_cycles = (CTR2 + 1) * [(CTR1 + 1) * (2 * (CTR0 + 1) + 1) + 1] + 1
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*/
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/* Load counters */
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IOWR_32DIRECT(RW_MGR_LOAD_CNTR_0, 0,
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SKIP_DELAY_LOOP_VALUE_OR_ZERO(0xFF));
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SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR0_VAL));
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IOWR_32DIRECT(RW_MGR_LOAD_CNTR_1, 0,
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SKIP_DELAY_LOOP_VALUE_OR_ZERO(0x6A));
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SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR1_VAL));
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IOWR_32DIRECT(RW_MGR_LOAD_CNTR_2, 0,
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SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR2_VAL));
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/* Load jump address */
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IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_0, 0,
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__RW_MGR_INIT_RESET_0_CKE_0);
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IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_1, 0,
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__RW_MGR_INIT_RESET_0_CKE_0_inloop);
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__RW_MGR_INIT_RESET_0_CKE_0);
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IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_2, 0,
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__RW_MGR_INIT_RESET_0_CKE_0);
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/* Execute count instruction */
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/* IOWR_32DIRECT(BASE_RW_MGR, 0, __RW_MGR_COUNT_REG_0); */
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IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_RESET_0_CKE_0);
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/* indicate that memory is stable */
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@ -1194,26 +1192,21 @@ static void rw_mgr_mem_initialize (void)
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/* transition the RESET to high */
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/* Wait for 500us */
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/*
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* 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
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* If a and b are the number of iteration in 2 nested loops
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* it takes the following number of cycles to complete the operation
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* number_of_cycles = ((2 + n) * a + 2) * b
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* where n is the number of instruction in the inner loop
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* One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
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* b = FF
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*/
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/* num_cycles = (CTR2 + 1) * [(CTR1 + 1) * (2 * (CTR0 + 1) + 1) + 1] + 1 */
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/* Load counters */
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IOWR_32DIRECT(RW_MGR_LOAD_CNTR_0, 0,
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SKIP_DELAY_LOOP_VALUE_OR_ZERO(0x83));
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SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR0_VAL));
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IOWR_32DIRECT(RW_MGR_LOAD_CNTR_1, 0,
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SKIP_DELAY_LOOP_VALUE_OR_ZERO(0xFF));
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SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR1_VAL));
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IOWR_32DIRECT(RW_MGR_LOAD_CNTR_2, 0,
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SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR2_VAL));
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/* Load jump address */
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IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_INIT_RESET_1_CKE_0);
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IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_1, 0,
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__RW_MGR_INIT_RESET_1_CKE_0_inloop_1);
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IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_INIT_RESET_1_CKE_0);
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IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_INIT_RESET_1_CKE_0);
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IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_RESET_1_CKE_0);
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@ -1305,27 +1298,28 @@ static void rw_mgr_mem_initialize (void)
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/* tINIT = 200us */
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/* 200us @ 300MHz (3.33 ns) ~ 60000 clock cycles
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* If a and b are the number of iteration in 2 nested loops
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* it takes the following number of cycles to complete the operation:
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* number_of_cycles = ((2 + n) * b + 2) * a
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* where n is the number of instruction in the inner loop
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* One possible solution is n = 0 , a = 256 , b = 118 => a = FF,
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* b = 76
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*/
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/* tINIT is typically 200us (but can be adjusted in the GUI)
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* The total number of cycles required for this nested counter structure to
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* complete is defined by:
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* num_cycles = (CTR0 + 1) * [(CTR1 + 1) * (2 * (CTR2 + 1) + 1) + 1] + 1
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*/
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/*TODO: Need to manage multi-rank */
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/* Load counters */
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IOWR_32DIRECT(RW_MGR_LOAD_CNTR_0, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(0xFF));
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IOWR_32DIRECT(RW_MGR_LOAD_CNTR_1, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(0x76));
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IOWR_32DIRECT(RW_MGR_LOAD_CNTR_0, 0,
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SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR0_VAL));
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IOWR_32DIRECT(RW_MGR_LOAD_CNTR_1, 0,
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SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR1_VAL));
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IOWR_32DIRECT(RW_MGR_LOAD_CNTR_2, 0,
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SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR2_VAL));
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/* Load jump address */
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IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_INIT_CKE_0);
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IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_INIT_CKE_0_inloop);
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IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_INIT_CKE_0);
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IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_INIT_CKE_0);
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/* Execute count instruction */
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/* IOWR_32DIRECT(BASE_RW_MGR, 0, __RW_MGR_COUNT_REG_0); */
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IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_CKE_0);
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/* indicate that memory is stable */
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@ -1717,8 +1711,25 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns (uint32_t rank_bgn,
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static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks
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(uint32_t group, uint32_t num_tries, t_btfld *bit_chk)
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{
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return rw_mgr_mem_calibrate_read_test_patterns (0, group,
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num_tries, bit_chk, 1);
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if (rw_mgr_mem_calibrate_read_test_patterns(0, group, num_tries, bit_chk, 1)) {
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return 1;
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} else {
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/* case:139851 - if guaranteed read fails, we can retry using
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* different dqs enable phases. It is possible that with the
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* initial phase, dqs enable is asserted/deasserted too close
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* to an dqs edge, truncating the read burst.
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*/
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uint32_t p;
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for (p = 0; p <= IO_DQS_EN_PHASE_MAX; p++) {
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scc_mgr_set_dqs_en_phase_all_ranks (group, p);
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if (rw_mgr_mem_calibrate_read_test_patterns(0,
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group, num_tries, bit_chk, 1)) {
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return 1;
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}
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}
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return 0;
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}
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}
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/* load up the patterns we are going to use during a read test */
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@ -4260,6 +4271,7 @@ static int socfpga_sdram_calibration(const uint32_t *inst_rom_init, uint32_t ins
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param_t my_param;
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gbl_t my_gbl;
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uint32_t pass;
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uint32_t i;
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param = &my_param;
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gbl = &my_gbl;
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@ -4280,6 +4292,16 @@ static int socfpga_sdram_calibration(const uint32_t *inst_rom_init, uint32_t ins
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#if USE_DQS_TRACKING
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initialize_tracking();
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#endif
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/* Enable all ranks, groups */
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for (i = 0; i < RW_MGR_MEM_NUMBER_OF_RANKS; i++)
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param->skip_ranks[i] = 0;
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for (i = 0; i < NUM_SHADOW_REGS; ++i)
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param->skip_shadow_regs[i] = 0;
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param->skip_groups = 0;
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pr_debug("Preparing to start memory calibration\n");
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pr_debug("%s%s %s ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u "
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@ -2,31 +2,32 @@
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#define _SEQUENCER_H_
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/*
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Copyright (c) 2012, Altera Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Altera Corporation nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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* Copyright Altera Corporation (C) 2012-2014. All rights reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Altera Corporation nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#define MRS_MIRROR_PING_PONG_ATSO 0
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#define DYNAMIC_CALIBRATION_MODE 0
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@ -396,6 +397,48 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010
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#define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020
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/* Init and Reset delay constants - Only use if defined by sequencer_defines.h,
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* otherwise, revert to defaults
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* Default for Tinit = (0+1) * ((202+1) * (2 * 131 + 1) + 1) = 53532 = 200.75us @ 266MHz
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*/
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#ifdef TINIT_CNTR0_VAL
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#define SEQ_TINIT_CNTR0_VAL TINIT_CNTR0_VAL
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#else
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#define SEQ_TINIT_CNTR0_VAL 0
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#endif
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#ifdef TINIT_CNTR1_VAL
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#define SEQ_TINIT_CNTR1_VAL TINIT_CNTR1_VAL
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#else
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#define SEQ_TINIT_CNTR1_VAL 202
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#endif
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#ifdef TINIT_CNTR2_VAL
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#define SEQ_TINIT_CNTR2_VAL TINIT_CNTR2_VAL
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#else
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#define SEQ_TINIT_CNTR2_VAL 131
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#endif
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/* Default for Treset = (2+1) * ((252+1) * (2 * 131 + 1) + 1) = 133563 = 500.86us @ 266MHz */
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#ifdef TRESET_CNTR0_VAL
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#define SEQ_TRESET_CNTR0_VAL TRESET_CNTR0_VAL
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#else
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#define SEQ_TRESET_CNTR0_VAL 2
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#endif
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#ifdef TRESET_CNTR1_VAL
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#define SEQ_TRESET_CNTR1_VAL TRESET_CNTR1_VAL
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#else
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#define SEQ_TRESET_CNTR1_VAL 252
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#endif
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#ifdef TRESET_CNTR2_VAL
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#define SEQ_TRESET_CNTR2_VAL TRESET_CNTR2_VAL
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#else
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#define SEQ_TRESET_CNTR2_VAL 131
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#endif
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/* Bitfield type changes depending on protocol */
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typedef uint32_t t_btfld;
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@ -409,6 +452,9 @@ typedef struct param_type {
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t_btfld read_correct_mask_vg;
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t_btfld write_correct_mask;
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t_btfld write_correct_mask_vg;
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uint32_t skip_ranks[MAX_RANKS];
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uint32_t skip_groups;
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uint32_t skip_shadow_regs[NUM_SHADOW_REGS];
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/* set a particular entry to 1 if we need to skip a particular group */
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} param_t;
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