arm: implement optimized string functions
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
66457f42e4
commit
270c2673a1
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@ -285,6 +285,14 @@ config ARMCORTEXA8_DCACHE_SKIP
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help
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If your architecture configuration uses some other method of disabling caches, enable this
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So that the D-Cache invalidation logic is skipped
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config ARM_OPTIMZED_STRING_FUNCTIONS
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bool "use assembler optimzed string functions"
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help
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Say yes here to use assembler optimized memcpy / memset functions.
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These functions work much faster than the normal versions but
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increase your binary size.
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endmenu
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source common/Kconfig
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@ -17,6 +17,8 @@ obj-y += io-readsl.o
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obj-y += io-writesb.o
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obj-y += io-writesw-armv4.o
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obj-y += io-writesl.o
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obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS) += memcpy.o
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obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS) += memset.o
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obj-$(CONFIG_MODULES) += module.o
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extra-$(CONFIG_GENERIC_LINKER_SCRIPT) += u-boot.lds
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@ -0,0 +1,248 @@
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/*
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* linux/arch/arm/lib/copy_template.s
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*
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* Code template for optimized memory copy functions
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*
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* Author: Nicolas Pitre
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* Created: Sep 28, 2005
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* Copyright: MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* Theory of operation
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* -------------------
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*
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* This file provides the core code for a forward memory copy used in
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* the implementation of memcopy(), copy_to_user() and copy_from_user().
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*
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* The including file must define the following accessor macros
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* according to the need of the given function:
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*
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* ldr1w ptr reg abort
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*
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* This loads one word from 'ptr', stores it in 'reg' and increments
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* 'ptr' to the next word. The 'abort' argument is used for fixup tables.
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*
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* ldr4w ptr reg1 reg2 reg3 reg4 abort
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* ldr8w ptr, reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
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*
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* This loads four or eight words starting from 'ptr', stores them
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* in provided registers and increments 'ptr' past those words.
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* The'abort' argument is used for fixup tables.
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*
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* ldr1b ptr reg cond abort
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*
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* Similar to ldr1w, but it loads a byte and increments 'ptr' one byte.
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* It also must apply the condition code if provided, otherwise the
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* "al" condition is assumed by default.
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*
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* str1w ptr reg abort
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* str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
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* str1b ptr reg cond abort
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*
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* Same as their ldr* counterparts, but data is stored to 'ptr' location
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* rather than being loaded.
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*
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* enter reg1 reg2
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*
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* Preserve the provided registers on the stack plus any additional
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* data as needed by the implementation including this code. Called
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* upon code entry.
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*
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* exit reg1 reg2
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*
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* Restore registers with the values previously saved with the
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* 'preserv' macro. Called upon code termination.
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*/
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enter r4, lr
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subs r2, r2, #4
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blt 8f
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ands ip, r0, #3
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PLD( pld [r1, #0] )
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bne 9f
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ands ip, r1, #3
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bne 10f
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1: subs r2, r2, #(28)
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stmfd sp!, {r5 - r8}
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blt 5f
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CALGN( ands ip, r0, #31 )
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CALGN( rsb r3, ip, #32 )
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CALGN( sbcnes r4, r3, r2 ) @ C is always set here
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CALGN( bcs 2f )
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CALGN( adr r4, 6f )
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CALGN( subs r2, r2, r3 ) @ C gets set
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CALGN( add pc, r4, ip )
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PLD( pld [r1, #0] )
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2: PLD( subs r2, r2, #96 )
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PLD( pld [r1, #28] )
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PLD( blt 4f )
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PLD( pld [r1, #60] )
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PLD( pld [r1, #92] )
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3: PLD( pld [r1, #124] )
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4: ldr8w r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
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subs r2, r2, #32
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str8w r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
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bge 3b
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PLD( cmn r2, #96 )
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PLD( bge 4b )
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5: ands ip, r2, #28
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rsb ip, ip, #32
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addne pc, pc, ip @ C is always clear here
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b 7f
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6: nop
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ldr1w r1, r3, abort=20f
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ldr1w r1, r4, abort=20f
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ldr1w r1, r5, abort=20f
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ldr1w r1, r6, abort=20f
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ldr1w r1, r7, abort=20f
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ldr1w r1, r8, abort=20f
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ldr1w r1, lr, abort=20f
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add pc, pc, ip
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nop
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nop
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str1w r0, r3, abort=20f
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str1w r0, r4, abort=20f
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str1w r0, r5, abort=20f
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str1w r0, r6, abort=20f
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str1w r0, r7, abort=20f
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str1w r0, r8, abort=20f
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str1w r0, lr, abort=20f
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CALGN( bcs 2b )
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7: ldmfd sp!, {r5 - r8}
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8: movs r2, r2, lsl #31
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ldr1b r1, r3, ne, abort=21f
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ldr1b r1, r4, cs, abort=21f
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ldr1b r1, ip, cs, abort=21f
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str1b r0, r3, ne, abort=21f
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str1b r0, r4, cs, abort=21f
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str1b r0, ip, cs, abort=21f
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exit r4, pc
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9: rsb ip, ip, #4
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cmp ip, #2
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ldr1b r1, r3, gt, abort=21f
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ldr1b r1, r4, ge, abort=21f
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ldr1b r1, lr, abort=21f
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str1b r0, r3, gt, abort=21f
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str1b r0, r4, ge, abort=21f
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subs r2, r2, ip
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str1b r0, lr, abort=21f
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blt 8b
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ands ip, r1, #3
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beq 1b
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10: bic r1, r1, #3
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cmp ip, #2
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ldr1w r1, lr, abort=21f
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beq 17f
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bgt 18f
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.macro forward_copy_shift pull push
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subs r2, r2, #28
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blt 14f
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CALGN( ands ip, r0, #31 )
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CALGN( rsb ip, ip, #32 )
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CALGN( sbcnes r4, ip, r2 ) @ C is always set here
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CALGN( subcc r2, r2, ip )
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CALGN( bcc 15f )
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11: stmfd sp!, {r5 - r9}
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PLD( pld [r1, #0] )
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PLD( subs r2, r2, #96 )
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PLD( pld [r1, #28] )
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PLD( blt 13f )
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PLD( pld [r1, #60] )
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PLD( pld [r1, #92] )
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12: PLD( pld [r1, #124] )
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13: ldr4w r1, r4, r5, r6, r7, abort=19f
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mov r3, lr, pull #\pull
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subs r2, r2, #32
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ldr4w r1, r8, r9, ip, lr, abort=19f
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orr r3, r3, r4, push #\push
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mov r4, r4, pull #\pull
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orr r4, r4, r5, push #\push
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mov r5, r5, pull #\pull
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orr r5, r5, r6, push #\push
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mov r6, r6, pull #\pull
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orr r6, r6, r7, push #\push
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mov r7, r7, pull #\pull
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orr r7, r7, r8, push #\push
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mov r8, r8, pull #\pull
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orr r8, r8, r9, push #\push
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mov r9, r9, pull #\pull
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orr r9, r9, ip, push #\push
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mov ip, ip, pull #\pull
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orr ip, ip, lr, push #\push
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str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f
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bge 12b
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PLD( cmn r2, #96 )
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PLD( bge 13b )
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ldmfd sp!, {r5 - r9}
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14: ands ip, r2, #28
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beq 16f
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15: mov r3, lr, pull #\pull
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ldr1w r1, lr, abort=21f
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subs ip, ip, #4
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orr r3, r3, lr, push #\push
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str1w r0, r3, abort=21f
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bgt 15b
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CALGN( cmp r2, #0 )
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CALGN( bge 11b )
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16: sub r1, r1, #(\push / 8)
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b 8b
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.endm
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forward_copy_shift pull=8 push=24
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17: forward_copy_shift pull=16 push=16
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18: forward_copy_shift pull=24 push=8
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/*
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* Abort preamble and completion macros.
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* If a fixup handler is required then those macros must surround it.
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* It is assumed that the fixup code will handle the private part of
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* the exit macro.
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*/
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.macro copy_abort_preamble
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19: ldmfd sp!, {r5 - r9}
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b 21f
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20: ldmfd sp!, {r5 - r8}
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21:
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.endm
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.macro copy_abort_end
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ldmfd sp!, {r4, pc}
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.endm
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@ -0,0 +1,61 @@
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/*
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* linux/arch/arm/lib/memcpy.S
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*
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* Author: Nicolas Pitre
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* Created: Sep 28, 2005
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* Copyright: MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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.macro ldr1w ptr reg abort
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ldr \reg, [\ptr], #4
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.endm
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.macro ldr4w ptr reg1 reg2 reg3 reg4 abort
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ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
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.endm
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.macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
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ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
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.endm
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.macro ldr1b ptr reg cond=al abort
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ldr\cond\()b \reg, [\ptr], #1
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.endm
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.macro str1w ptr reg abort
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str \reg, [\ptr], #4
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.endm
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.macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
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stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
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.endm
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.macro str1b ptr reg cond=al abort
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str\cond\()b \reg, [\ptr], #1
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.endm
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.macro enter reg1 reg2
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stmdb sp!, {r0, \reg1, \reg2}
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.endm
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.macro exit reg1 reg2
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ldmfd sp!, {r0, \reg1, \reg2}
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.endm
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.text
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/* Prototype: void *memcpy(void *dest, const void *src, size_t n); */
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ENTRY(memcpy)
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#include "copy_template.S"
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ENDPROC(memcpy)
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@ -0,0 +1,128 @@
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/*
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* linux/arch/arm/lib/memset.S
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*
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* Copyright (C) 1995-2000 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* ASM optimised string functions
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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.text
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.align 5
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.word 0
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1: subs r2, r2, #4 @ 1 do we have enough
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blt 5f @ 1 bytes to align with?
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cmp r3, #2 @ 1
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strltb r1, [r0], #1 @ 1
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strleb r1, [r0], #1 @ 1
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strb r1, [r0], #1 @ 1
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add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3))
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/*
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* The pointer is now aligned and the length is adjusted. Try doing the
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* memset again.
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*/
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ENTRY(memset)
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ands r3, r0, #3 @ 1 unaligned?
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bne 1b @ 1
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/*
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* we know that the pointer in r0 is aligned to a word boundary.
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*/
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orr r1, r1, r1, lsl #8
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orr r1, r1, r1, lsl #16
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mov r3, r1
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cmp r2, #16
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blt 4f
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#if ! CALGN(1)+0
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/*
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* We need an extra register for this loop - save the return address and
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* use the LR
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*/
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str lr, [sp, #-4]!
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mov ip, r1
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mov lr, r1
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2: subs r2, r2, #64
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stmgeia r0!, {r1, r3, ip, lr} @ 64 bytes at a time.
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stmgeia r0!, {r1, r3, ip, lr}
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stmgeia r0!, {r1, r3, ip, lr}
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stmgeia r0!, {r1, r3, ip, lr}
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bgt 2b
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ldmeqfd sp!, {pc} @ Now <64 bytes to go.
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/*
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* No need to correct the count; we're only testing bits from now on
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*/
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tst r2, #32
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stmneia r0!, {r1, r3, ip, lr}
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stmneia r0!, {r1, r3, ip, lr}
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tst r2, #16
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stmneia r0!, {r1, r3, ip, lr}
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ldr lr, [sp], #4
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#else
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/*
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* This version aligns the destination pointer in order to write
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* whole cache lines at once.
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*/
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stmfd sp!, {r4-r7, lr}
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mov r4, r1
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mov r5, r1
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mov r6, r1
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mov r7, r1
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mov ip, r1
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mov lr, r1
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cmp r2, #96
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tstgt r0, #31
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ble 3f
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and ip, r0, #31
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rsb ip, ip, #32
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sub r2, r2, ip
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movs ip, ip, lsl #(32 - 4)
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stmcsia r0!, {r4, r5, r6, r7}
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stmmiia r0!, {r4, r5}
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tst ip, #(1 << 30)
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mov ip, r1
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strne r1, [r0], #4
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3: subs r2, r2, #64
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stmgeia r0!, {r1, r3-r7, ip, lr}
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stmgeia r0!, {r1, r3-r7, ip, lr}
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bgt 3b
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ldmeqfd sp!, {r4-r7, pc}
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tst r2, #32
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stmneia r0!, {r1, r3-r7, ip, lr}
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tst r2, #16
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stmneia r0!, {r4-r7}
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ldmfd sp!, {r4-r7, lr}
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#endif
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4: tst r2, #8
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stmneia r0!, {r1, r3}
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tst r2, #4
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strne r1, [r0], #4
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/*
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* When we get here, we've got less than 4 bytes to zero. We
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* may have an unaligned pointer as well.
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*/
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5: tst r2, #2
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strneb r1, [r0], #1
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strneb r1, [r0], #1
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tst r2, #1
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strneb r1, [r0], #1
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mov pc, lr
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ENDPROC(memset)
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@ -1,9 +1,13 @@
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#ifndef __ASM_ARM_STRING_H
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#define __ASM_ARM_STRING_H
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/*
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||||
* We don't do inline string functions, since the
|
||||
* optimised inline asm versions are not small.
|
||||
*/
|
||||
#ifdef CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS
|
||||
|
||||
#define __HAVE_ARCH_MEMCPY
|
||||
extern void *memcpy(void *, const void *, __kernel_size_t);
|
||||
#define __HAVE_ARCH_MEMSET
|
||||
extern void *memset(void *, int, __kernel_size_t);
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue