arm: add vexpress board support
detect the cpu model to dynamise the periphs mapping currently only tested on qemu but should work on real hardware Cortex-A9 if you use 1GiB of ram you can run the same barebox on Cortex-A15 or Cortex-A9 otherwise use vexpress_ca9_defconfig where the TEXT_BASE is at 0x63f00000 when we will add the relocation support this defconfig will be drop qemu/arm-softmmu/qemu-system-arm -M vexpress-a9 -m 1024 -smp 1 -kernel build/vexpress/barebox -pflash build/vexpress/flash0 -nographic Cortex-A15 qemu/arm-softmmu/qemu-system-arm -M vexpress-a15 -m 1024 -smp 1 -kernel build/vexpress/barebox -pflash build/vexpress/flash0 -nographic Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
parent
19905efac5
commit
2738f72352
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@ -105,6 +105,15 @@ config ARCH_VERSATILE
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select CPU_ARM926T
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select GPIOLIB
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config ARCH_VEXPRESS
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bool "ARM Vexpres boards"
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select HAS_DEBUG_LL
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select CPU_V7
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select ARM_AMBA
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select AMBA_SP804
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select CLKDEV_LOOKUP
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select COMMON_CLK
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config ARCH_TEGRA
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bool "Nvidia Tegra-based boards"
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select CPU_ARM926T
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@ -125,6 +134,7 @@ source arch/arm/mach-omap/Kconfig
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source arch/arm/mach-pxa/Kconfig
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source arch/arm/mach-samsung/Kconfig
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source arch/arm/mach-versatile/Kconfig
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source arch/arm/mach-vexpress/Kconfig
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source arch/arm/mach-tegra/Kconfig
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config ARM_ASM_UNIFIED
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@ -63,6 +63,7 @@ machine-$(CONFIG_ARCH_OMAP) := omap
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machine-$(CONFIG_ARCH_PXA) := pxa
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machine-$(CONFIG_ARCH_SAMSUNG) := samsung
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machine-$(CONFIG_ARCH_VERSATILE) := versatile
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machine-$(CONFIG_ARCH_VEXPRESS) := vexpress
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machine-$(CONFIG_ARCH_TEGRA) := tegra
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# Board directory name. This list is sorted alphanumerically
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@ -146,6 +147,7 @@ board-$(CONFIG_MACH_USB_A9260) := usb-a926x
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board-$(CONFIG_MACH_USB_A9263) := usb-a926x
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board-$(CONFIG_MACH_USB_A9G20) := usb-a926x
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board-$(CONFIG_MACH_VERSATILEPB) := versatile
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board-$(CONFIG_MACH_VEXPRESS) := vexpress
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board-$(CONFIG_MACH_TX25) := karo-tx25
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board-$(CONFIG_MACH_TQMA53) := tqma53
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board-$(CONFIG_MACH_TX51) := karo-tx51
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@ -0,0 +1,10 @@
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if MACH_VERSATILEPB
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config ARCH_TEXT_BASE
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hex
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default 0x01000000
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config BOARDINFO
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default "ARM Versatile/PB (ARM926EJ-S)"
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endif
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@ -0,0 +1,4 @@
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obj-y += init.o
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obj-y += lowlevel.o
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pbl-y += lowlevel.o
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@ -0,0 +1,5 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#endif /* __CONFIG_H */
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@ -0,0 +1,40 @@
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#!/bin/sh
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# use 'dhcp' to do dhcp in barebox and in kernel
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# use 'none' if you want to skip kernel ip autoconfiguration
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ip=dhcp
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# set in c
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#global.hostname=vexpress
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global.dhcp.vendor_id=barebox-${global.hostname}
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# or set your networking parameters here
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#eth0.ipaddr=a.b.c.d
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#eth0.netmask=a.b.c.d
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#eth0.gateway=a.b.c.d
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#eth0.serverip=a.b.c.d
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# can be either 'nfs', 'tftp' or 'nor'
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kernel_loc=tftp
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# can be either 'net', 'nor' or 'initrd'
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rootfs_loc=initrd
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# can be either 'jffs2' or 'ubifs'
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rootfs_type=ubifs
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rootfsimage=root.$rootfs_type
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kernelimage=zImage
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#kernelimage=uImage
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#kernelimage=Image
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#kernelimage=Image.lzo
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nfsroot="$eth0.serverip:/opt/work/busybox/arm9/rootfs_arm"
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nor_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)"
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rootfs_mtdblock_nor=3
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autoboot_timeout=3
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bootargs="console=ttyAMA0,115200n8 CONSOLE=/dev/ttyAMA0"
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# set a fancy prompt (if support is compiled in)
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PS1="\e[1;31m[barebox@\h]:\w\e[0m\n# "
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@ -0,0 +1,142 @@
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/*
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* Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
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*
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* GPLv2 only
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*/
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#include <common.h>
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#include <init.h>
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#include <asm/armlinux.h>
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#include <asm/system_info.h>
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#include <generated/mach-types.h>
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#include <mach/devices.h>
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#include <environment.h>
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#include <partition.h>
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#include <sizes.h>
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#include <io.h>
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#include <globalvar.h>
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struct vexpress_init {
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void (*core_init)(void);
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void (*mem_init)(void);
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void (*console_init)(void);
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void (*devices_init)(void);
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char *hostname;
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};
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struct vexpress_init *v2m_init;
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static void vexpress_ax_mem_init(void)
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{
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vexpress_add_ddram(SZ_512M);
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}
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#define V2M_SYS_FLASH 0x03c
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static void vexpress_ax_devices_init(void)
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{
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add_cfi_flash_device(0, 0x08000000, SZ_64M, 0);
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add_cfi_flash_device(1, 0x0c000000, SZ_64M, 0);
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add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, 0x1a000000,
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64 * 1024, IORESOURCE_MEM, NULL);
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armlinux_set_bootparams((void *)(0x80000100));
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}
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static void vexpress_ax_console_init(void)
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{
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vexpress_register_uart(0);
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vexpress_register_uart(1);
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vexpress_register_uart(2);
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vexpress_register_uart(3);
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}
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struct vexpress_init vexpress_init_ax = {
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.core_init = vexpress_init,
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.mem_init = vexpress_ax_mem_init,
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.console_init = vexpress_ax_console_init,
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.devices_init = vexpress_ax_devices_init,
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};
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static void vexpress_a9_mem_init(void)
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{
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vexpress_a9_add_ddram(SZ_512M, SZ_512M);
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}
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static void vexpress_a9_devices_init(void)
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{
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add_cfi_flash_device(0, 0x40000000, SZ_64M, 0);
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add_cfi_flash_device(1, 0x44000000, SZ_64M, 0);
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add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, 0x4e000000,
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64 * 1024, IORESOURCE_MEM, NULL);
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armlinux_set_architecture(MACH_TYPE_VEXPRESS);
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armlinux_set_bootparams((void *)(0x60000100));
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}
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static void vexpress_a9_console_init(void)
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{
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vexpress_a9_register_uart(0);
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vexpress_a9_register_uart(1);
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vexpress_a9_register_uart(2);
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vexpress_a9_register_uart(3);
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}
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struct vexpress_init vexpress_init_a9 = {
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.core_init = vexpress_a9_init,
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.mem_init = vexpress_a9_mem_init,
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.console_init = vexpress_a9_console_init,
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.devices_init = vexpress_a9_devices_init,
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.hostname = "vexpress-a9",
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};
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static int vexpress_mem_init(void)
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{
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v2m_init->mem_init();
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return 0;
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}
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mem_initcall(vexpress_mem_init);
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static int vexpress_devices_init(void)
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{
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writel(1, v2m_sysreg_base + V2M_SYS_FLASH);
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v2m_init->devices_init();
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devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self");
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devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
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globalvar_add_simple("hostname");
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setenv("global.hostname", v2m_init->hostname);
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return 0;
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}
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device_initcall(vexpress_devices_init);
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static int vexpress_console_init(void)
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{
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v2m_init->console_init();
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return 0;
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}
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console_initcall(vexpress_console_init);
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static int vexpress_core_init(void)
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{
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if (cpu_is_cortex_a9()) {
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v2m_init = &vexpress_init_a9;
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} else {
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v2m_init = &vexpress_init_ax;
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if (cpu_is_cortex_a5())
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v2m_init->hostname = "vexpress-a5";
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else if (cpu_is_cortex_a7())
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v2m_init->hostname = "vexpress-a7";
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else if (cpu_is_cortex_a15())
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v2m_init->hostname = "vexpress-a15";
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}
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v2m_init->core_init();
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return 0;
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}
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postcore_initcall(vexpress_core_init);
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@ -0,0 +1,21 @@
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/*
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* Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
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*
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* GPLv2 only
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*/
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#include <common.h>
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#include <sizes.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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#include <asm/system_info.h>
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void __naked barebox_arm_reset_vector(void)
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{
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arm_cpu_lowlevel_init();
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if (cpu_is_cortex_a9())
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barebox_arm_entry(0x60000000, SZ_512M, 0);
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else
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barebox_arm_entry(0x80000000, SZ_512M, 0);
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}
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@ -0,0 +1,61 @@
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CONFIG_ARCH_VEXPRESS=y
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CONFIG_MACH_VEXPRESS
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CONFIG_AEABI=y
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CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
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CONFIG_TEXT_BASE=0x63f00000
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CONFIG_MALLOC_TLSF=y
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CONFIG_PROMPT="vexpress: "
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CONFIG_LONGHELP=y
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CONFIG_GLOB=y
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CONFIG_HUSH_FANCY_PROMPT=y
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CONFIG_CMDLINE_EDITING=y
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CONFIG_AUTO_COMPLETE=y
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CONFIG_MENU=y
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CONFIG_PARTITION=y
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CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
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CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/vexpress/env"
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CONFIG_CMD_EDIT=y
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CONFIG_CMD_SLEEP=y
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CONFIG_CMD_SAVEENV=y
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CONFIG_CMD_EXPORT=y
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CONFIG_CMD_PRINTENV=y
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CONFIG_CMD_READLINE=y
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CONFIG_CMD_MENU=y
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CONFIG_CMD_MENU_MANAGEMENT=y
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CONFIG_CMD_PASSWD=y
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CONFIG_CMD_TFTP=y
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CONFIG_CMD_ECHO_E=y
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CONFIG_CMD_LOADB=y
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CONFIG_CMD_MEMINFO=y
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CONFIG_CMD_BOOTM_SHOW_TYPE=y
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CONFIG_CMD_BOOTM_VERBOSE=y
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CONFIG_CMD_BOOTM_INITRD=y
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CONFIG_CMD_BOO
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CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
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CONFIG_CMD_UIMAGE=y
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# CONFIG_CMD_BOOTU is not set
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CONFIG_CMD_RESET=y
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CONFIG_CMD_GO=y
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CONFIG_CMD_OFTREE=y
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CONFIG_CMD_MTEST=y
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CONFIG_CMD_MTEST_ALTERNATIVE=y
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CONFIG_CMD_TIMEOUT=y
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CONFIG_CMD_PARTITION=y
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CONFIG_CMD_UNCOMPRESS=y
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CONFIG_CMD_CLK=y
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CONFIG_NET=y
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CONFIG_NET_DHCP=y
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CONFIG_NET_NFS=y
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CONFIG_NET_PING=y
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CONFIG_NET_NETCONSOLE=y
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CONFIG_NET_RESOLV=y
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CONFIG_SERIAL_AMBA_PL011=y
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CONFIG_DRIVER_NET_SMC91111=y
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# CONFIG_SPI is not set
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CONFIG_DRIVER_CFI=y
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# CONFIG_DRIVER_CFI_AMD is not set
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# CONFIG_DRIVER_CFI_BANK_WIDTH_1 is not set
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# CONFIG_DRIVER_CFI_BANK_WIDTH_2 is not set
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CONFIG_FS_TFTP=y
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CONFIG_SHA1=y
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CONFIG_SHA256=y
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@ -0,0 +1,60 @@
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CONFIG_ARCH_VEXPRESS=y
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CONFIG_MACH_VEXPRESS
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CONFIG_AEABI=y
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CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
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CONFIG_MALLOC_TLSF=y
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CONFIG_PROMPT="vexpress: "
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CONFIG_LONGHELP=y
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CONFIG_GLOB=y
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CONFIG_HUSH_FANCY_PROMPT=y
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CONFIG_CMDLINE_EDITING=y
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CONFIG_AUTO_COMPLETE=y
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CONFIG_MENU=y
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CONFIG_PARTITION=y
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CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
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CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/vexpress/env"
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CONFIG_CMD_EDIT=y
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CONFIG_CMD_SLEEP=y
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CONFIG_CMD_SAVEENV=y
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CONFIG_CMD_EXPORT=y
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CONFIG_CMD_PRINTENV=y
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CONFIG_CMD_READLINE=y
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CONFIG_CMD_MENU=y
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CONFIG_CMD_MENU_MANAGEMENT=y
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CONFIG_CMD_PASSWD=y
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CONFIG_CMD_TFTP=y
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CONFIG_CMD_ECHO_E=y
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CONFIG_CMD_LOADB=y
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CONFIG_CMD_MEMINFO=y
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CONFIG_CMD_BOOTM_SHOW_TYPE=y
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CONFIG_CMD_BOOTM_VERBOSE=y
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CONFIG_CMD_BOOTM_INITRD=y
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CONFIG_CMD_BOO
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CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
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CONFIG_CMD_UIMAGE=y
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# CONFIG_CMD_BOOTU is not set
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CONFIG_CMD_RESET=y
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CONFIG_CMD_GO=y
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CONFIG_CMD_OFTREE=y
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CONFIG_CMD_MTEST=y
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CONFIG_CMD_MTEST_ALTERNATIVE=y
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CONFIG_CMD_TIMEOUT=y
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CONFIG_CMD_PARTITION=y
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CONFIG_CMD_UNCOMPRESS=y
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CONFIG_CMD_CLK=y
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CONFIG_NET=y
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CONFIG_NET_DHCP=y
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CONFIG_NET_NFS=y
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CONFIG_NET_PING=y
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CONFIG_NET_NETCONSOLE=y
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CONFIG_NET_RESOLV=y
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CONFIG_SERIAL_AMBA_PL011=y
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CONFIG_DRIVER_NET_SMC91111=y
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# CONFIG_SPI is not set
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CONFIG_DRIVER_CFI=y
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# CONFIG_DRIVER_CFI_AMD is not set
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# CONFIG_DRIVER_CFI_BANK_WIDTH_1 is not set
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# CONFIG_DRIVER_CFI_BANK_WIDTH_2 is not set
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CONFIG_FS_TFTP=y
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CONFIG_SHA1=y
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CONFIG_SHA256=y
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@ -12,7 +12,12 @@
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*
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* Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview
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* can have 16-bit or 32-bit selectable via a bit in the control register.
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*
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* Every SP804 contains two identical timers.
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*/
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#define TIMER_1_BASE 0x00
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#define TIMER_2_BASE 0x20
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#define TIMER_LOAD 0x00 /* ACVR rw */
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#define TIMER_VALUE 0x04 /* ACVR ro */
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#define TIMER_CTRL 0x08 /* ACVR rw */
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@ -0,0 +1,68 @@
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/*
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* arch/arm/include/asm/hardware/sp810.h
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*
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* ARM PrimeXsys System Controller SP810 header file
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*
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* Copyright (C) 2009 ST Microelectronics
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* Viresh Kumar <viresh.linux@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARM_SP810_H
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#define __ASM_ARM_SP810_H
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#include <io.h>
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/* sysctl registers offset */
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#define SCCTRL 0x000
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#define SCSYSSTAT 0x004
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#define SCIMCTRL 0x008
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#define SCIMSTAT 0x00C
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#define SCXTALCTRL 0x010
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#define SCPLLCTRL 0x014
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#define SCPLLFCTRL 0x018
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#define SCPERCTRL0 0x01C
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#define SCPERCTRL1 0x020
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#define SCPEREN 0x024
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#define SCPERDIS 0x028
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#define SCPERCLKEN 0x02C
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#define SCPERSTAT 0x030
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#define SCSYSID0 0xEE0
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#define SCSYSID1 0xEE4
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#define SCSYSID2 0xEE8
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#define SCSYSID3 0xEEC
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#define SCITCR 0xF00
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#define SCITIR0 0xF04
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||||
#define SCITIR1 0xF08
|
||||
#define SCITOR 0xF0C
|
||||
#define SCCNTCTRL 0xF10
|
||||
#define SCCNTDATA 0xF14
|
||||
#define SCCNTSTEP 0xF18
|
||||
#define SCPERIPHID0 0xFE0
|
||||
#define SCPERIPHID1 0xFE4
|
||||
#define SCPERIPHID2 0xFE8
|
||||
#define SCPERIPHID3 0xFEC
|
||||
#define SCPCELLID0 0xFF0
|
||||
#define SCPCELLID1 0xFF4
|
||||
#define SCPCELLID2 0xFF8
|
||||
#define SCPCELLID3 0xFFC
|
||||
|
||||
#define SCCTRL_TIMEREN0SEL_REFCLK (0 << 15)
|
||||
#define SCCTRL_TIMEREN0SEL_TIMCLK (1 << 15)
|
||||
|
||||
#define SCCTRL_TIMEREN1SEL_REFCLK (0 << 17)
|
||||
#define SCCTRL_TIMEREN1SEL_TIMCLK (1 << 17)
|
||||
|
||||
static inline void sysctl_soft_reset(void __iomem *base)
|
||||
{
|
||||
/* switch to slow mode */
|
||||
writel(0x2, base + SCCTRL);
|
||||
|
||||
/* writing any value to SCSYSSTAT reg will reset system */
|
||||
writel(0, base + SCSYSSTAT);
|
||||
}
|
||||
|
||||
#endif /* __ASM_ARM_SP810_H */
|
|
@ -0,0 +1,18 @@
|
|||
if ARCH_VEXPRESS
|
||||
|
||||
config ARCH_TEXT_BASE
|
||||
hex
|
||||
default 0x83f00000
|
||||
|
||||
config BOARDINFO
|
||||
default "ARM Vexpress" if MACH_VEXPRESS
|
||||
|
||||
choice
|
||||
prompt "ARM Board type"
|
||||
|
||||
config MACH_VEXPRESS
|
||||
bool "ARM Vexpress"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
|
@ -0,0 +1,3 @@
|
|||
obj-y += v2m.o
|
||||
obj-y += devices.o
|
||||
obj-y += reset.o
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
|
||||
*
|
||||
* GPLv2 only
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#include <linux/amba/bus.h>
|
||||
|
||||
#include <asm/memory.h>
|
||||
|
||||
#include <mach/devices.h>
|
||||
|
||||
void vexpress_a9_add_ddram(u32 ddr0_size, u32 ddr1_size)
|
||||
{
|
||||
arm_add_mem_device("ram0", 0x60000000, ddr0_size);
|
||||
|
||||
if (ddr1_size)
|
||||
arm_add_mem_device("ram1", 0x80000000, ddr1_size);
|
||||
}
|
||||
|
||||
|
||||
void vexpress_a9_register_uart(unsigned id)
|
||||
{
|
||||
resource_size_t start;
|
||||
|
||||
switch (id) {
|
||||
case 0:
|
||||
start = 0x10009000;
|
||||
break;
|
||||
case 1:
|
||||
start = 0x1000a000;
|
||||
break;
|
||||
case 2:
|
||||
start = 0x1000b000;
|
||||
break;
|
||||
case 3:
|
||||
start = 0x1000c000;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
amba_apb_device_add(NULL, "uart-pl011", id, start, 4096, NULL, 0);
|
||||
}
|
||||
|
||||
void vexpress_add_ddram(u32 size)
|
||||
{
|
||||
arm_add_mem_device("ram1", 0x80000000, size);
|
||||
}
|
||||
|
||||
void vexpress_register_uart(unsigned id)
|
||||
{
|
||||
resource_size_t start;
|
||||
|
||||
switch (id) {
|
||||
case 0:
|
||||
start = 0x1c090000;
|
||||
break;
|
||||
case 1:
|
||||
start = 0x1c0a0000;
|
||||
break;
|
||||
case 2:
|
||||
start = 0x1c0b0000;
|
||||
break;
|
||||
case 3:
|
||||
start = 0x1c0c0000;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
amba_apb_device_add(NULL, "uart-pl011", id, start, 4096, NULL, 0);
|
||||
}
|
|
@ -0,0 +1,7 @@
|
|||
#ifndef __ASM_MACH_CLKDEV_H
|
||||
#define __ASM_MACH_CLKDEV_H
|
||||
|
||||
#define __clk_get(clk) ({ 1; })
|
||||
#define __clk_put(clk) do { } while (0)
|
||||
|
||||
#endif
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Copyright 2013 Jean-Christophe PLAGNIOL-VILLARD <plagniol@jcrosoft.com>
|
||||
*
|
||||
* GPLv2 only
|
||||
*/
|
||||
|
||||
#ifndef __MACH_DEBUG_LL_H__
|
||||
#define __MACH_DEBUG_LL_H__
|
||||
|
||||
#include <linux/amba/serial.h>
|
||||
#include <io.h>
|
||||
|
||||
#define DEBUG_LL_PHYS_BASE 0x10000000
|
||||
#define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
|
||||
|
||||
#ifdef MP
|
||||
#define UART_BASE DEBUG_LL_PHYS_BASE
|
||||
#else
|
||||
#define UART_BASE DEBUG_LL_PHYS_BASE_RS1
|
||||
#endif
|
||||
|
||||
static inline void PUTC_LL(char c)
|
||||
{
|
||||
/* Wait until there is space in the FIFO */
|
||||
while (readl(UART_BASE + UART01x_FR) & UART01x_FR_TXFF);
|
||||
|
||||
/* Send the character */
|
||||
writel(c, UART_BASE + UART01x_DR);
|
||||
|
||||
/* Wait to make sure it hits the line, in case we die too soon. */
|
||||
while (readl(UART_BASE + UART01x_FR) & UART01x_FR_TXFF);
|
||||
}
|
||||
#endif
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
|
||||
*
|
||||
* GPLv2 only
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_DEVICES_H__
|
||||
#define __ASM_ARCH_DEVICES_H__
|
||||
|
||||
void vexpress_a9_add_ddram(u32 ddr0_size, u32 ddr1_size);
|
||||
void vexpress_add_ddram(u32 size);
|
||||
|
||||
void vexpress_a9_register_uart(unsigned id);
|
||||
void vexpress_register_uart(unsigned id);
|
||||
|
||||
void vexpress_a9_init(void);
|
||||
void vexpress_init(void);
|
||||
|
||||
extern void *v2m_wdt_base;
|
||||
extern void *v2m_sysreg_base;
|
||||
|
||||
#endif /* __ASM_ARCH_DEVICES_H__ */
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
|
||||
*
|
||||
* GPLv2 only
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <io.h>
|
||||
#include <linux/amba/sp805.h>
|
||||
|
||||
#include <mach/devices.h>
|
||||
|
||||
void __iomem *v2m_wdt_base;
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
writel(LOAD_MIN, v2m_wdt_base + WDTLOAD);
|
||||
writeb(RESET_ENABLE, v2m_wdt_base + WDTCONTROL);
|
||||
|
||||
while (1)
|
||||
;
|
||||
}
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
|
||||
*
|
||||
* GPLv2 only
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <io.h>
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/amba/bus.h>
|
||||
|
||||
#include <asm/hardware/arm_timer.h>
|
||||
#include <asm/hardware/sp810.h>
|
||||
|
||||
#include <mach/devices.h>
|
||||
|
||||
void __iomem *v2m_sysreg_base;
|
||||
|
||||
static const char *v2m_osc2_periphs[] = {
|
||||
"mb:uart0", "uart-pl0110", /* PL011 UART0 */
|
||||
"mb:uart1", "uart-pl0111", /* PL011 UART1 */
|
||||
"mb:uart2", "uart-pl0112", /* PL011 UART2 */
|
||||
"mb:uart3", "uart-pl0113", /* PL011 UART3 */
|
||||
};
|
||||
|
||||
static void v2m_clk_init(void)
|
||||
{
|
||||
struct clk *clk;
|
||||
int i;
|
||||
|
||||
clk = clk_fixed("dummy_apb_pclk", 0);
|
||||
clk_register_clkdev(clk, "apb_pclk", NULL);
|
||||
|
||||
clk = clk_fixed("mb:sp804_clk", 1000000);
|
||||
clk_register_clkdev(clk, NULL, "sp804");
|
||||
|
||||
clk = clk_fixed("mb:osc2", 24000000);
|
||||
for (i = 0; i < ARRAY_SIZE(v2m_osc2_periphs); i++)
|
||||
clk_register_clkdev(clk, NULL, v2m_osc2_periphs[i]);
|
||||
|
||||
}
|
||||
|
||||
static void v2m_sysctl_init(void __iomem *base)
|
||||
{
|
||||
u32 scctrl;
|
||||
|
||||
if (WARN_ON(!base))
|
||||
return;
|
||||
|
||||
/* Select 1MHz TIMCLK as the reference clock for SP804 timers */
|
||||
scctrl = readl(base + SCCTRL);
|
||||
scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;
|
||||
scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK;
|
||||
writel(scctrl, base + SCCTRL);
|
||||
}
|
||||
|
||||
static void __init v2m_sp804_init(void __iomem *base)
|
||||
{
|
||||
writel(0, base + TIMER_1_BASE + TIMER_CTRL);
|
||||
|
||||
amba_apb_device_add(NULL, "sp804", DEVICE_ID_SINGLE, (resource_size_t)base, 4096, NULL, 0);
|
||||
}
|
||||
|
||||
void vexpress_a9_init(void)
|
||||
{
|
||||
v2m_wdt_base = IOMEM(0x1000f000);
|
||||
v2m_sysreg_base = IOMEM(0x10001000);
|
||||
v2m_sysctl_init(IOMEM(0x10001000));
|
||||
v2m_clk_init();
|
||||
|
||||
v2m_sp804_init(IOMEM(0x10011000));
|
||||
}
|
||||
|
||||
void vexpress_init(void)
|
||||
{
|
||||
v2m_wdt_base = IOMEM(0x1c0f0000);
|
||||
v2m_sysreg_base = IOMEM(0x1c020000);
|
||||
v2m_sysctl_init(IOMEM(0x1c020000));
|
||||
v2m_clk_init();
|
||||
|
||||
v2m_sp804_init(IOMEM(0x1c110000));
|
||||
}
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Watchdog driver for ARM SP805 watchdog module
|
||||
*
|
||||
* Copyright (C) 2010 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2 or later. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __AMBA_SP805_H__
|
||||
#define __AMBA_SP805_H__
|
||||
|
||||
/* watchdog register offsets and masks */
|
||||
#define WDTLOAD 0x000
|
||||
#define LOAD_MIN 0x00000001
|
||||
#define LOAD_MAX 0xFFFFFFFF
|
||||
#define WDTVALUE 0x004
|
||||
#define WDTCONTROL 0x008
|
||||
/* control register masks */
|
||||
#define INT_ENABLE (1 << 0)
|
||||
#define RESET_ENABLE (1 << 1)
|
||||
#define WDTINTCLR 0x00C
|
||||
#define WDTRIS 0x010
|
||||
#define WDTMIS 0x014
|
||||
#define INT_MASK (1 << 0)
|
||||
#define WDTLOCK 0xC00
|
||||
#define UNLOCK 0x1ACCE551
|
||||
#define LOCK 0x00000001
|
||||
|
||||
#endif /* __AMBA_SP805_H__ */
|
Loading…
Reference in New Issue