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ARM: use unconditional branch in exception vectors 

If we want to trap the processer in the exception vectors
we have to use unconditional branch instructions. I don't
know what I thought when using bne :-/

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer 2012-03-06 09:38:39 +01:00
parent 104a6a7ccf
commit 276252a559
1 changed files with 8 additions and 8 deletions
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16
arch/arm/cpu/start.c
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@ -43,17 +43,17 @@ void __naked __section(.text_exceptions) exception_vectors(void)
"ldr pc, =software_interrupt\n" /* software interrupt (SWI) */
"ldr pc, =prefetch_abort\n" /* prefetch abort */
"ldr pc, =data_abort\n" /* data abort */
"1: bne 1b\n" /* (reserved) */
"1: b 1b\n" /* (reserved) */
"ldr pc, =irq\n" /* irq (interrupt) */
"ldr pc, =fiq\n" /* fiq (fast interrupt) */
#else
"1: bne 1b\n" /* undefined instruction */
"1: bne 1b\n" /* software interrupt (SWI) */
"1: bne 1b\n" /* prefetch abort */
"1: bne 1b\n" /* data abort */
"1: bne 1b\n" /* (reserved) */
"1: bne 1b\n" /* irq (interrupt) */
"1: bne 1b\n" /* fiq (fast interrupt) */
"1: b 1b\n" /* undefined instruction */
"1: b 1b\n" /* software interrupt (SWI) */
"1: b 1b\n" /* prefetch abort */
"1: b 1b\n" /* data abort */
"1: b 1b\n" /* (reserved) */
"1: b 1b\n" /* irq (interrupt) */
"1: b 1b\n" /* fiq (fast interrupt) */
#endif
);
}