pcm038: initialize PLLs in one step
We used to initialize the PLLs on PCM038 in two steps. The first was to initialize a basic setup so that all peripheral clocks run at their final speed and the second step was to push the processor to full speed after the PMIC has been initialized for the higher voltage. Do this in one step instead to get an easier setup. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
c651bda2d5
commit
287700795c
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@ -104,6 +104,9 @@ config MACH_PCM038
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select HAS_CFI
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select ARCH_IMX27
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select MACH_HAS_LOWLEVEL_INIT
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select SPI
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select DRIVER_SPI_IMX
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select DRIVER_SPI_MC13783
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help
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Say Y here if you are using Phytec's phyCORE-i.MX27 (pcm038) equipped
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with a Freescale i.MX27 Processor
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@ -25,6 +25,7 @@
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#include <environment.h>
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#include <asm/arch/imx-regs.h>
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#include <fec.h>
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#include <notifier.h>
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#include <asm/arch/gpio.h>
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#include <asm/armlinux.h>
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#include <asm/mach-types.h>
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@ -110,9 +111,6 @@ static struct device_d nand_dev = {
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static int pcm038_devices_init(void)
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{
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int i;
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struct device_d *nand, *dev;
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char *envdev = "no";
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unsigned int mode[] = {
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PD0_AIN_FEC_TXD0,
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PD1_AIN_FEC_TXD1,
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@ -164,17 +162,100 @@ static int pcm038_devices_init(void)
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for (i = 0; i < ARRAY_SIZE(mode); i++)
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imx_gpio_mode(mode[i]);
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PCCR0 |= PCCR0_CSPI1_EN;
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PCCR1 |= PCCR1_PERCLK2_EN;
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spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info));
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register_device(&spi_dev);
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return 0;
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}
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device_initcall(pcm038_devices_init);
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static struct device_d pcm038_serial_device = {
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.name = "imx_serial",
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.id = "cs0",
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.map_base = IMX_UART1_BASE,
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.size = 4096,
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.type = DEVICE_TYPE_CONSOLE,
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};
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static int pcm038_power_init(void)
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{
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struct device_d *nand, *dev;
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char *envdev = "no";
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int i = 0;
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int ret;
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ret = pmic_power();
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if (ret)
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goto out;
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/* wait for good power level */
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udelay(1000);
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#define CSCR_VAL CSCR_USB_DIV(3) | \
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CSCR_SD_CNT(3) | \
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CSCR_MSHC_SEL | \
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CSCR_H264_SEL | \
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CSCR_SSI1_SEL | \
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CSCR_SSI2_SEL | \
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CSCR_MCU_SEL | \
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CSCR_ARM_SRC_MPLL | \
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CSCR_SP_SEL | \
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CSCR_ARM_DIV(0) | \
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CSCR_FPM_EN | \
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CSCR_SPEN | \
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CSCR_MPEN
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CSCR &= ~CSCR_MCU_SEL;
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/*
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* pll clock initialization - see section 3.4.3 of the i.MX27 manual
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*/
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MPCTL0 = IMX_PLL_PD(0) |
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IMX_PLL_MFD(51) |
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IMX_PLL_MFI(7) |
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IMX_PLL_MFN(35); /* MPLL = 2 * 26 * 3.83654 MHz = 199.5 MHz */
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SPCTL0 = IMX_PLL_PD(1) |
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IMX_PLL_MFD(12) |
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IMX_PLL_MFI(9) |
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IMX_PLL_MFN(3); /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
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/*
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* ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz
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* AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz
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* System clock (HCLK) = 133 MHz
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*/
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CSCR = CSCR_VAL | CSCR_AHB_DIV(1) | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART;
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udelay(1000);
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/* clock gating enable */
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GPCR = 0x00050f08;
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PCDR0 = 0x130410c3;
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PCDR1 = 0x09030911;
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/* Clocks have changed. Notify clients */
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clock_notifier_call_chain();
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out:
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register_device(&pcm038_serial_device);
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register_device(&cfi_dev);
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register_device(&nand_dev);
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register_device(&sdram_dev);
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#if 0
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register_device(&sram_dev);
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#endif
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PCCR0 |= PCCR0_CSPI1_EN;
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PCCR1 |= PCCR1_PERCLK2_EN;
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spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info));
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register_device(&spi_dev);
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/* Register the fec device after the PLL re-initialisation
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* as the fec depends on the (now higher) ipg clock
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*/
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register_device(&fec_dev);
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switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) {
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case GPCR_BOOT_8BIT_NAND_2k:
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@ -210,67 +291,6 @@ static int pcm038_devices_init(void)
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return 0;
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}
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device_initcall(pcm038_devices_init);
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static struct device_d pcm038_serial_device = {
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.name = "imx_serial",
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.id = "cs0",
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.map_base = IMX_UART1_BASE,
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.size = 4096,
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.type = DEVICE_TYPE_CONSOLE,
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};
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static int pcm038_console_init(void)
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{
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register_device(&pcm038_serial_device);
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return 0;
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}
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console_initcall(pcm038_console_init);
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static int pcm038_power_init(void)
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{
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#ifdef CONFIG_DRIVER_SPI_MC13783
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int i = 0;
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int ret;
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ret = pmic_power();
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if (ret)
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goto out;
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CSCR |= CSCR_UPDATE_DIS;
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MPCTL0 = IMX_PLL_PD(0) |
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IMX_PLL_MFD(51) |
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IMX_PLL_MFI(7) |
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IMX_PLL_MFN(35);
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/* wait for good power level */
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while (i++ < 128) {
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while (CCSR & CCSR_32K_SR);
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while (!(CCSR & CCSR_32K_SR));
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}
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i = 0;
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CSCR |= CSCR_MPLL_RESTART;
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while (!(MPCTL1 & MPCTL1_LF));
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PCDR1 = 0x09030911;
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out:
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#else
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#warning no pmic support enabled. your pcm038 will run on low speed
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#endif
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/* Register the fec device after the PLL re-initialisation
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* as the fec depends on the (now higher) ipg clock
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*/
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register_device(&fec_dev);
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return 0;
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}
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late_initcall(pcm038_power_init);
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#ifdef CONFIG_NAND_IMX_BOOT
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@ -280,61 +300,3 @@ void __bare_init nand_boot(void)
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}
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#endif
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static int pll_init(void)
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{
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int i = 0;
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#define CSCR_VAL CSCR_USB_DIV(3) | \
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CSCR_SD_CNT(3) | \
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CSCR_MSHC_SEL | \
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CSCR_H264_SEL | \
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CSCR_SSI1_SEL | \
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CSCR_SSI2_SEL | \
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CSCR_MCU_SEL | \
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CSCR_SP_SEL | \
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CSCR_ARM_SRC_MPLL | \
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CSCR_ARM_DIV(0) | \
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CSCR_FPM_EN | \
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CSCR_SPEN | \
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CSCR_MPEN
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CSCR = CSCR_VAL | CSCR_AHB_DIV(3);
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/*
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* pll clock initialization - see section 3.4.3 of the i.MX27 manual
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*/
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MPCTL0 = IMX_PLL_PD(1) |
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IMX_PLL_MFD(51) |
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IMX_PLL_MFI(7) |
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IMX_PLL_MFN(35); /* MPLL = 2 * 26 * 3.83654 MHz = 199.5 MHz */
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SPCTL0 = IMX_PLL_PD(1) |
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IMX_PLL_MFD(12) |
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IMX_PLL_MFI(9) |
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IMX_PLL_MFN(3); /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
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/*
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* ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz
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* AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz
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* System clock (HCLK) = 133 MHz
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*/
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CSCR = CSCR_VAL | CSCR_AHB_DIV(1) | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART;
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while (i++ < 1000) {
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while (CCSR & CCSR_32K_SR);
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while (!(CCSR & CCSR_32K_SR));
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}
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/* clock gating enable */
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GPCR = 0x00050f08;
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/* peripheral clock divider */
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PCDR0 = 0x130410c3; /* FIXME */
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PCDR1 = 0x09030908; /* PERDIV1=08 @133 MHz */
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return 0;
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}
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core_initcall(pll_init);
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