Merge branch 'for-next/imx'
This commit is contained in:
Sascha Hauer
commit
2a2a8b9052
|
|
@ -0,0 +1,13 @@
|
|||
KaRo TX6x
|
||||
=========
|
||||
|
||||
This CPU cards are based on a Freescale i.MX6 SoC.
|
||||
There are currently six variants of this module, that are distinguished
|
||||
by the suffix: 'Q' use an i.MX6Q and 'U' an i.MX6DL.
|
||||
|
||||
The TX6U-801x modules are shipped with:
|
||||
|
||||
* 128MiB NAND flash
|
||||
* 1024MiB DDR3 SDRAM
|
||||
|
||||
see http://www.karo-electronics.de/tx6.html for more information
|
||||
|
|
@ -49,6 +49,7 @@ obj-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += globalscale-mirabox/
|
|||
obj-$(CONFIG_MACH_GUF_CUPID) += guf-cupid/
|
||||
obj-$(CONFIG_MACH_GUF_SANTARO) += guf-santaro/
|
||||
obj-$(CONFIG_MACH_GUF_VINCELL) += guf-vincell/
|
||||
obj-$(CONFIG_MACH_GW_VENTANA) += gateworks-ventana/
|
||||
obj-$(CONFIG_MACH_HIGHBANK) += highbank/
|
||||
obj-$(CONFIG_MACH_IMX21ADS) += freescale-mx21-ads/
|
||||
obj-$(CONFIG_MACH_IMX233_OLINUXINO) += imx233-olinuxino/
|
||||
|
|
@ -110,6 +111,7 @@ obj-$(CONFIG_MACH_TX25) += karo-tx25/
|
|||
obj-$(CONFIG_MACH_TX28) += karo-tx28/
|
||||
obj-$(CONFIG_MACH_TX51) += karo-tx51/
|
||||
obj-$(CONFIG_MACH_TX53) += karo-tx53/
|
||||
obj-$(CONFIG_MACH_TX6X) += karo-tx6x/
|
||||
obj-$(CONFIG_MACH_UDOO) += udoo/
|
||||
obj-$(CONFIG_MACH_USB_A9260) += usb-a926x/
|
||||
obj-$(CONFIG_MACH_USB_A9263) += usb-a926x/
|
||||
|
|
|
|||
|
|
@ -0,0 +1,2 @@
|
|||
obj-y += board.o gsc.o
|
||||
lwl-y += lowlevel.o
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Lucas Stach, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <environment.h>
|
||||
#include <i2c/i2c.h>
|
||||
#include <init.h>
|
||||
#include <linux/marvell_phy.h>
|
||||
#include <linux/phy.h>
|
||||
#include <mach/bbu.h>
|
||||
#include <mach/imx6.h>
|
||||
#include <net.h>
|
||||
|
||||
#include "gsc.h"
|
||||
|
||||
static int gw54xx_devices_init(void)
|
||||
{
|
||||
struct i2c_client client;
|
||||
struct device_node *dnode;
|
||||
u8 reg;
|
||||
u8 mac[6];
|
||||
|
||||
if (!of_machine_is_compatible("gw,imx6q-gw54xx"))
|
||||
return 0;
|
||||
|
||||
client.adapter = i2c_get_adapter(0);
|
||||
if (!client.adapter) {
|
||||
pr_err("could not get system controller i2c bus\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* disable the GSC boot watchdog */
|
||||
client.addr = GSC_SC_ADDR;
|
||||
gsc_i2c_read(&client, GSC_SC_CTRL1, ®, 1);
|
||||
reg |= GSC_SC_CTRL1_WDDIS;
|
||||
gsc_i2c_write(&client, GSC_SC_CTRL1, ®, 1);
|
||||
|
||||
/* read MAC adresses from EEPROM and attach to eth devices */
|
||||
dnode = of_find_node_by_alias(of_get_root_node(), "ethernet0");
|
||||
if (dnode) {
|
||||
client.addr = GSC_EEPROM_ADDR;
|
||||
gsc_i2c_read(&client, 0x00, mac, 6);
|
||||
of_eth_register_ethaddr(dnode, mac);
|
||||
}
|
||||
dnode = of_find_node_by_alias(of_get_root_node(), "ethernet1");
|
||||
if (dnode) {
|
||||
client.addr = GSC_EEPROM_ADDR;
|
||||
gsc_i2c_read(&client, 0x06, mac, 6);
|
||||
of_eth_register_ethaddr(dnode, mac);
|
||||
}
|
||||
|
||||
imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT);
|
||||
|
||||
barebox_set_hostname("gw54xx");
|
||||
|
||||
return 0;
|
||||
}
|
||||
device_initcall(gw54xx_devices_init);
|
||||
|
||||
static int marvell_88e1510_phy_fixup(struct phy_device *dev)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* LED settings */
|
||||
phy_write(dev, 22, 3);
|
||||
val = phy_read(dev, 16);
|
||||
val &= 0xff00;
|
||||
val |= 0x0017;
|
||||
phy_write(dev, 16, val);
|
||||
phy_write(dev, 22, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gw54xx_coredevices_init(void)
|
||||
{
|
||||
if (!of_machine_is_compatible("gw,imx6q-gw54xx"))
|
||||
return 0;
|
||||
|
||||
phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK,
|
||||
marvell_88e1510_phy_fixup);
|
||||
|
||||
return 0;
|
||||
}
|
||||
coredevice_initcall(gw54xx_coredevices_init);
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
wm 32 MX6_CCM_CCGR0 0x00C03F3F
|
||||
wm 32 MX6_CCM_CCGR1 0x0030FC03
|
||||
wm 32 MX6_CCM_CCGR2 0x0FFFC000
|
||||
wm 32 MX6_CCM_CCGR3 0x3FF00000
|
||||
wm 32 MX6_CCM_CCGR4 0xFFFFF300
|
||||
wm 32 MX6_CCM_CCGR5 0x0F0000C3
|
||||
wm 32 MX6_CCM_CCGR6 0x000003FF
|
||||
wm 32 MX6_CCM_CCOSR 0x000000FB
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
soc imx6
|
||||
loadaddr 0x20000000
|
||||
dcdofs 0x400
|
||||
|
||||
#include <mach/imx6-ddr-regs.h>
|
||||
#include <mach/imx6q-ddr-regs.h>
|
||||
#include <mach/imx6-ccm-regs.h>
|
||||
|
||||
#include "ram-base.imxcfg"
|
||||
#include "quad_128x64.imxcfg"
|
||||
#include "clocks.imxcfg"
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Gateworks Corporation
|
||||
* Copyright (C) 2014 Lucas Stach, Pengutronix
|
||||
* Author: Tim Harvey <tharvey@gateworks.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The Gateworks System Controller will fail to ACK a master transaction if
|
||||
* it is busy, which can occur during its 1HZ timer tick while reading ADC's.
|
||||
* When this does occur, it will never be busy long enough to fail more than
|
||||
* 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with
|
||||
* 3 retries.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c/i2c.h>
|
||||
|
||||
#include "gsc.h"
|
||||
|
||||
int gsc_i2c_read(struct i2c_client *client, u32 addr, u8 *buf, u16 count)
|
||||
{
|
||||
int retry = 3;
|
||||
int n = 0;
|
||||
int ret;
|
||||
|
||||
while (n++ < retry) {
|
||||
ret = i2c_read_reg(client, addr, buf, count);
|
||||
if (!ret)
|
||||
break;
|
||||
pr_debug("GSC read failed\n");
|
||||
if (ret != -ENODEV)
|
||||
break;
|
||||
mdelay(10);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int gsc_i2c_write(struct i2c_client *client, u32 addr, const u8 *buf, u16 count)
|
||||
{
|
||||
int retry = 3;
|
||||
int n = 0;
|
||||
int ret;
|
||||
|
||||
while (n++ < retry) {
|
||||
ret = i2c_write_reg(client, addr, buf, count);
|
||||
if (!ret)
|
||||
break;
|
||||
pr_debug("GSC write failed\n");
|
||||
if (ret != -ENODEV)
|
||||
break;
|
||||
mdelay(10);
|
||||
}
|
||||
mdelay(100);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Gateworks Corporation
|
||||
* Copyright (C) 2014 Lucas Stach, Pengutronix
|
||||
* Author: Tim Harvey <tharvey@gateworks.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* i2c slave addresses */
|
||||
#define GSC_SC_ADDR 0x20
|
||||
#define GSC_RTC_ADDR 0x68
|
||||
#define GSC_HWMON_ADDR 0x29
|
||||
#define GSC_EEPROM_ADDR 0x51
|
||||
|
||||
/* System Controller registers */
|
||||
#define GSC_SC_CTRL0 0x00
|
||||
#define GSC_SC_CTRL1 0x01
|
||||
#define GSC_SC_CTRL1_WDDIS (1 << 7)
|
||||
#define GSC_SC_STATUS 0x0a
|
||||
#define GSC_SC_FWVER 0x0e
|
||||
|
||||
/* System Controller Interrupt bits */
|
||||
#define GSC_SC_IRQ_PB 0 /* Pushbutton switch */
|
||||
#define GSC_SC_IRQ_SECURE 1 /* Secure Key erase complete */
|
||||
#define GSC_SC_IRQ_EEPROM_WP 2 /* EEPROM write violation */
|
||||
#define GSC_SC_IRQ_GPIO 4 /* GPIO change */
|
||||
#define GSC_SC_IRQ_TAMPER 5 /* Tamper detect */
|
||||
#define GSC_SC_IRQ_WATCHDOG 6 /* Watchdog trip */
|
||||
#define GSC_SC_IRQ_PBLONG 7 /* Pushbutton long hold */
|
||||
|
||||
/* Hardware Monitor registers */
|
||||
#define GSC_HWMON_TEMP 0x00
|
||||
#define GSC_HWMON_VIN 0x02
|
||||
#define GSC_HWMON_VDD_3P3 0x05
|
||||
#define GSC_HWMON_VBATT 0x08
|
||||
#define GSC_HWMON_VDD_5P0 0x0b
|
||||
#define GSC_HWMON_VDD_CORE 0x0e
|
||||
#define GSC_HWMON_VDD_HIGH 0x14
|
||||
#define GSC_HWMON_VDD_DDR 0x17
|
||||
#define GSC_HWMON_VDD_SOC 0x11
|
||||
#define GSC_HWMON_VDD_1P8 0x1d
|
||||
#define GSC_HWMON_VDD_2P5 0x23
|
||||
#define GSC_HWMON_VDD_1P0 0x20
|
||||
|
||||
/*
|
||||
* I2C transactions to the GSC are done via these functions which
|
||||
* perform retries in the case of a busy GSC NAK'ing the transaction
|
||||
*/
|
||||
int gsc_i2c_read(struct i2c_client *client, u32 addr, u8 *buf, u16 count);
|
||||
int gsc_i2c_write(struct i2c_client *client, u32 addr, const u8 *buf, u16 count);
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
#include <common.h>
|
||||
#include <sizes.h>
|
||||
#include <mach/generic.h>
|
||||
#include <asm/barebox-arm-head.h>
|
||||
#include <asm/barebox-arm.h>
|
||||
|
||||
extern char __dtb_imx6q_gw54xx_start[];
|
||||
|
||||
ENTRY_FUNCTION(start_imx6q_gw54xx_1gx64, r0, r1, r2)
|
||||
{
|
||||
void *fdt;
|
||||
|
||||
imx6_cpu_lowlevel_init();
|
||||
|
||||
fdt = __dtb_imx6q_gw54xx_start - get_runtime_offset();
|
||||
|
||||
barebox_arm_entry(0x10000000, SZ_1G, fdt);
|
||||
}
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x00190017
|
||||
wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x00140026
|
||||
wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x0021001C
|
||||
wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x0011001D
|
||||
|
||||
wm 32 MX6_MMDC_P0_MPDGCTRL0 0x43380347
|
||||
wm 32 MX6_MMDC_P0_MPDGCTRL1 0x433C034D
|
||||
wm 32 MX6_MMDC_P1_MPDGCTRL0 0x032C0324
|
||||
wm 32 MX6_MMDC_P1_MPDGCTRL1 0x03310232
|
||||
|
||||
wm 32 MX6_MMDC_P0_MPRDDLCTL 0x3C313539
|
||||
wm 32 MX6_MMDC_P1_MPRDDLCTL 0x37343141
|
||||
wm 32 MX6_MMDC_P0_MPWRDLCTL 0x36393C39
|
||||
wm 32 MX6_MMDC_P1_MPWRDLCTL 0x42344438
|
||||
|
||||
wm 32 MX6_MMDC_P0_MPODTCTRL 0x00022227
|
||||
wm 32 MX6_MMDC_P1_MPODTCTRL 0x00022227
|
||||
|
||||
wm 32 MX6_MMDC_P0_MPMUR0 0x00000800
|
||||
wm 32 MX6_MMDC_P1_MPMUR0 0x00000800
|
||||
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x00008000
|
||||
wm 32 MX6_MMDC_P0_MDCFG0 0x54597955
|
||||
wm 32 MX6_MMDC_P0_MDCFG1 0xFF328F64
|
||||
wm 32 MX6_MMDC_P0_MDCFG2 0x01FF00DB
|
||||
wm 32 MX6_MMDC_P0_MDOTC 0x09444040
|
||||
wm 32 MX6_MMDC_P0_MDASP 0x0000007F
|
||||
wm 32 MX6_MMDC_P0_MDMISC 0x00011740
|
||||
wm 32 MX6_MMDC_P0_MDOR 0x00591023
|
||||
wm 32 MX6_MMDC_P0_MDCTL 0x831A0000
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x02088032
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x00008033
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x00408031
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x09408030
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x04008040
|
||||
wm 32 MX6_MMDC_P0_MDPDC 0x00025576
|
||||
wm 32 MX6_MMDC_P0_MAPSR 0x00011006
|
||||
wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1390003
|
||||
wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xA1390003
|
||||
wm 32 MX6_MMDC_P0_MDREF 0x00007800
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x00000000
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
wm 32 MX6_IOM_DRAM_SDQS0 0x00000030
|
||||
wm 32 MX6_IOM_DRAM_SDQS1 0x00000030
|
||||
wm 32 MX6_IOM_DRAM_SDQS2 0x00000030
|
||||
wm 32 MX6_IOM_DRAM_SDQS3 0x00000030
|
||||
wm 32 MX6_IOM_DRAM_SDQS4 0x00000030
|
||||
wm 32 MX6_IOM_DRAM_SDQS5 0x00000030
|
||||
wm 32 MX6_IOM_DRAM_SDQS6 0x00000030
|
||||
wm 32 MX6_IOM_DRAM_SDQS7 0x00000030
|
||||
|
||||
wm 32 MX6_IOM_DRAM_DQM0 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_DQM1 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_DQM2 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_DQM3 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_DQM4 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_DQM5 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_DQM6 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_DQM7 0x00020030
|
||||
|
||||
wm 32 MX6_IOM_GRP_B0DS 0x00000030
|
||||
wm 32 MX6_IOM_GRP_B1DS 0x00000030
|
||||
wm 32 MX6_IOM_GRP_B2DS 0x00000030
|
||||
wm 32 MX6_IOM_GRP_B3DS 0x00000030
|
||||
wm 32 MX6_IOM_GRP_B4DS 0x00000030
|
||||
wm 32 MX6_IOM_GRP_B5DS 0x00000030
|
||||
wm 32 MX6_IOM_GRP_B6DS 0x00000030
|
||||
wm 32 MX6_IOM_GRP_B7DS 0x00000030
|
||||
|
||||
wm 32 MX6_IOM_DRAM_CAS 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_RAS 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_SDCLK_0 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_SDCLK_1 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_RESET 0x00020030
|
||||
|
||||
wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000
|
||||
wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000
|
||||
|
||||
wm 32 MX6_IOM_DRAM_SDBA2 0x00000000
|
||||
|
||||
wm 32 MX6_IOM_DRAM_SDODT0 0x00003030
|
||||
wm 32 MX6_IOM_DRAM_SDODT1 0x00003030
|
||||
|
||||
wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000
|
||||
wm 32 MX6_IOM_DDRMODE_CTL 0x00020000
|
||||
wm 32 MX6_IOM_GRP_DDRPKE 0x00000000
|
||||
wm 32 MX6_IOM_GRP_ADDDS 0x00000030
|
||||
wm 32 MX6_IOM_GRP_CTLDS 0x00000030
|
||||
wm 32 MX6_IOM_GRP_DDRMODE 0x00020000
|
||||
|
||||
wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333
|
||||
wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333
|
||||
wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333
|
||||
wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333
|
||||
wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333
|
||||
wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333
|
||||
wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333
|
||||
wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
/* MDMISC mirroring interleaved (row/bank/col) */
|
||||
wm 32 MX6_MMDC_P0_MDMISC 0x00000742
|
||||
check 32 while_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002
|
||||
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x00008000
|
||||
check 32 while_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000
|
||||
|
||||
wm 32 MX6_MMDC_P0_MDCTL 0x831a0000
|
||||
check 32 while_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000
|
||||
|
||||
wm 32 MX6_MMDC_P0_MDCFG0 0x3f435333
|
||||
wm 32 MX6_MMDC_P0_MDCFG1 0x926e8a63
|
||||
wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db
|
||||
wm 32 MX6_MMDC_P0_MDRWD 0x000026d2
|
||||
wm 32 MX6_MMDC_P0_MDOR 0x00431023
|
||||
wm 32 MX6_MMDC_P0_MDOTC 0x1b333030
|
||||
wm 32 MX6_MMDC_P0_MDPDC 0x0002006d
|
||||
wm 32 MX6_MMDC_P1_MDPDC 0x0002006d
|
||||
wm 32 MX6_MMDC_P0_MDASP 0x00000027
|
||||
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x05208030
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x00048031
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x00408032
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x00008033
|
||||
wm 32 MX6_MMDC_P0_MDREF 0x0000c000
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x00008020
|
||||
|
||||
wm 32 MX6_MMDC_P0_MPODTCTRL 0x00022222
|
||||
wm 32 MX6_MMDC_P1_MPODTCTRL 0x00022222
|
||||
|
||||
wm 32 MX6_MMDC_P0_MPPDCMPR2 0x00000003
|
||||
wm 32 MX6_MMDC_P0_MAPSR 0x00001007
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x04008010
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x04008040
|
||||
|
||||
wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1390001
|
||||
check 32 while_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000
|
||||
wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1380000
|
||||
|
||||
wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001e001e
|
||||
wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x001e001e
|
||||
wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x001e001e
|
||||
wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x001e001e
|
||||
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x00048033
|
||||
wm 32 MX6_IOM_DRAM_SDQS0 0x00007030
|
||||
wm 32 MX6_IOM_DRAM_SDQS1 0x00007030
|
||||
wm 32 MX6_IOM_DRAM_SDQS2 0x00007030
|
||||
wm 32 MX6_IOM_DRAM_SDQS3 0x00007030
|
||||
wm 32 MX6_IOM_DRAM_SDQS4 0x00007030
|
||||
wm 32 MX6_IOM_DRAM_SDQS5 0x00007030
|
||||
wm 32 MX6_IOM_DRAM_SDQS6 0x00007030
|
||||
wm 32 MX6_IOM_DRAM_SDQS7 0x00007030
|
||||
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x00008020
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x04008050
|
||||
|
||||
wm 32 MX6_MMDC_P0_MPRDDLCTL 0x40404040
|
||||
wm 32 MX6_MMDC_P0_MPWRDLCTL 0x40404040
|
||||
wm 32 MX6_MMDC_P1_MPRDDLCTL 0x40404040
|
||||
wm 32 MX6_MMDC_P1_MPWRDLCTL 0x40404040
|
||||
wm 32 MX6_MMDC_P0_MPMUR0 0x00000800
|
||||
|
||||
wm 32 MX6_MMDC_P0_MPDGCTRL0 0x80000000
|
||||
check 32 while_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000
|
||||
wm 32 MX6_MMDC_P0_MPDGCTRL0 0x80000000
|
||||
check 32 while_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000
|
||||
wm 32 MX6_MMDC_P0_MPDGCTRL0 0x50800000
|
||||
check 32 while_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x10001000
|
||||
|
||||
wm 32 MX6_IOM_DRAM_SDQS0 0x00000030
|
||||
wm 32 MX6_IOM_DRAM_SDQS1 0x00000030
|
||||
wm 32 MX6_IOM_DRAM_SDQS2 0x00000030
|
||||
wm 32 MX6_IOM_DRAM_SDQS3 0x00000030
|
||||
wm 32 MX6_IOM_DRAM_SDQS4 0x00000030
|
||||
wm 32 MX6_IOM_DRAM_SDQS5 0x00000030
|
||||
wm 32 MX6_IOM_DRAM_SDQS6 0x00000030
|
||||
wm 32 MX6_IOM_DRAM_SDQS7 0x00000030
|
||||
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x04008050
|
||||
wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030
|
||||
wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030
|
||||
|
||||
check 32 while_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
|
||||
check 32 while_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f
|
||||
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x04008050
|
||||
wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030
|
||||
check 32 while_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
|
||||
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x04008050
|
||||
wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030
|
||||
check 32 while_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x00008033
|
||||
wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b
|
||||
wm 32 MX6_MMDC_P0_MDREF 0x00001800
|
||||
wm 32 MX6_MMDC_P0_MAPSR 0x00001006
|
||||
wm 32 MX6_MMDC_P0_MDPDC 0x0002556d
|
||||
wm 32 MX6_MMDC_P1_MDPDC 0x0002556d
|
||||
wm 32 MX6_MMDC_P0_MDSCR 0x00000000
|
||||
check 32 while_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
obj-y += board.o
|
||||
lwl-y += lowlevel.o
|
||||
|
|
@ -0,0 +1,202 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Steffen Trumtrar, Pengutronix
|
||||
*
|
||||
*
|
||||
* with the PMIC init code taken from u-boot
|
||||
* Copyright (C) 2012,2013 Lothar Waßmann <LW@KARO-electronics.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <gpio.h>
|
||||
#include <init.h>
|
||||
#include <i2c/i2c.h>
|
||||
#include <linux/clk.h>
|
||||
#include <environment.h>
|
||||
#include <mach/bbu.h>
|
||||
#include <mach/imx6.h>
|
||||
#include <mfd/imx6q-iomuxc-gpr.h>
|
||||
|
||||
#define ETH_PHY_RST IMX_GPIO_NR(7, 6)
|
||||
#define ETH_PHY_PWR IMX_GPIO_NR(3, 20)
|
||||
#define ETH_PHY_INT IMX_GPIO_NR(7, 1)
|
||||
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
|
||||
#define DIV_ROUND(n,d) (((n) + ((d)/2)) / (d))
|
||||
|
||||
#define LTC3676_BUCK1 0x01
|
||||
#define LTC3676_BUCK2 0x02
|
||||
#define LTC3676_BUCK3 0x03
|
||||
#define LTC3676_BUCK4 0x04
|
||||
#define LTC3676_DVB1A 0x0A
|
||||
#define LTC3676_DVB1B 0x0B
|
||||
#define LTC3676_DVB2A 0x0C
|
||||
#define LTC3676_DVB2B 0x0D
|
||||
#define LTC3676_DVB3A 0x0E
|
||||
#define LTC3676_DVB3B 0x0F
|
||||
#define LTC3676_DVB4A 0x10
|
||||
#define LTC3676_DVB4B 0x11
|
||||
#define LTC3676_MSKPG 0x13
|
||||
#define LTC3676_CLIRQ 0x1f
|
||||
|
||||
#define LTC3676_BUCK_DVDT_FAST (1 << 0)
|
||||
#define LTC3676_BUCK_KEEP_ALIVE (1 << 1)
|
||||
#define LTC3676_BUCK_CLK_RATE_LOW (1 << 2)
|
||||
#define LTC3676_BUCK_PHASE_SEL (1 << 3)
|
||||
#define LTC3676_BUCK_ENABLE_300 (1 << 4)
|
||||
#define LTC3676_BUCK_PULSE_SKIP (0 << 5)
|
||||
#define LTC3676_BUCK_BURST_MODE (1 << 5)
|
||||
#define LTC3676_BUCK_CONTINUOUS (2 << 5)
|
||||
#define LTC3676_BUCK_ENABLE (1 << 7)
|
||||
|
||||
#define LTC3676_PGOOD_MASK (1 << 5)
|
||||
|
||||
#define LTC3676_MSKPG_BUCK1 (1 << 0)
|
||||
#define LTC3676_MSKPG_BUCK2 (1 << 1)
|
||||
#define LTC3676_MSKPG_BUCK3 (1 << 2)
|
||||
#define LTC3676_MSKPG_BUCK4 (1 << 3)
|
||||
#define LTC3676_MSKPG_LDO2 (1 << 5)
|
||||
#define LTC3676_MSKPG_LDO3 (1 << 6)
|
||||
#define LTC3676_MSKPG_LDO4 (1 << 7)
|
||||
|
||||
#define VDD_IO_VAL mV_to_regval(vout_to_vref(3300 * 10, 5))
|
||||
#define VDD_IO_VAL_LP mV_to_regval(vout_to_vref(3100 * 10, 5))
|
||||
#define VDD_IO_VAL_2 mV_to_regval(vout_to_vref(3300 * 10, 5_2))
|
||||
#define VDD_IO_VAL_2_LP mV_to_regval(vout_to_vref(3100 * 10, 5_2))
|
||||
#define VDD_SOC_VAL mV_to_regval(vout_to_vref(1425 * 10, 6))
|
||||
#define VDD_SOC_VAL_LP mV_to_regval(vout_to_vref(900 * 10, 6))
|
||||
#define VDD_DDR_VAL mV_to_regval(vout_to_vref(1500 * 10, 7))
|
||||
#define VDD_DDR_VAL_LP mV_to_regval(vout_to_vref(1500 * 10, 7))
|
||||
#define VDD_CORE_VAL mV_to_regval(vout_to_vref(1425 * 10, 8))
|
||||
#define VDD_CORE_VAL_LP mV_to_regval(vout_to_vref(900 * 10, 8))
|
||||
|
||||
/* LDO1 */
|
||||
#define R1_1 470
|
||||
#define R2_1 150
|
||||
/* LDO4 */
|
||||
#define R1_4 470
|
||||
#define R2_4 150
|
||||
/* Buck1 */
|
||||
#define R1_5 390
|
||||
#define R2_5 110
|
||||
#define R1_5_2 470
|
||||
#define R2_5_2 150
|
||||
/* Buck2 (SOC) */
|
||||
#define R1_6 150
|
||||
#define R2_6 180
|
||||
/* Buck3 (DDR) */
|
||||
#define R1_7 150
|
||||
#define R2_7 140
|
||||
/* Buck4 (CORE) */
|
||||
#define R1_8 150
|
||||
#define R2_8 180
|
||||
|
||||
/* calculate voltages in 10mV */
|
||||
#define R1(idx) R1_##idx
|
||||
#define R2(idx) R2_##idx
|
||||
|
||||
#define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx)))
|
||||
#define vref_to_vout(vref, idx) DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx))
|
||||
|
||||
#define mV_to_regval(mV) DIV_ROUND(((((mV) < 4125) ? 4125 : (mV)) - 4125), 125)
|
||||
#define regval_to_mV(v) (((v) * 125 + 4125))
|
||||
|
||||
static struct ltc3673_regs {
|
||||
u8 addr;
|
||||
u8 val;
|
||||
u8 mask;
|
||||
} ltc3676_regs[] = {
|
||||
{ LTC3676_MSKPG, ~LTC3676_MSKPG_BUCK1, },
|
||||
{ LTC3676_DVB2B, VDD_SOC_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, },
|
||||
{ LTC3676_DVB3B, VDD_DDR_VAL_LP, ~0x3f, },
|
||||
{ LTC3676_DVB4B, VDD_CORE_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, },
|
||||
{ LTC3676_DVB2A, VDD_SOC_VAL, ~0x3f, },
|
||||
{ LTC3676_DVB3A, VDD_DDR_VAL, ~0x3f, },
|
||||
{ LTC3676_DVB4A, VDD_CORE_VAL, ~0x3f, },
|
||||
{ LTC3676_BUCK1, LTC3676_BUCK_BURST_MODE | LTC3676_BUCK_CLK_RATE_LOW, },
|
||||
{ LTC3676_BUCK2, LTC3676_BUCK_BURST_MODE, },
|
||||
{ LTC3676_BUCK3, LTC3676_BUCK_BURST_MODE, },
|
||||
{ LTC3676_BUCK4, LTC3676_BUCK_BURST_MODE, },
|
||||
{ LTC3676_CLIRQ, 0, }, /* clear interrupt status */
|
||||
};
|
||||
|
||||
static struct ltc3673_regs ltc3676_regs_2[] = {
|
||||
{ LTC3676_DVB1B, VDD_IO_VAL_2_LP | LTC3676_PGOOD_MASK, ~0x3f, },
|
||||
{ LTC3676_DVB1A, VDD_IO_VAL_2, ~0x3f, },
|
||||
};
|
||||
|
||||
|
||||
static int setup_pmic_voltages(void)
|
||||
{
|
||||
struct i2c_adapter *adapter = NULL;
|
||||
struct i2c_client client;
|
||||
int addr = 0x3c;
|
||||
int bus = 0;
|
||||
int i;
|
||||
struct ltc3673_regs *r;
|
||||
|
||||
adapter = i2c_get_adapter(bus);
|
||||
if (!adapter) {
|
||||
pr_err("i2c bus %d not found\n", bus);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
client.adapter = adapter;
|
||||
client.addr = addr;
|
||||
|
||||
r = ltc3676_regs;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(ltc3676_regs); i++, r++) {
|
||||
if (i2c_write_reg(&client, r->addr, &r->val, 1) != 1) {
|
||||
pr_err("i2c write error\n");
|
||||
return -EIO;
|
||||
}
|
||||
}
|
||||
|
||||
r = ltc3676_regs_2;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(ltc3676_regs_2); i++, r++) {
|
||||
if (i2c_write_reg(&client, r->addr, &r->val, 1) != 1) {
|
||||
pr_err("i2c write error\n");
|
||||
return -EIO;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void eth_init(void)
|
||||
{
|
||||
void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR;
|
||||
uint32_t val;
|
||||
|
||||
val = readl(iomux + IOMUXC_GPR1);
|
||||
val |= IMX6Q_GPR1_ENET_CLK_SEL_ANATOP;
|
||||
writel(val, iomux + IOMUXC_GPR1);
|
||||
}
|
||||
|
||||
static int tx6x_devices_init(void)
|
||||
{
|
||||
if (!of_machine_is_compatible("karo,imx6dl-tx6dl") &&
|
||||
!of_machine_is_compatible("karo,imx6q-tx6q"))
|
||||
return 0;
|
||||
|
||||
barebox_set_hostname("tx6u");
|
||||
|
||||
eth_init();
|
||||
|
||||
setup_pmic_voltages();
|
||||
|
||||
imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
device_initcall(tx6x_devices_init);
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
soc imx6
|
||||
loadaddr 0x20000000
|
||||
dcdofs 0x400
|
||||
|
||||
#include <mach/imx6-ddr-regs.h>
|
||||
#include <mach/imx6dl-ddr-regs.h>
|
||||
#include <mach/imx6-ccm-regs.h>
|
||||
|
||||
#include "ram-base.imxcfg"
|
||||
#include "1600mhz_4x128mx16.imxcfg"
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Steffen Trumtrar, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <debug_ll.h>
|
||||
#include <common.h>
|
||||
#include <asm/barebox-arm-head.h>
|
||||
#include <asm/barebox-arm.h>
|
||||
#include <image-metadata.h>
|
||||
#include <mach/generic.h>
|
||||
#include <sizes.h>
|
||||
|
||||
static inline void setup_uart(void)
|
||||
{
|
||||
void __iomem *ccmbase = (void *)MX6_CCM_BASE_ADDR;
|
||||
void __iomem *uartbase = (void *)MX6_UART1_BASE_ADDR;
|
||||
void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;
|
||||
|
||||
writel(0x1, iomuxbase + 0x0314);
|
||||
writel(0x1, iomuxbase + 0x0318);
|
||||
writel(0x1, iomuxbase + 0x0330);
|
||||
writel(0x1, iomuxbase + 0x032c);
|
||||
|
||||
writel(0xffffffff, ccmbase + 0x68);
|
||||
writel(0xffffffff, ccmbase + 0x6c);
|
||||
writel(0xffffffff, ccmbase + 0x70);
|
||||
writel(0xffffffff, ccmbase + 0x74);
|
||||
writel(0xffffffff, ccmbase + 0x78);
|
||||
writel(0xffffffff, ccmbase + 0x7c);
|
||||
writel(0xffffffff, ccmbase + 0x80);
|
||||
|
||||
writel(0x00000000, uartbase + 0x80);
|
||||
writel(0x00004027, uartbase + 0x84);
|
||||
writel(0x00000784, uartbase + 0x88);
|
||||
writel(0x00000a81, uartbase + 0x90);
|
||||
writel(0x0000002b, uartbase + 0x9c);
|
||||
writel(0x0001b0b0, uartbase + 0xb0);
|
||||
writel(0x0000047f, uartbase + 0xa4);
|
||||
writel(0x0000c34f, uartbase + 0xa8);
|
||||
writel(0x00000001, uartbase + 0x80);
|
||||
|
||||
putc_ll('>');
|
||||
}
|
||||
|
||||
extern char __dtb_imx6dl_tx6u_801x_start[];
|
||||
|
||||
BAREBOX_IMD_TAG_STRING(tx6x_mx6_memsize_1G, IMD_TYPE_PARAMETER, "memsize=1024", 0);
|
||||
|
||||
ENTRY_FUNCTION(start_imx6dl_tx6x_1g, r0, r1, r2)
|
||||
{
|
||||
void *fdt;
|
||||
|
||||
imx6_cpu_lowlevel_init();
|
||||
|
||||
arm_setup_stack(0x00920000 - 8);
|
||||
|
||||
IMD_USED(tx6x_mx6_memsize_1G);
|
||||
|
||||
if (IS_ENABLED(CONFIG_DEBUG_LL))
|
||||
setup_uart();
|
||||
|
||||
fdt = __dtb_imx6dl_tx6u_801x_start - get_runtime_offset();
|
||||
|
||||
barebox_arm_entry(0x10000000, SZ_1G, fdt);
|
||||
}
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
wm 32 MX6_IOM_DRAM_DQM0 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_DQM1 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_DQM2 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_DQM3 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_DQM4 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_DQM5 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_DQM6 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_DQM7 0x00020030
|
||||
|
||||
wm 32 MX6_IOM_DRAM_ADDR00 0x00000000
|
||||
wm 32 MX6_IOM_DRAM_ADDR01 0x00000000
|
||||
wm 32 MX6_IOM_DRAM_ADDR02 0x00000000
|
||||
wm 32 MX6_IOM_DRAM_ADDR03 0x00000000
|
||||
wm 32 MX6_IOM_DRAM_ADDR04 0x00000000
|
||||
wm 32 MX6_IOM_DRAM_ADDR05 0x00000000
|
||||
wm 32 MX6_IOM_DRAM_ADDR06 0x00000000
|
||||
wm 32 MX6_IOM_DRAM_ADDR07 0x00000000
|
||||
wm 32 MX6_IOM_DRAM_ADDR08 0x00000000
|
||||
wm 32 MX6_IOM_DRAM_ADDR09 0x00000000
|
||||
wm 32 MX6_IOM_DRAM_ADDR10 0x00000000
|
||||
wm 32 MX6_IOM_DRAM_ADDR11 0x00000000
|
||||
wm 32 MX6_IOM_DRAM_ADDR12 0x00000000
|
||||
wm 32 MX6_IOM_DRAM_ADDR13 0x00000000
|
||||
wm 32 MX6_IOM_DRAM_ADDR14 0x00000000
|
||||
wm 32 MX6_IOM_DRAM_ADDR15 0x00000000
|
||||
|
||||
wm 32 MX6_IOM_DRAM_CAS 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_RAS 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_SDCLK_0 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_SDCLK_1 0x00020030
|
||||
|
||||
wm 32 MX6_IOM_DRAM_RESET 0x00020030
|
||||
wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000
|
||||
wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000
|
||||
wm 32 MX6_IOM_DRAM_SDBA0 0x00000000
|
||||
wm 32 MX6_IOM_DRAM_SDBA1 0x00000000
|
||||
wm 32 MX6_IOM_DRAM_SDBA2 0x00000000
|
||||
wm 32 MX6_IOM_DRAM_SDODT0 0x00003030
|
||||
wm 32 MX6_IOM_DRAM_SDODT1 0x00003030
|
||||
wm 32 MX6_IOM_GRP_B0DS 0x00000030
|
||||
wm 32 MX6_IOM_GRP_B1DS 0x00000030
|
||||
wm 32 MX6_IOM_GRP_B2DS 0x00000030
|
||||
wm 32 MX6_IOM_GRP_B3DS 0x00000030
|
||||
wm 32 MX6_IOM_GRP_B4DS 0x00000030
|
||||
wm 32 MX6_IOM_GRP_B5DS 0x00000030
|
||||
wm 32 MX6_IOM_GRP_B6DS 0x00000030
|
||||
wm 32 MX6_IOM_GRP_B7DS 0x00000030
|
||||
wm 32 MX6_IOM_GRP_ADDDS 0x00000030
|
||||
|
||||
/* (differential input) */
|
||||
wm 32 MX6_IOM_DDRMODE_CTL 0x00020000
|
||||
/* disable ddr pullups */
|
||||
wm 32 MX6_IOM_GRP_DDRPKE 0x00000000
|
||||
/* (differential input) */
|
||||
wm 32 MX6_IOM_GRP_DDRMODE 0x00020000
|
||||
wm 32 MX6_IOM_GRP_CTLDS 0x00000030
|
||||
|
||||
wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000
|
||||
wm 32 MX6_IOM_GRP_DDRPKE 0x00002000
|
||||
/* GRP_DDRHYS */
|
||||
wm 32 MX6_IOM_GRP_DDRHYS 0x00000000
|
||||
|
||||
/* Read data DQ Byte0-3 delay */
|
||||
wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333
|
||||
wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333
|
||||
wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333
|
||||
wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333
|
||||
wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333
|
||||
wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333
|
||||
wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333
|
||||
wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333
|
||||
|
|
@ -1,6 +1,7 @@
|
|||
CONFIG_ARCH_IMX=y
|
||||
CONFIG_IMX_MULTI_BOARDS=y
|
||||
CONFIG_MACH_EFIKA_MX_SMARTBOOK=y
|
||||
CONFIG_MACH_EMBEDSKY_E9=y
|
||||
CONFIG_MACH_FREESCALE_MX51_PDK=y
|
||||
CONFIG_MACH_FREESCALE_MX53_LOCO=y
|
||||
CONFIG_MACH_TQMA53=y
|
||||
|
|
@ -16,10 +17,10 @@ CONFIG_MACH_SABRELITE=y
|
|||
CONFIG_MACH_SABRESD=y
|
||||
CONFIG_MACH_NITROGEN6X=y
|
||||
CONFIG_MACH_SOLIDRUN_MICROSOM=y
|
||||
CONFIG_MACH_EMBEDSKY_E9=y
|
||||
CONFIG_MACH_EMBEST_RIOTBOARD=y
|
||||
CONFIG_MACH_UDOO=y
|
||||
CONFIG_MACH_VARISCITE_MX6=y
|
||||
CONFIG_MACH_GW_VENTANA=y
|
||||
CONFIG_IMX_IIM=y
|
||||
CONFIG_IMX_IIM_FUSE_BLOW=y
|
||||
CONFIG_IMX_OCOTP=y
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@ pbl-dtb-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o
|
|||
pbl-dtb-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += kirkwood-guruplug-server-plus-bb.dtb.o
|
||||
pbl-dtb-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += armada-370-mirabox-bb.dtb.o
|
||||
pbl-dtb-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o
|
||||
pbl-dtb-$(CONFIG_MACH_GW_VENTANA) += imx6q-gw54xx.dtb.o
|
||||
pbl-dtb-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += armada-xp-gp-bb.dtb.o
|
||||
pbl-dtb-$(CONFIG_MACH_NITROGEN6X) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o
|
||||
pbl-dtb-$(CONFIG_MACH_NVIDIA_BEAVER) += tegra30-beaver.dtb.o
|
||||
|
|
@ -42,6 +43,7 @@ pbl-dtb-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o
|
|||
pbl-dtb-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o
|
||||
pbl-dtb-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o
|
||||
pbl-dtb-$(CONFIG_MACH_TX25) += imx25-karo-tx25.dtb.o
|
||||
pbl-dtb-$(CONFIG_MACH_TX6X) += imx6dl-tx6u-801x.dtb.o
|
||||
pbl-dtb-$(CONFIG_MACH_UDOO) += imx6q-udoo.dtb.o
|
||||
pbl-dtb-$(CONFIG_MACH_USI_TOPKICK) += kirkwood-topkick-bb.dtb.o
|
||||
pbl-dtb-$(CONFIG_MACH_VARISCITE_MX6) += imx6q-var-custom.dtb.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,65 @@
|
|||
#include <arm/imx6dl-tx6u-801x.dts>
|
||||
#include "imx6qdl.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ka-Ro electronics TX6U-801x Module";
|
||||
compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = &uart1;
|
||||
|
||||
environment@0 {
|
||||
compatible = "barebox,environment";
|
||||
device-path = &gpmi, "partname:barebox-environment";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpmi {
|
||||
partition@0 {
|
||||
label = "barebox";
|
||||
reg = <0x0 0x100000>;
|
||||
};
|
||||
|
||||
partition@1 {
|
||||
label = "barebox-environment";
|
||||
reg = <0x100000 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx6qdl-tx6 {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */
|
||||
MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
|
||||
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
|
||||
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
|
||||
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
|
||||
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
|
||||
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
|
||||
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
phy-reset-duration = <22>;
|
||||
};
|
||||
|
||||
&ocotp {
|
||||
barebox,provide-mac-address = <&fec 0x620>;
|
||||
};
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright 2013 Gateworks Corporation
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-gw54xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Gateworks Ventana i.MX6 Quad GW54XX";
|
||||
compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright 2013 Gateworks Corporation
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <arm/imx6qdl-gw54xx.dtsi>
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
linux,stdout-path = &uart2;
|
||||
|
||||
environment@0 {
|
||||
compatible = "barebox,environment";
|
||||
device-path = &gpmi, "partname:barebox-environment";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpmi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "barebox";
|
||||
reg = <0x0 0x400000>;
|
||||
};
|
||||
|
||||
partition@1 {
|
||||
label = "barebox-environment";
|
||||
reg = <0x400000 0x20000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -261,6 +261,10 @@ config MACH_TQMA6X
|
|||
bool "TQ tqma6x on mba6x"
|
||||
select ARCH_IMX6
|
||||
|
||||
config MACH_TX6X
|
||||
bool "Karo TX6x"
|
||||
select ARCH_IMX6
|
||||
|
||||
config MACH_SABRELITE
|
||||
bool "Freescale i.MX6 Sabre Lite"
|
||||
select ARCH_IMX6
|
||||
|
|
@ -291,6 +295,9 @@ config MACH_VARISCITE_MX6
|
|||
bool "Variscite i.MX6 Quad SOM"
|
||||
select ARCH_IMX6
|
||||
|
||||
config MACH_GW_VENTANA
|
||||
bool "Gateworks Ventana SBC"
|
||||
select ARCH_IMX6
|
||||
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -153,6 +153,7 @@
|
|||
#define MX35_CCM_CGR1_FEC_SHIFT 0
|
||||
#define MX35_CCM_CGR1_I2C1_SHIFT 10
|
||||
#define MX35_CCM_CGR1_SDHC1_SHIFT 26
|
||||
#define MX35_CCM_CGR2_UART2_SHIFT 18
|
||||
#define MX35_CCM_CGR2_USB_SHIFT 22
|
||||
|
||||
#define MX35_CCM_RCSR_MEM_CTRL_SHIFT 25
|
||||
|
|
|
|||
|
|
@ -37,6 +37,9 @@
|
|||
#define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
|
||||
#define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
|
||||
#define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
|
||||
#define MX6_MMDC_P0_MPRDDLHWCTL 0x021b0860
|
||||
#define MX6_MMDC_P0_MPWRDLHWCTL 0x021b0864
|
||||
#define MX6_MMDC_P0_MPPDCMPR2 0x021b0890
|
||||
#define MX6_MMDC_P0_MPMUR0 0x021b08b8
|
||||
|
||||
#define MX6_MMDC_P1_MDCTL 0x021b4000
|
||||
|
|
@ -64,4 +67,7 @@
|
|||
#define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
|
||||
#define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
|
||||
#define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
|
||||
#define MX6_MMDC_P1_MPRDDLHWCTL 0x021b4860
|
||||
#define MX6_MMDC_P1_MPWRDLHWCTL 0x021b4864
|
||||
#define MX6_MMDC_P1_MPPDCMPR2 0x021b4890
|
||||
#define MX6_MMDC_P1_MPMUR0 0x021b48b8
|
||||
|
|
|
|||
|
|
@ -12,6 +12,23 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define MX6_IOM_DRAM_ADDR00 0x020e0424
|
||||
#define MX6_IOM_DRAM_ADDR01 0x020e0428
|
||||
#define MX6_IOM_DRAM_ADDR10 0x020e042c
|
||||
#define MX6_IOM_DRAM_ADDR11 0x020e0430
|
||||
#define MX6_IOM_DRAM_ADDR12 0x020e0434
|
||||
#define MX6_IOM_DRAM_ADDR13 0x020e0438
|
||||
#define MX6_IOM_DRAM_ADDR14 0x020e043c
|
||||
#define MX6_IOM_DRAM_ADDR15 0x020e0440
|
||||
#define MX6_IOM_DRAM_ADDR02 0x020e0444
|
||||
#define MX6_IOM_DRAM_ADDR03 0x020e0448
|
||||
#define MX6_IOM_DRAM_ADDR04 0x020e044c
|
||||
#define MX6_IOM_DRAM_ADDR05 0x020e0450
|
||||
#define MX6_IOM_DRAM_ADDR06 0x020e0454
|
||||
#define MX6_IOM_DRAM_ADDR07 0x020e0458
|
||||
#define MX6_IOM_DRAM_ADDR08 0x020e045c
|
||||
#define MX6_IOM_DRAM_ADDR09 0x020e0460
|
||||
|
||||
#define MX6_IOM_DRAM_DQM0 0x020e0470
|
||||
#define MX6_IOM_DRAM_DQM1 0x020e0474
|
||||
#define MX6_IOM_DRAM_DQM2 0x020e0478
|
||||
|
|
@ -24,6 +41,8 @@
|
|||
#define MX6_IOM_DRAM_CAS 0x020e0464
|
||||
#define MX6_IOM_DRAM_RAS 0x020e0490
|
||||
#define MX6_IOM_DRAM_RESET 0x020e0494
|
||||
#define MX6_IOM_DRAM_SDBA0 0x020e0498
|
||||
#define MX6_IOM_DRAM_SDBA1 0x020e049c
|
||||
#define MX6_IOM_DRAM_SDCLK_0 0x020e04ac
|
||||
#define MX6_IOM_DRAM_SDCLK_1 0x020e04b0
|
||||
#define MX6_IOM_DRAM_SDBA2 0x020e04a0
|
||||
|
|
@ -52,6 +71,7 @@
|
|||
#define MX6_IOM_GRP_ADDDS 0x020e074c
|
||||
#define MX6_IOM_DDRMODE_CTL 0x020e0750
|
||||
#define MX6_IOM_GRP_DDRPKE 0x020e0754
|
||||
#define MX6_IOM_GRP_DDRHYS 0x020e075c
|
||||
#define MX6_IOM_GRP_DDRMODE 0x020e0760
|
||||
#define MX6_IOM_GRP_CTLDS 0x020e076c
|
||||
#define MX6_IOM_GRP_DDR_TYPE 0x020e0774
|
||||
|
|
|
|||
|
|
@ -10,22 +10,7 @@
|
|||
#include <linux/ethtool.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/smscphy.h>
|
||||
|
||||
/* Known PHY IDs */
|
||||
#define MARVELL_PHY_ID_88E1101 0x01410c60
|
||||
#define MARVELL_PHY_ID_88E1112 0x01410c90
|
||||
#define MARVELL_PHY_ID_88E1111 0x01410cc0
|
||||
#define MARVELL_PHY_ID_88E1118 0x01410e10
|
||||
#define MARVELL_PHY_ID_88E1121R 0x01410cb0
|
||||
#define MARVELL_PHY_ID_88E1145 0x01410cd0
|
||||
#define MARVELL_PHY_ID_88E1149R 0x01410e50
|
||||
#define MARVELL_PHY_ID_88E1240 0x01410e30
|
||||
#define MARVELL_PHY_ID_88E1318S 0x01410e90
|
||||
#define MARVELL_PHY_ID_88E1116R 0x01410e40
|
||||
#define MARVELL_PHY_ID_88E1510 0x01410dd0
|
||||
|
||||
/* Mask used for ID comparisons */
|
||||
#define MARVELL_PHY_ID_MASK 0xfffffff0
|
||||
#include <linux/marvell_phy.h>
|
||||
|
||||
/* Marvell Register Page register */
|
||||
#define MII_MARVELL_PHY_PAGE 22
|
||||
|
|
|
|||
|
|
@ -160,6 +160,11 @@ CFG_start_imx6dl_nitrogen6x_1g.pblx.imximg = $(board)/boundarydevices-nitrogen6x
|
|||
FILE_barebox-boundarydevices-imx6dl-nitrogen6x-1g.img = start_imx6dl_nitrogen6x_1g.pblx.imximg
|
||||
image-$(CONFIG_MACH_NITROGEN6X) += barebox-boundarydevices-imx6dl-nitrogen6x-1g.img
|
||||
|
||||
pblx-$(CONFIG_MACH_TX6X) += start_imx6dl_tx6x_1g
|
||||
CFG_start_imx6dl_tx6x_1g.pblx.imximg = $(board)/karo-tx6x/flash-header-tx6dl-1g.imxcfg
|
||||
FILE_barebox-karo-imx6dl-tx6x-1g.img = start_imx6dl_tx6x_1g.pblx.imximg
|
||||
image-$(CONFIG_MACH_TX6X) += barebox-karo-imx6dl-tx6x-1g.img
|
||||
|
||||
pblx-$(CONFIG_MACH_UDOO) += start_imx6_udoo
|
||||
CFG_start_imx6_udoo.pblx.imximg = $(board)/udoo/flash-header-mx6-udoo.imxcfg
|
||||
FILE_barebox-udoo-imx6q.img = start_imx6_udoo.pblx.imximg
|
||||
|
|
@ -194,3 +199,8 @@ pblx-$(CONFIG_MACH_PCAAXL3) += start_phytec_pbaa03_2gib
|
|||
CFG_start_phytec_pbaa03_2gib.pblx.imximg = $(board)/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg
|
||||
FILE_barebox-phytec-pbaa03-2gib.img = start_phytec_pbaa03_2gib.pblx.imximg
|
||||
image-$(CONFIG_MACH_PCAAXL3) += barebox-phytec-pbaa03-2gib.img
|
||||
|
||||
pblx-$(CONFIG_MACH_GW_VENTANA) += start_imx6q_gw54xx_1gx64
|
||||
CFG_start_imx6q_gw54xx_1gx64.pblx.imximg = $(board)/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg
|
||||
FILE_barebox-gateworks-imx6q-ventana-1gx64.img = start_imx6q_gw54xx_1gx64.pblx.imximg
|
||||
image-$(CONFIG_MACH_GW_VENTANA) += barebox-gateworks-imx6q-ventana-1gx64.img
|
||||
|
|
|
|||
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Marvell PHY IDs
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _MARVELL_PHY_H
|
||||
#define _MARVELL_PHY_H
|
||||
|
||||
/* Known PHY IDs */
|
||||
#define MARVELL_PHY_ID_88E1101 0x01410c60
|
||||
#define MARVELL_PHY_ID_88E1112 0x01410c90
|
||||
#define MARVELL_PHY_ID_88E1111 0x01410cc0
|
||||
#define MARVELL_PHY_ID_88E1118 0x01410e10
|
||||
#define MARVELL_PHY_ID_88E1121R 0x01410cb0
|
||||
#define MARVELL_PHY_ID_88E1145 0x01410cd0
|
||||
#define MARVELL_PHY_ID_88E1149R 0x01410e50
|
||||
#define MARVELL_PHY_ID_88E1240 0x01410e30
|
||||
#define MARVELL_PHY_ID_88E1318S 0x01410e90
|
||||
#define MARVELL_PHY_ID_88E1116R 0x01410e40
|
||||
#define MARVELL_PHY_ID_88E1510 0x01410dd0
|
||||
|
||||
/* Mask used for ID comparisons */
|
||||
#define MARVELL_PHY_ID_MASK 0xfffffff0
|
||||
|
||||
#endif /* _MARVELL_PHY_H */
|
||||
|
|
@ -37,6 +37,7 @@ static uint32_t image_dcd_offset;
|
|||
static uint32_t dcdtable[MAX_DCD];
|
||||
static int curdcd;
|
||||
static int header_version;
|
||||
static int cpu_type;
|
||||
static int add_barebox_header;
|
||||
|
||||
/*
|
||||
|
|
@ -259,34 +260,29 @@ struct command {
|
|||
int (*parse)(int argc, char *argv[]);
|
||||
};
|
||||
|
||||
static uint32_t last_cmd;
|
||||
static uint32_t last_write_cmd;
|
||||
static int last_cmd_len;
|
||||
static uint32_t *last_dcd;
|
||||
|
||||
static void check_last_dcd(uint32_t cmd)
|
||||
{
|
||||
if (last_dcd) {
|
||||
if (last_cmd == cmd) {
|
||||
return;
|
||||
} else {
|
||||
uint32_t l = be32toh(*last_dcd);
|
||||
cmd &= 0xff0000ff;
|
||||
|
||||
l |= last_cmd_len << 8;
|
||||
|
||||
*last_dcd = htobe32(l);
|
||||
|
||||
last_dcd = NULL;
|
||||
}
|
||||
if (cmd == last_write_cmd) {
|
||||
last_cmd_len += sizeof(uint32_t) * 2;
|
||||
return;
|
||||
}
|
||||
|
||||
if (!cmd)
|
||||
return;
|
||||
/* write length ... */
|
||||
if (last_write_cmd)
|
||||
*last_dcd = htobe32(last_write_cmd | (last_cmd_len << 8));
|
||||
|
||||
if (!last_dcd) {
|
||||
if ((cmd >> 24) == TAG_WRITE) {
|
||||
last_write_cmd = cmd;
|
||||
last_dcd = &dcdtable[curdcd++];
|
||||
*last_dcd = htobe32(cmd);
|
||||
last_cmd_len = sizeof(uint32_t);
|
||||
last_cmd = cmd;
|
||||
last_cmd_len = sizeof(uint32_t) * 3;
|
||||
} else {
|
||||
last_write_cmd = 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -303,7 +299,6 @@ static int write_mem_v2(uint32_t addr, uint32_t val, int width)
|
|||
|
||||
check_last_dcd(cmd);
|
||||
|
||||
last_cmd_len += sizeof(uint32_t) * 2;
|
||||
dcdtable[curdcd++] = htobe32(addr);
|
||||
dcdtable[curdcd++] = htobe32(val);
|
||||
|
||||
|
|
@ -370,11 +365,11 @@ static int do_cmd_check(int argc, char *argv[])
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
cmd = (TAG_CHECK << 24) | (i << 3) | width;
|
||||
cmd = (TAG_CHECK << 24) | (i << 3) | width | ((sizeof(uint32_t) * 3) << 8);
|
||||
|
||||
check_last_dcd(cmd);
|
||||
|
||||
last_cmd_len += sizeof(uint32_t) * 2;
|
||||
dcdtable[curdcd++] = htobe32(cmd);
|
||||
dcdtable[curdcd++] = htobe32(addr);
|
||||
dcdtable[curdcd++] = htobe32(mask);
|
||||
|
||||
|
|
@ -454,14 +449,15 @@ static int do_dcd_offset(int argc, char *argv[])
|
|||
struct soc_type {
|
||||
char *name;
|
||||
int header_version;
|
||||
int cpu_type;
|
||||
};
|
||||
|
||||
static struct soc_type socs[] = {
|
||||
{ .name = "imx25", .header_version = 1, },
|
||||
{ .name = "imx35", .header_version = 1, },
|
||||
{ .name = "imx51", .header_version = 1, },
|
||||
{ .name = "imx53", .header_version = 2, },
|
||||
{ .name = "imx6", .header_version = 2, },
|
||||
{ .name = "imx25", .header_version = 1, .cpu_type = 25},
|
||||
{ .name = "imx35", .header_version = 1, .cpu_type = 35 },
|
||||
{ .name = "imx51", .header_version = 1, .cpu_type = 51 },
|
||||
{ .name = "imx53", .header_version = 2, .cpu_type = 53 },
|
||||
{ .name = "imx6", .header_version = 2, .cpu_type = 6 },
|
||||
};
|
||||
|
||||
static int do_soc(int argc, char *argv[])
|
||||
|
|
@ -477,6 +473,7 @@ static int do_soc(int argc, char *argv[])
|
|||
for (i = 0; i < ARRAY_SIZE(socs); i++) {
|
||||
if (!strcmp(socs[i].name, soc)) {
|
||||
header_version = socs[i].header_version;
|
||||
cpu_type = socs[i].cpu_type;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
|
@ -767,6 +764,14 @@ int main(int argc, char *argv[])
|
|||
exit(1);
|
||||
}
|
||||
|
||||
if (cpu_type == 35) {
|
||||
ret = xwrite(outfd, buf, 4096);
|
||||
if (ret < 0) {
|
||||
perror("write");
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
infd = open(imagename, O_RDONLY);
|
||||
if (infd < 0) {
|
||||
perror("open");
|
||||
|
|
|
|||
|
|
@ -615,8 +615,10 @@ static int write_dcd_table_ivt(struct libusb_device_handle *h, struct usb_id *p_
|
|||
printf("sub dcd length %x\n", s_length);
|
||||
|
||||
if ((dcd[0] != 0xcc) || (dcd[3] != 0x04)) {
|
||||
printf("Unknown sub tag\n");
|
||||
return -1;
|
||||
printf("Skipping unknown sub tag 0x%02x with len %04x\n", dcd[0], s_length);
|
||||
usleep(50000);
|
||||
dcd += s_length;
|
||||
continue;
|
||||
}
|
||||
dcd += 4;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue