Merge branch 'for-next/friendlyarm'
This commit is contained in:
Sascha Hauer
commit
2b3bf599b3
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|
@ -123,7 +123,7 @@ board-$(CONFIG_MACH_FREESCALE_MX51_PDK) := freescale-mx51-pdk
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|||
board-$(CONFIG_MACH_FREESCALE_MX53_LOCO) := freescale-mx53-loco
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||||
board-$(CONFIG_MACH_FREESCALE_MX53_SMD) := freescale-mx53-smd
|
||||
board-$(CONFIG_MACH_GUF_CUPID) := guf-cupid
|
||||
board-$(CONFIG_MACH_MINI2440) := mini2440
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||||
board-$(CONFIG_MACH_MINI2440) := friendlyarm-mini2440
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||||
board-$(CONFIG_MACH_QIL_A9260) := qil-a9260
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||||
board-$(CONFIG_MACH_TNY_A9260) := tny-a926x
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||||
board-$(CONFIG_MACH_TNY_A9263) := tny-a926x
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||||
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@ -138,6 +138,7 @@ board-$(CONFIG_MACH_TX51) := karo-tx51
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|||
board-$(CONFIG_MACH_MX6Q_ARM2) := freescale-mx6-arm2
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board-$(CONFIG_MACH_TOSHIBA_AC100) := toshiba-ac100
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||||
board-$(CONFIG_MACH_CCMX51) := ccxmx51
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board-$(CONFIG_MACH_TINY210) := friendlyarm-tiny210
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||||
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||||
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
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||||
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|
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|||
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@ -0,0 +1 @@
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obj-y += tiny210.o lowlevel.o
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||||
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@ -0,0 +1,19 @@
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|||
#define S5PCXX_CLOCK_REFERENCE 24000000
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||||
#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
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||||
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#define BOARD_APLL_VAL set_pll(0x7d, 0x3, 0x1)
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||||
#define BOARD_MPLL_VAL set_pll(0x29b, 0xc, 0x1)
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||||
#define BOARD_EPLL_VAL set_pll(0x60, 0x6, 0x2)
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||||
#define BOARD_VPLL_VAL set_pll(0x6c, 0x6, 0x3)
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|
||||
#define BOARD_CLK_DIV0_MASK 0xFFFFFFFF
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||||
#define BOARD_CLK_DIV0_VAL 0x14131440
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||||
#define BOARD_APLL_LOCKTIME 0x2cf
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||||
|
||||
#define S5P_DRAM_WR 3
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||||
#define S5P_DRAM_CAS 4
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||||
#define DMC_TIMING_AREF 0x00000618
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||||
#define DMC_TIMING_ROW 0x2B34438A
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||||
#define DMC_TIMING_DATA 0x24240000
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||||
#define DMC_TIMING_PWR 0x0BDC0343
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@ -0,0 +1,72 @@
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|||
/*
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||||
* Copyright (C) 2012 Alexey Galakhov
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||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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||||
*/
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#include <config.h>
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <asm/barebox-arm.h>
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#include <asm/sections.h>
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#include <mach/s3c-iomap.h>
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#include <mach/s3c-clocks.h>
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#include <mach/s3c-generic.h>
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||||
/*
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* iROM boot from MMC
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||||
* TODO: replace this by native boot
|
||||
*/
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||||
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#define ADDR_V210_SDMMC_BASE 0xD0037488
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#define ADDR_CopySDMMCtoMem 0xD0037F98
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int __bare_init s5p_irom_load_mmc(void *dest, uint32_t start_block, uint16_t block_count)
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{
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typedef uint32_t (*func_t) (int32_t, uint32_t, uint16_t, uint32_t*, int8_t);
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uint32_t chbase = readl(ADDR_V210_SDMMC_BASE);
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func_t func = (func_t)readl(ADDR_CopySDMMCtoMem);
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int chan = (chbase - 0xEB000000) >> 20;
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if (chan != 0 && chan != 2)
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return 0;
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return func(chan, start_block, block_count, (uint32_t*)dest, 0) ? 1 : 0;
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}
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void __bare_init board_init_lowlevel(void)
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{
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uint32_t r;
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#ifdef CONFIG_S3C_PLL_INIT
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s5p_init_pll();
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#endif
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if (get_pc() < 0xD0000000) /* Are we running from iRAM? */
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return; /* No, we don't. */
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s5p_init_dram_bank_ddr2(S5P_DMC0_BASE, 0x20E00323, 0, 0);
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if (! s5p_irom_load_mmc((void*)TEXT_BASE - 16, 1, (barebox_image_size + 16 + 511) / 512))
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while (1) { } /* hang */
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||||
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||||
/* Jump to SDRAM */
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||||
r = (unsigned)TEXT_BASE;
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||||
__asm__ __volatile__("mov pc, %0" : : "r"(r));
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while (1) { } /* hang */
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||||
}
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||||
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@ -0,0 +1,113 @@
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|||
/*
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||||
* Copyright (C) 2012 Alexey Galakhov
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||||
* Based on Mini6410 code by Juergen Beisert
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||||
*
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||||
* Copyright (C) 2012 Juergen Beisert, Pengutronix
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||||
*
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||||
* In some ways inspired by code
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||||
*
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||||
* (C) Copyright 2002
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||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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*
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
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||||
|
||||
#include <common.h>
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#include <driver.h>
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#include <init.h>
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||||
#include <sizes.h>
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||||
#include <generated/mach-types.h>
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#include <dm9000.h>
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#include <gpio.h>
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#include <led.h>
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#include <io.h>
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#include <nand.h>
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#include <asm/armlinux.h>
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#include <mach/s3c-iomap.h>
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#include <mach/s3c-clocks.h>
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||||
#include <mach/s3c-generic.h>
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||||
|
||||
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||||
static const unsigned pin_usage[] = {
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||||
/* TODO */
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||||
};
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||||
|
||||
static struct gpio_led leds[] = {
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||||
{
|
||||
.gpio = GPJ20,
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.led = {
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||||
.name = "led1",
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||||
}
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||||
}, {
|
||||
.gpio = GPJ21,
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||||
.led = {
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||||
.name = "led2",
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||||
}
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||||
}, {
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||||
.gpio = GPJ22,
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||||
.led = {
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||||
.name = "led3",
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||||
}
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||||
}, {
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||||
.gpio = GPJ23,
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.led = {
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||||
.name = "led4",
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||||
}
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||||
}
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||||
};
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||||
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||||
static int tiny210_mem_init(void)
|
||||
{
|
||||
arm_add_mem_device("ram0", S3C_SDRAM_BASE, s5p_get_memory_size());
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return 0;
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||||
}
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mem_initcall(tiny210_mem_init);
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static int tiny210_console_init(void)
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{
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/*
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* configure the UART1 right now, as barebox will
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* start to send data immediately
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||||
*/
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s3c_gpio_mode(GPA00_RXD0 | ENABLE_PU);
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s3c_gpio_mode(GPA01_TXD0);
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s3c_gpio_mode(GPA02_NCTS0 | ENABLE_PU);
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s3c_gpio_mode(GPA03_NRTS0);
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add_generic_device("s3c_serial", -1, NULL,
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S3C_UART1_BASE, S3C_UART1_SIZE,
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IORESOURCE_MEM, NULL);
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return 0;
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}
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console_initcall(tiny210_console_init);
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static int tiny210_devices_init(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(pin_usage); i++)
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s3c_gpio_mode(pin_usage[i]);
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for (i = 0; i < ARRAY_SIZE(leds); i++) {
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leds[i].active_low = 1;
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gpio_direction_output(leds[i].gpio, leds[i].active_low);
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led_gpio_register(&leds[i]);
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}
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armlinux_set_bootparams((void*)S3C_SDRAM_BASE + 0x100);
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armlinux_set_architecture(MACH_TYPE_MINI210);
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return 0;
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}
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device_initcall(tiny210_devices_init);
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@ -12,7 +12,7 @@ CONFIG_GLOB=y
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CONFIG_CMDLINE_EDITING=y
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CONFIG_AUTO_COMPLETE=y
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CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
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CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/mini2440/env"
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CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/friendlyarm-mini2440/env"
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CONFIG_DEBUG_INFO=y
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CONFIG_CMD_EDIT=y
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CONFIG_CMD_SLEEP=y
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@ -0,0 +1,17 @@
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CONFIG_ARCH_S5PCxx=y
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CONFIG_CPU_V7=y
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CONFIG_CPU_32v7=y
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CONFIG_BOARDINFO="Tiny 210"
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CONFIG_ARCH_BAREBOX_MAX_BARE_INIT_SIZE=0x1ff0
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CONFIG_ARCH_SAMSUNG=y
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CONFIG_CPU_S5PV210=y
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CONFIG_MACH_TINY210=y
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CONFIG_S3C_LOWLEVEL_INIT=y
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CONFIG_S3C_PLL_INIT=y
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CONFIG_S3C_SDRAM_INIT=y
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CONFIG_CMD_LED=y
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CONFIG_CMD_LED_TRIGGER=y
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CONFIG_DRIVER_SERIAL_S3C=y
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CONFIG_LED=y
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CONFIG_LED_GPIO=y
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CONFIG_LED_TRIGGERS=y
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@ -8,11 +8,13 @@ config ARCH_TEXT_BASE
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default 0x31fc0000 if MACH_MINI2440
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default 0x31fc0000 if MACH_A9M2440
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default 0x31fc0000 if MACH_A9M2410
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default 0x23e00000 if MACH_TINY210
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config BOARDINFO
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default "Mini 2440" if MACH_MINI2440
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default "Digi A9M2440" if MACH_A9M2440
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default "Digi A9M2410" if MACH_A9M2410
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||||
default "Tiny 210" if MACH_TINY210
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||||
config ARCH_BAREBOX_MAX_BARE_INIT_SIZE
|
||||
hex
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@ -78,7 +80,7 @@ config MACH_A9M2410DEV
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||||
endchoice
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||||
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||||
source arch/arm/boards/mini2440/Kconfig
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source arch/arm/boards/friendlyarm-mini2440/Kconfig
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||||
|
||||
endmenu
|
||||
|
||||
|
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@ -92,12 +94,18 @@ config CPU_S5PC110
|
|||
config CPU_S5PV210
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bool
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#choice
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#
|
||||
# prompt "S5PCxx board type"
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||||
#
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||||
#
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||||
#endchoice
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||||
choice
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||||
|
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prompt "S5PCxx board type"
|
||||
|
||||
config MACH_TINY210
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bool "Tiny 210"
|
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select CPU_S5PV210
|
||||
select MACH_HAS_LOWLEVEL_INIT
|
||||
select MACH_DO_LOWLEVEL_INIT
|
||||
select S3C_SDRAM_INIT
|
||||
|
||||
endchoice
|
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|
||||
endif
|
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|
||||
|
|
|
|||
|
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@ -2,5 +2,5 @@ obj-y += s3c-timer.o generic.o
|
|||
obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
|
||||
obj-lowlevel-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
|
||||
obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o s3c24xx-clocks.o mem-s3c24x0.o
|
||||
obj-$(CONFIG_ARCH_S5PCxx) += gpio-s5pcxx.o clocks-s5pcxx.o
|
||||
obj-$(CONFIG_ARCH_S5PCxx) += gpio-s5pcxx.o clocks-s5pcxx.o mem-s5pcxx.o
|
||||
obj-$(CONFIG_S3C_LOWLEVEL_INIT) += $(obj-lowlevel-y)
|
||||
|
|
|
|||
|
|
@ -24,6 +24,8 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
uint32_t s3c_get_mpllclk(void);
|
||||
uint32_t s3c_get_upllclk(void);
|
||||
uint32_t s3c_get_fclk(void);
|
||||
|
|
@ -40,4 +42,8 @@ void s3c24xx_disable_second_sdram_bank(void);
|
|||
|
||||
#ifdef CONFIG_ARCH_S5PCxx
|
||||
void s5p_init_pll(void);
|
||||
void s5p_init_dram_bank_lpddr(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16);
|
||||
void s5p_init_dram_bank_lpddr2(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16);
|
||||
void s5p_init_dram_bank_ddr2(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16);
|
||||
uint32_t s5p_get_memory_size(void);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -47,3 +47,6 @@
|
|||
#define S3C_UART3_SIZE 0x400
|
||||
#define S3C_UART_HAS_UBRDIVSLOT
|
||||
#define S3C_UART_HAS_UINTM
|
||||
|
||||
#define S5P_DMC0_BASE 0xF0000000
|
||||
#define S5P_DMC1_BASE 0xF1400000
|
||||
|
|
|
|||
|
|
@ -0,0 +1,320 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Alexey Galakhov
|
||||
*
|
||||
* Based on code from u-boot found somewhere on the web
|
||||
* that seems to originate from Samsung
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <io.h>
|
||||
#include <init.h>
|
||||
#include <mach/s3c-generic.h>
|
||||
#include <mach/s3c-iomap.h>
|
||||
|
||||
#define S5P_DMC_CONCONTROL 0x00
|
||||
#define S5P_DMC_MEMCONTROL 0x04
|
||||
#define S5P_DMC_MEMCONFIG0 0x08
|
||||
#define S5P_DMC_MEMCONFIG1 0x0C
|
||||
#define S5P_DMC_DIRECTCMD 0x10
|
||||
#define S5P_DMC_PRECHCONFIG 0x14
|
||||
#define S5P_DMC_PHYCONTROL0 0x18
|
||||
#define S5P_DMC_PHYCONTROL1 0x1C
|
||||
#define S5P_DMC_PWRDNCONFIG 0x28
|
||||
#define S5P_DMC_TIMINGAREF 0x30
|
||||
#define S5P_DMC_TIMINGROW 0x34
|
||||
#define S5P_DMC_TIMINGDATA 0x38
|
||||
#define S5P_DMC_TIMINGPOWER 0x3C
|
||||
#define S5P_DMC_PHYSTATUS 0x40
|
||||
#define S5P_DMC_MRSTATUS 0x54
|
||||
|
||||
/* DRAM commands */
|
||||
#define CMD(x) ((x) << 24)
|
||||
#define BANK(x) ((x) << 16)
|
||||
#define CHIP(x) ((x) << 20)
|
||||
#define ADDR(x) (x)
|
||||
|
||||
/**
|
||||
* MR definition:
|
||||
* 1 11
|
||||
* 2 1098 7654 3210
|
||||
* | | ^^^- burst length, 010=4, 011=8
|
||||
* | | ^- burst type 0=sequnential, 1=interleaved
|
||||
* | ^^^-- CAS latency
|
||||
* | ^----- test, 0=normal, 1=test
|
||||
* |^---- DLL reset, 1=yes
|
||||
* ^^^----- WR, 1=2, 2=3 etc.
|
||||
* ^------- PD, 0=fast exit, 1=low power
|
||||
*
|
||||
* EMR1 definition:
|
||||
* 1 11
|
||||
* 2 1098 7654 3210
|
||||
* | ^- DLL, 0=enable
|
||||
* | ^-- output strength, 0=full, 1=reduced
|
||||
* |^.. .^--- Rtt, 00=off, 01=75, 10=150, 11=50 Ohm
|
||||
* | ^^ ^-- Posted CAS# AL, 0-6
|
||||
* ^^ ^------ OCD: 000=OCD exit, 111=enable defaults
|
||||
* ^------ DQS#, 0=enable, 1=disable
|
||||
* ^------- RDQS enable, 0=no, 1=yes
|
||||
* ^-------- outputs, 0=enabled, 1=disabled
|
||||
*
|
||||
* EMR2 definition:
|
||||
* bit 7
|
||||
* 1 1
|
||||
* 2 1098 7654 3210
|
||||
* ^-- SRT, 0=1x (0-85 deg.C), 1=2x (>85 deg.C)
|
||||
* all other bits = 0
|
||||
*
|
||||
* EMR3 definition: all bits 0
|
||||
*/
|
||||
|
||||
#define MRS CMD(0x0)
|
||||
#define PALL CMD(0x1)
|
||||
#define PRE CMD(0x2)
|
||||
#define DPD CMD(0x3)
|
||||
#define REFS CMD(0x4)
|
||||
#define REFA CMD(0x5)
|
||||
#define CKEL CMD(0x6)
|
||||
#define NOP CMD(0x7)
|
||||
#define REFSX CMD(0x8)
|
||||
#define MRR CMD(0x9)
|
||||
|
||||
#define EMRS1 (MRS | BANK(1))
|
||||
#define EMRS2 (MRS | BANK(2))
|
||||
#define EMRS3 (MRS | BANK(3))
|
||||
|
||||
/* Burst is (1 << S5P_DRAM_BURST), i.e. S5P_DRAM_BURST=2 for burst 4 */
|
||||
#ifndef S5P_DRAM_BURST
|
||||
/* (LP)DDR2 supports burst 4 only, make it default */
|
||||
# define S5P_DRAM_BURST 2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Initialization sequences for different kinds of DRAM
|
||||
*/
|
||||
#define dcmd(x) writel((x) | CHIP(chip), base + S5P_DMC_DIRECTCMD)
|
||||
|
||||
static void __bare_init s5p_dram_init_seq_lpddr(phys_addr_t base, unsigned chip)
|
||||
{
|
||||
const uint32_t emr = 0x400; /* DQS disable */
|
||||
const uint32_t mr = (((S5P_DRAM_WR) - 1) << 9)
|
||||
| ((S5P_DRAM_CAS) << 4)
|
||||
| (S5P_DRAM_BURST);
|
||||
/* TODO this sequence is untested */
|
||||
dcmd(PALL); dcmd(REFA); dcmd(REFA);
|
||||
dcmd(MRS | ADDR(mr));
|
||||
dcmd(EMRS1 | ADDR(emr));
|
||||
}
|
||||
|
||||
static void __bare_init s5p_dram_init_seq_lpddr2(phys_addr_t base, unsigned chip)
|
||||
{
|
||||
const uint32_t mr = (((S5P_DRAM_WR) - 1) << 9)
|
||||
| ((S5P_DRAM_CAS) << 4)
|
||||
| (S5P_DRAM_BURST);
|
||||
/* TODO this sequence is untested */
|
||||
dcmd(NOP);
|
||||
dcmd(MRS | ADDR(mr));
|
||||
do {
|
||||
dcmd(MRR);
|
||||
} while (readl(base + S5P_DMC_MRSTATUS) & 0x01); /* poll DAI */
|
||||
}
|
||||
|
||||
static void __bare_init s5p_dram_init_seq_ddr2(phys_addr_t base, unsigned chip)
|
||||
{
|
||||
const uint32_t emr = 0x400; /* DQS disable */
|
||||
const uint32_t mr = (((S5P_DRAM_WR) - 1) << 9)
|
||||
| ((S5P_DRAM_CAS) << 4)
|
||||
| (S5P_DRAM_BURST);
|
||||
dcmd(NOP);
|
||||
/* FIXME wait here? JEDEC recommends but nobody does */
|
||||
dcmd(PALL); dcmd(EMRS2); dcmd(EMRS3);
|
||||
dcmd(EMRS1 | ADDR(emr)); /* DQS disable */
|
||||
dcmd(MRS | ADDR(mr | 0x100)); /* DLL reset */
|
||||
dcmd(PALL); dcmd(REFA); dcmd(REFA);
|
||||
dcmd(MRS | ADDR(mr)); /* DLL no reset */
|
||||
dcmd(EMRS1 | ADDR(emr | 0x380)); /* OCD defaults */
|
||||
dcmd(EMRS1 | ADDR(emr)); /* OCD exit */
|
||||
}
|
||||
|
||||
#undef dcmd
|
||||
|
||||
static inline void __bare_init s5p_dram_start_dll(phys_addr_t base, uint32_t phycon1)
|
||||
{
|
||||
uint32_t pc0 = 0x00101000; /* the only legal initial value */
|
||||
uint32_t lv;
|
||||
|
||||
/* Init DLL */
|
||||
writel(pc0, base + S5P_DMC_PHYCONTROL0);
|
||||
writel(phycon1, base + S5P_DMC_PHYCONTROL1);
|
||||
|
||||
/* DLL on */
|
||||
pc0 |= 0x2;
|
||||
writel(pc0, base + S5P_DMC_PHYCONTROL0);
|
||||
|
||||
/* DLL start */
|
||||
pc0 |= 0x1;
|
||||
writel(pc0, base + S5P_DMC_PHYCONTROL0);
|
||||
|
||||
/* Find lock val */
|
||||
do {
|
||||
lv = readl(base + S5P_DMC_PHYSTATUS);
|
||||
} while ((lv & 0x7) != 0x7);
|
||||
|
||||
lv >>= 6;
|
||||
lv &= 0xff; /* ctrl_lock_value[9:2] - coarse */
|
||||
pc0 |= (lv << 24); /* ctrl_force */
|
||||
writel(pc0, base + S5P_DMC_PHYCONTROL0); /* force value locking */
|
||||
}
|
||||
|
||||
static inline void __bare_init s5p_dram_setup(phys_addr_t base, uint32_t mc0, uint32_t mc1,
|
||||
int bus16, uint32_t mcon)
|
||||
{
|
||||
mcon |= (S5P_DRAM_BURST) << 20;
|
||||
/* 16 or 32-bit bus ? */
|
||||
mcon |= bus16 ? 0x1000 : 0x2000;
|
||||
if (mc1)
|
||||
mcon |= 0x10000; /* two chips */
|
||||
|
||||
writel(mcon, base + S5P_DMC_MEMCONTROL);
|
||||
|
||||
/* Set up memory layout */
|
||||
writel(mc0, base + S5P_DMC_MEMCONFIG0);
|
||||
if (mc1)
|
||||
writel(mc1, base + S5P_DMC_MEMCONFIG1);
|
||||
|
||||
/* Open page precharge policy - reasonable defaults */
|
||||
writel(0xFF000000, base + S5P_DMC_PRECHCONFIG);
|
||||
|
||||
/* Set up timings */
|
||||
writel(DMC_TIMING_AREF, base + S5P_DMC_TIMINGAREF);
|
||||
writel(DMC_TIMING_ROW, base + S5P_DMC_TIMINGROW);
|
||||
writel(DMC_TIMING_DATA, base + S5P_DMC_TIMINGDATA);
|
||||
writel(DMC_TIMING_PWR, base + S5P_DMC_TIMINGPOWER);
|
||||
}
|
||||
|
||||
static inline void __bare_init s5p_dram_start(phys_addr_t base)
|
||||
{
|
||||
/* Reasonable defaults and auto-refresh on */
|
||||
writel(0x0FFF1070, base + S5P_DMC_CONCONTROL);
|
||||
/* Reasonable defaults */
|
||||
writel(0xFFFF00FF, base + S5P_DMC_PWRDNCONFIG);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize LPDDR memory bank
|
||||
* TODO: this function is untested, see also init_seq function
|
||||
*/
|
||||
void __bare_init s5p_init_dram_bank_lpddr(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16)
|
||||
{
|
||||
/* refcount 8, 90 deg. shift */
|
||||
s5p_dram_start_dll(base, 0x00000085);
|
||||
/* LPDDR type */
|
||||
s5p_dram_setup(base, mc0, mc1, bus16, 0x100);
|
||||
|
||||
/* Start-Up Commands */
|
||||
s5p_dram_init_seq_lpddr(base, 0);
|
||||
if (mc1)
|
||||
s5p_dram_init_seq_lpddr(base, 1);
|
||||
|
||||
s5p_dram_start(base);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize LPDDR2 memory bank
|
||||
* TODO: this function is untested, see also init_seq function
|
||||
*/
|
||||
void __bare_init s5p_init_dram_bank_lpddr2(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16)
|
||||
{
|
||||
/* refcount 8, 90 deg. shift */
|
||||
s5p_dram_start_dll(base, 0x00000085);
|
||||
/* LPDDR2 type */
|
||||
s5p_dram_setup(base, mc0, mc1, bus16, 0x200);
|
||||
|
||||
/* Start-Up Commands */
|
||||
s5p_dram_init_seq_lpddr2(base, 0);
|
||||
if (mc1)
|
||||
s5p_dram_init_seq_lpddr2(base, 1);
|
||||
|
||||
s5p_dram_start(base);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize DDR2 memory bank
|
||||
*/
|
||||
void __bare_init s5p_init_dram_bank_ddr2(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16)
|
||||
{
|
||||
/* refcount 8, 180 deg. shift */
|
||||
s5p_dram_start_dll(base, 0x00000086);
|
||||
/* DDR2 type */
|
||||
s5p_dram_setup(base, mc0, mc1, bus16, 0x400);
|
||||
|
||||
/* Start-Up Commands */
|
||||
s5p_dram_init_seq_ddr2(base, 0);
|
||||
if (mc1)
|
||||
s5p_dram_init_seq_ddr2(base, 1);
|
||||
|
||||
s5p_dram_start(base);
|
||||
}
|
||||
|
||||
|
||||
#define BANK_ENABLED(base) (readl((base) + S5P_DMC_PHYCONTROL0) & 1)
|
||||
#define NUM_EXTRA_CHIPS(base) ((readl((base) + S5P_DMC_MEMCONTROL) >> 16) & 0xF)
|
||||
|
||||
#define BANK_START(x) ((x) & 0xFF000000)
|
||||
#define BANK_END(x) (BANK_START(x) | ~(((x) & 0x00FF0000) << 8))
|
||||
#define BANK_LEN(x) (BANK_END(x) - BANK_START(x) + 1)
|
||||
|
||||
static inline void sortswap(uint32_t *x, uint32_t *y)
|
||||
{
|
||||
if (*y < *x) {
|
||||
*x ^= *y;
|
||||
*y ^= *x;
|
||||
*x ^= *y;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t s5p_get_memory_size(void)
|
||||
{
|
||||
int i;
|
||||
uint32_t len;
|
||||
uint32_t mc[4] = { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF };
|
||||
/* Read MEMCONFIG registers */
|
||||
if (BANK_ENABLED(S5P_DMC0_BASE)) {
|
||||
mc[0] = readl(S5P_DMC0_BASE + S5P_DMC_MEMCONFIG0);
|
||||
if (NUM_EXTRA_CHIPS(S5P_DMC0_BASE) > 0)
|
||||
mc[1] = readl(S5P_DMC0_BASE + S5P_DMC_MEMCONFIG1);
|
||||
}
|
||||
if (BANK_ENABLED(S5P_DMC1_BASE)) {
|
||||
mc[2] = readl(S5P_DMC1_BASE + S5P_DMC_MEMCONFIG0);
|
||||
if (NUM_EXTRA_CHIPS(S5P_DMC1_BASE) > 0)
|
||||
mc[3] = readl(S5P_DMC1_BASE + S5P_DMC_MEMCONFIG1);
|
||||
}
|
||||
/* Sort using a sorting network */
|
||||
sortswap(mc + 0, mc + 2);
|
||||
sortswap(mc + 1, mc + 3);
|
||||
sortswap(mc + 0, mc + 1);
|
||||
sortswap(mc + 2, mc + 3);
|
||||
sortswap(mc + 1, mc + 2);
|
||||
/* Is at least one chip enabled? */
|
||||
if (mc[0] == 0xFFFFFFFF)
|
||||
return 0;
|
||||
/* Determine maximum continuous region at start */
|
||||
len = BANK_LEN(mc[0]);
|
||||
for (i = 1; i < 4; ++i) {
|
||||
if (BANK_START(mc[i]) == BANK_END(mc[i - 1]) + 1)
|
||||
len += BANK_LEN(mc[i]);
|
||||
else
|
||||
break;
|
||||
}
|
||||
return len;
|
||||
}
|
||||
Loading…
Reference in New Issue