ARM: add initial i.MX6 support
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
parent
a58bfe06b5
commit
2e7db33d4b
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@ -68,7 +68,7 @@ choice
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config ARCH_IMX_INTERNAL_BOOT
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bool "support internal boot mode"
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depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51 || ARCH_IMX53
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depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51 || ARCH_IMX53 || ARCH_IMX6
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config ARCH_IMX_EXTERNAL_BOOT
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bool "support external boot mode"
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@ -165,6 +165,11 @@ config ARCH_IMX53
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select CPU_V7
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select ARCH_HAS_FEC_IMX
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config ARCH_IMX6
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bool "i.MX6"
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select ARCH_HAS_FEC_IMX
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select CPU_V7
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endchoice
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# ----------------------------------------------------------
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@ -7,6 +7,7 @@ obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o
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obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o
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obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o imx5.o
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obj-$(CONFIG_ARCH_IMX53) += speed-imx53.o imx53.o iomux-v3.o imx5.o
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obj-$(CONFIG_ARCH_IMX6) += speed-imx6.o imx6.o iomux-v3.o
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obj-$(CONFIG_IMX_CLKO) += clko.o
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obj-$(CONFIG_IMX_IIM) += iim.o
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obj-$(CONFIG_NAND_IMX) += nand.o
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@ -0,0 +1,71 @@
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <init.h>
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#include <common.h>
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#include <io.h>
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#include <sizes.h>
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#include <mach/imx6-regs.h>
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#include "gpio.h"
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void *imx_gpio_base[] = {
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(void *)MX6_GPIO1_BASE_ADDR,
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(void *)MX6_GPIO2_BASE_ADDR,
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(void *)MX6_GPIO3_BASE_ADDR,
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(void *)MX6_GPIO4_BASE_ADDR,
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(void *)MX6_GPIO5_BASE_ADDR,
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(void *)MX6_GPIO6_BASE_ADDR,
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(void *)MX6_GPIO7_BASE_ADDR,
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};
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int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32;
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void imx6_init_lowlevel(void)
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{
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void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR;
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void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR;
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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writel(0x77777777, aips1);
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writel(0x77777777, aips1 + 0x4);
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writel(0, aips1 + 0x40);
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writel(0, aips1 + 0x44);
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writel(0, aips1 + 0x48);
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writel(0, aips1 + 0x4c);
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writel(0, aips1 + 0x50);
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writel(0x77777777, aips2);
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writel(0x77777777, aips2 + 0x4);
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writel(0, aips2 + 0x40);
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writel(0, aips2 + 0x44);
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writel(0, aips2 + 0x48);
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writel(0, aips2 + 0x4c);
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writel(0, aips2 + 0x50);
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/* enable all clocks */
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writel(0xffffffff, 0x020c4068);
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writel(0xffffffff, 0x020c406c);
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writel(0xffffffff, 0x020c4070);
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writel(0xffffffff, 0x020c4074);
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writel(0xffffffff, 0x020c4078);
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writel(0xffffffff, 0x020c407c);
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writel(0xffffffff, 0x020c4080);
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}
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@ -0,0 +1,347 @@
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/*
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* Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef __ARCH_ARM_MACH_MX6_CRM_REGS_H__
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#define __ARCH_ARM_MACH_MX6_CRM_REGS_H__
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#define MXC_CCM_BASE MX6_CCM_BASE_ADDR
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/* Register addresses of CCM*/
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#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00)
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#define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04)
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#define MXC_CCM_CSR (MXC_CCM_BASE + 0x08)
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#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C)
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#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10)
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#define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14)
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#define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18)
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#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C)
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#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20)
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#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24)
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#define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28)
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#define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C)
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#define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30)
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#define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34)
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#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38)
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#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C)
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#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40)
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#define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44)
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#define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48)
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#define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C)
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#define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50)
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#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54)
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#define MXC_CCM_CISR (MXC_CCM_BASE + 0x58)
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#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C)
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#define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60)
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#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64)
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#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68)
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#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C)
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#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70)
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#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74)
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#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78)
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#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C)
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#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80)
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#define MXC_CCM_CCGR7 (MXC_CCM_BASE + 0x80)
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#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x88)
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/* Define the bits in register CCR */
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#define MXC_CCM_CCR_RBC_EN (1 << 27)
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#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
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#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET (21)
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#define MXC_CCM_CCR_WB_COUNT_MASK (0x7)
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#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
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#define MXC_CCM_CCR_COSC_EN (1 << 12)
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#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
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#define MXC_CCM_CCR_OSCNT_OFFSET (0)
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/* Define the bits in register CCDR */
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#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
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#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
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/* Define the bits in register CSR */
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#define MXC_CCM_CSR_COSC_READY (1 << 5)
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#define MXC_CCM_CSR_REF_EN_B (1 << 0)
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/* Define the bits in register CCSR */
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#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
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#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
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#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
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#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
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#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
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#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
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#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
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#define MXC_CCM_CCSR_STEP_SEL (1 << 8)
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#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
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#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
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#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
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/* Define the bits in register CACRR */
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#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
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#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
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/* Define the bits in register CBCDR */
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#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
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#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET (27)
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#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
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#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
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#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
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#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET (19)
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#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
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#define MXC_CCM_CBCDR_AXI_PODF_OFFSET (16)
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#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
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#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
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#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
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#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
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#define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
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#define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
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#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3)
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#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET (3)
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#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0)
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#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET (0)
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/* Define the bits in register CBCMR */
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#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
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#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET (29)
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#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
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#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET (26)
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#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
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#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET (23)
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#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
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#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET (21)
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#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
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#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
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#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET (18)
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#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
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#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (16)
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#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
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#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
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#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
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#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET (12)
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#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
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#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
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#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
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#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET (8)
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#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
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#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET (4)
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#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
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#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
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/* Define the bits in register CSCMR1 */
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#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
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#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET (29)
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#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
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#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET (27)
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#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
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#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET (23)
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#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
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#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET (20)
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#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
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#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
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#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
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#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
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#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14)
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#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET (14)
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#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
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#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
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#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
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#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (10)
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#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK (0x3F)
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/* Define the bits in register CSCMR2 */
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#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
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#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET (19)
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#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
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#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
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#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2)
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#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET (2)
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/* Define the bits in register CSCDR1 */
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#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
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#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET (25)
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#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
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#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET (22)
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#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
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#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET (19)
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#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16)
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#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET (16)
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#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
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#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET (11)
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#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
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#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
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#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
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#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
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#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x3F)
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#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
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/* Define the bits in register CS1CDR */
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#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
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#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET (25)
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#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
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#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET (16)
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#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
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#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET (9)
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#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
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#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
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#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
|
||||
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
|
||||
|
||||
/* Define the bits in register CS2CDR */
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET (21)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET (18)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET (16)
|
||||
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
|
||||
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET (12)
|
||||
#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
|
||||
#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET (9)
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
|
||||
|
||||
/* Define the bits in register CDCDR */
|
||||
#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
|
||||
#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET (29)
|
||||
#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET (20)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (12)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET (7)
|
||||
|
||||
/* Define the bits in register CHSCCDR */
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET (15)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET (12)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET (9)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET (6)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET (3)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET (0)
|
||||
|
||||
/* Define the bits in register CSCDR2 */
|
||||
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
|
||||
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET (19)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET (15)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET (12)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET (9)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET (6)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET (3)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK (0x7)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET (0)
|
||||
|
||||
/* Define the bits in register CSCDR3 */
|
||||
#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET (16)
|
||||
#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET (14)
|
||||
#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11)
|
||||
#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET (11)
|
||||
#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
|
||||
#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET (9)
|
||||
|
||||
/* Define the bits in register CDHIPR */
|
||||
#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
|
||||
#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
|
||||
#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
|
||||
#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
|
||||
#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
|
||||
#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
|
||||
#define MXC_CCM_CDHIPR_AXI_PODF_BUSY (1)
|
||||
|
||||
/* Define the bits in register CLPCR */
|
||||
#define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
|
||||
#define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
|
||||
#define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
|
||||
#define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
|
||||
#define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
|
||||
#define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
|
||||
#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
|
||||
#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
|
||||
#define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
|
||||
#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17)
|
||||
#define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
|
||||
#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
|
||||
#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
|
||||
#define MXC_CCM_CLPCR_VSTBY (1 << 8)
|
||||
#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
|
||||
#define MXC_CCM_CLPCR_SBYOS (1 << 6)
|
||||
#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
|
||||
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
|
||||
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
|
||||
#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
|
||||
#define MXC_CCM_CLPCR_LPM_MASK (0x3)
|
||||
#define MXC_CCM_CLPCR_LPM_OFFSET (0)
|
||||
|
||||
/* Define the bits in register CISR */
|
||||
#define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
|
||||
#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
|
||||
#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
|
||||
#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
|
||||
#define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
|
||||
#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
|
||||
#define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
|
||||
#define MXC_CCM_CISR_COSC_READY (1 << 6)
|
||||
#define MXC_CCM_CISR_LRF_PLL (1)
|
||||
|
||||
/* Define the bits in register CIMR */
|
||||
#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
|
||||
#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
|
||||
#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
|
||||
#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
|
||||
#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
|
||||
#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22)
|
||||
#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
|
||||
#define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
|
||||
#define MXC_CCM_CIMR_MASK_LRF_PLL (1)
|
||||
|
||||
/* Define the bits in register CCOSR */
|
||||
#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
|
||||
#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
|
||||
#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
|
||||
#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
|
||||
#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
|
||||
#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
|
||||
#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
|
||||
#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
|
||||
#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
|
||||
#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
|
||||
|
||||
/* Define the bits in registers CGPR */
|
||||
#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
|
||||
#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
|
||||
#define MXC_CCM_CGPR_PMIC_DELAY_SCALER (1)
|
||||
|
||||
#endif /* __ARCH_ARM_MACH_MX6_CRM_REGS_H__ */
|
|
@ -0,0 +1,46 @@
|
|||
#include <mach/devices.h>
|
||||
|
||||
static inline struct device_d *imx6_add_uart0(void)
|
||||
{
|
||||
return imx_add_uart((void *)MX6_UART1_BASE_ADDR, 0);
|
||||
}
|
||||
|
||||
static inline struct device_d *imx6_add_uart1(void)
|
||||
{
|
||||
return imx_add_uart((void *)MX6_UART2_BASE_ADDR, 1);
|
||||
}
|
||||
|
||||
static inline struct device_d *imx6_add_uart2(void)
|
||||
{
|
||||
return imx_add_uart((void *)MX6_UART3_BASE_ADDR, 2);
|
||||
}
|
||||
|
||||
static inline struct device_d *imx6_add_uart3(void)
|
||||
{
|
||||
return imx_add_uart((void *)MX6_UART4_BASE_ADDR, 3);
|
||||
}
|
||||
|
||||
static inline struct device_d *imx6_add_mmc0(struct esdhc_platform_data *pdata)
|
||||
{
|
||||
return imx_add_esdhc((void *)MX6_USDHC1_BASE_ADDR, 0, pdata);
|
||||
}
|
||||
|
||||
static inline struct device_d *imx6_add_mmc1(struct esdhc_platform_data *pdata)
|
||||
{
|
||||
return imx_add_esdhc((void *)MX6_USDHC2_BASE_ADDR, 1, pdata);
|
||||
}
|
||||
|
||||
static inline struct device_d *imx6_add_mmc2(struct esdhc_platform_data *pdata)
|
||||
{
|
||||
return imx_add_esdhc((void *)MX6_USDHC3_BASE_ADDR, 2, pdata);
|
||||
}
|
||||
|
||||
static inline struct device_d *imx6_add_mmc3(struct esdhc_platform_data *pdata)
|
||||
{
|
||||
return imx_add_esdhc((void *)MX6_USDHC4_BASE_ADDR, 3, pdata);
|
||||
}
|
||||
|
||||
static inline struct device_d *imx6_add_fec(struct fec_platform_data *pdata)
|
||||
{
|
||||
return imx_add_fec((void *)MX6_ENET_BASE_ADDR, pdata);
|
||||
}
|
|
@ -57,5 +57,11 @@ u64 imx_uid(void);
|
|||
#define cpu_is_mx53() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_IMX6
|
||||
#define cpu_is_mx6() (1)
|
||||
#else
|
||||
#define cpu_is_mx6() (0)
|
||||
#endif
|
||||
|
||||
#define cpu_is_mx23() (0)
|
||||
#define cpu_is_mx28() (0)
|
||||
|
|
|
@ -55,6 +55,8 @@
|
|||
# include <mach/imx51-regs.h>
|
||||
#elif defined CONFIG_ARCH_IMX53
|
||||
# include <mach/imx53-regs.h>
|
||||
#elif defined CONFIG_ARCH_IMX6
|
||||
# include <mach/imx6-regs.h>
|
||||
#else
|
||||
# error "unknown i.MX soc type"
|
||||
#endif
|
||||
|
|
|
@ -0,0 +1,721 @@
|
|||
/*
|
||||
* Freescale ANADIG Register Definitions
|
||||
*
|
||||
* Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM___ANADIG_H
|
||||
#define __ARCH_ARM___ANADIG_H
|
||||
|
||||
#define HW_ANADIG_PLL_SYS (0x00000000)
|
||||
#define HW_ANADIG_PLL_SYS_SET (0x00000004)
|
||||
#define HW_ANADIG_PLL_SYS_CLR (0x00000008)
|
||||
#define HW_ANADIG_PLL_SYS_TOG (0x0000000c)
|
||||
|
||||
#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
|
||||
#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
|
||||
#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
|
||||
#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
|
||||
#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
|
||||
#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
|
||||
#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
|
||||
#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
|
||||
#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
|
||||
#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
|
||||
#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
|
||||
#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
|
||||
#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
|
||||
#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
|
||||
#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
|
||||
#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
|
||||
#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
|
||||
#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
|
||||
#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
|
||||
#define BP_ANADIG_PLL_SYS_DIV_SELECT 0
|
||||
#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
|
||||
#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
|
||||
|
||||
#define HW_ANADIG_USB1_PLL_480_CTRL (0x00000010)
|
||||
#define HW_ANADIG_USB1_PLL_480_CTRL_SET (0x00000014)
|
||||
#define HW_ANADIG_USB1_PLL_480_CTRL_CLR (0x00000018)
|
||||
#define HW_ANADIG_USB1_PLL_480_CTRL_TOG (0x0000001c)
|
||||
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
|
||||
#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
|
||||
#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
|
||||
#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
|
||||
#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
|
||||
#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
|
||||
#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
|
||||
#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
|
||||
#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
|
||||
#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
|
||||
#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
|
||||
|
||||
#define HW_ANADIG_USB2_PLL_480_CTRL (0x00000020)
|
||||
#define HW_ANADIG_USB2_PLL_480_CTRL_SET (0x00000024)
|
||||
#define HW_ANADIG_USB2_PLL_480_CTRL_CLR (0x00000028)
|
||||
#define HW_ANADIG_USB2_PLL_480_CTRL_TOG (0x0000002c)
|
||||
|
||||
#define BM_ANADIG_USB2_PLL_480_CTRL_LOCK 0x80000000
|
||||
#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
|
||||
#define BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC 14
|
||||
#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
|
||||
#define BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(v) (((v) << 14) & BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC)
|
||||
#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
|
||||
#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
|
||||
#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
|
||||
#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
|
||||
#define BM_ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
|
||||
#define BM_ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
|
||||
#define BM_ANADIG_USB2_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
|
||||
#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_CP 0x00000400
|
||||
#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_CP 0x00000200
|
||||
#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_LF 0x00000100
|
||||
#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_LF 0x00000080
|
||||
#define BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
|
||||
#define BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0 2
|
||||
#define BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0 0x0000001C
|
||||
#define BF_ANADIG_USB2_PLL_480_CTRL_CONTROL0(v) (((v) << 2) & BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0)
|
||||
#define BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT 0
|
||||
#define BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT 0x00000003
|
||||
#define BF_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT(v) (((v) << 0) & BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT)
|
||||
|
||||
#define HW_ANADIG_PLL_528 (0x00000030)
|
||||
#define HW_ANADIG_PLL_528_SET (0x00000034)
|
||||
#define HW_ANADIG_PLL_528_CLR (0x00000038)
|
||||
#define HW_ANADIG_PLL_528_TOG (0x0000003c)
|
||||
|
||||
#define BM_ANADIG_PLL_528_LOCK 0x80000000
|
||||
#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
|
||||
#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
|
||||
#define BM_ANADIG_PLL_528_BYPASS 0x00010000
|
||||
#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
|
||||
#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
|
||||
#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
|
||||
#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
|
||||
#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
|
||||
#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
|
||||
#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
|
||||
#define BM_ANADIG_PLL_528_ENABLE 0x00002000
|
||||
#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
|
||||
#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
|
||||
#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
|
||||
#define BM_ANADIG_PLL_528_HALF_CP 0x00000200
|
||||
#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
|
||||
#define BM_ANADIG_PLL_528_HALF_LF 0x00000080
|
||||
#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
|
||||
|
||||
#define HW_ANADIG_PLL_528_SS (0x00000040)
|
||||
|
||||
#define BP_ANADIG_PLL_528_SS_STOP 16
|
||||
#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
|
||||
#define BF_ANADIG_PLL_528_SS_STOP(v) (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
|
||||
#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
|
||||
#define BP_ANADIG_PLL_528_SS_STEP 0
|
||||
#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
|
||||
#define BF_ANADIG_PLL_528_SS_STEP(v) (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
|
||||
|
||||
#define HW_ANADIG_PLL_528_NUM (0x00000050)
|
||||
|
||||
#define BP_ANADIG_PLL_528_NUM_A 0
|
||||
#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
|
||||
#define BF_ANADIG_PLL_528_NUM_A(v) (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
|
||||
|
||||
#define HW_ANADIG_PLL_528_DENOM (0x00000060)
|
||||
|
||||
#define BP_ANADIG_PLL_528_DENOM_B 0
|
||||
#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
|
||||
#define BF_ANADIG_PLL_528_DENOM_B(v) (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
|
||||
|
||||
#define HW_ANADIG_PLL_AUDIO (0x00000070)
|
||||
#define HW_ANADIG_PLL_AUDIO_SET (0x00000074)
|
||||
#define HW_ANADIG_PLL_AUDIO_CLR (0x00000078)
|
||||
#define HW_ANADIG_PLL_AUDIO_TOG (0x0000007c)
|
||||
|
||||
#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
|
||||
#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
|
||||
#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
|
||||
#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
|
||||
#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
|
||||
#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
|
||||
#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
|
||||
#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
|
||||
#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
|
||||
#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
|
||||
#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
|
||||
#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
|
||||
#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
|
||||
#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
|
||||
#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
|
||||
#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
|
||||
#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
|
||||
#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
|
||||
#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
|
||||
#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
|
||||
#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
|
||||
#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
|
||||
#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
|
||||
#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
|
||||
#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
|
||||
|
||||
#define HW_ANADIG_PLL_AUDIO_NUM (0x00000080)
|
||||
|
||||
#define BP_ANADIG_PLL_AUDIO_NUM_A 0
|
||||
#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
|
||||
#define BF_ANADIG_PLL_AUDIO_NUM_A(v) (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
|
||||
|
||||
#define HW_ANADIG_PLL_AUDIO_DENOM (0x00000090)
|
||||
|
||||
#define BP_ANADIG_PLL_AUDIO_DENOM_B 0
|
||||
#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
|
||||
#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
|
||||
|
||||
#define HW_ANADIG_PLL_VIDEO (0x000000a0)
|
||||
#define HW_ANADIG_PLL_VIDEO_SET (0x000000a4)
|
||||
#define HW_ANADIG_PLL_VIDEO_CLR (0x000000a8)
|
||||
#define HW_ANADIG_PLL_VIDEO_TOG (0x000000ac)
|
||||
|
||||
#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
|
||||
#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
|
||||
#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
|
||||
#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
|
||||
#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
|
||||
#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
|
||||
#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
|
||||
#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
|
||||
#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
|
||||
#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
|
||||
#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
|
||||
#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
|
||||
#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
|
||||
#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
|
||||
#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
|
||||
#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
|
||||
#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
|
||||
#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
|
||||
#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
|
||||
#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
|
||||
#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
|
||||
#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
|
||||
#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
|
||||
#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
|
||||
#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
|
||||
|
||||
#define HW_ANADIG_PLL_VIDEO_NUM (0x000000b0)
|
||||
|
||||
#define BP_ANADIG_PLL_VIDEO_NUM_A 0
|
||||
#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
|
||||
#define BF_ANADIG_PLL_VIDEO_NUM_A(v) (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
|
||||
|
||||
#define HW_ANADIG_PLL_VIDEO_DENOM (0x000000c0)
|
||||
|
||||
#define BP_ANADIG_PLL_VIDEO_DENOM_B 0
|
||||
#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
|
||||
#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
|
||||
|
||||
#define HW_ANADIG_PLL_MLB (0x000000d0)
|
||||
#define HW_ANADIG_PLL_MLB_SET (0x000000d4)
|
||||
#define HW_ANADIG_PLL_MLB_CLR (0x000000d8)
|
||||
#define HW_ANADIG_PLL_MLB_TOG (0x000000dc)
|
||||
|
||||
#define BM_ANADIG_PLL_MLB_LOCK 0x80000000
|
||||
#define BP_ANADIG_PLL_MLB_MLB_FLT_RES_SEL 26
|
||||
#define BM_ANADIG_PLL_MLB_MLB_FLT_RES_SEL 0x1C000000
|
||||
#define BF_ANADIG_PLL_MLB_MLB_FLT_RES_SEL(v) (((v) << 26) & BM_ANADIG_PLL_MLB_MLB_FLT_RES_SEL)
|
||||
#define BP_ANADIG_PLL_MLB_RX_CLK_DELAY_CFG 23
|
||||
#define BM_ANADIG_PLL_MLB_RX_CLK_DELAY_CFG 0x03800000
|
||||
#define BF_ANADIG_PLL_MLB_RX_CLK_DELAY_CFG(v) (((v) << 23) & BM_ANADIG_PLL_MLB_RX_CLK_DELAY_CFG)
|
||||
#define BP_ANADIG_PLL_MLB_VDDD_DELAY_CFG 20
|
||||
#define BM_ANADIG_PLL_MLB_VDDD_DELAY_CFG 0x00700000
|
||||
#define BF_ANADIG_PLL_MLB_VDDD_DELAY_CFG(v) (((v) << 20) & BM_ANADIG_PLL_MLB_VDDD_DELAY_CFG)
|
||||
#define BP_ANADIG_PLL_MLB_VDDA_DELAY_CFG 17
|
||||
#define BM_ANADIG_PLL_MLB_VDDA_DELAY_CFG 0x000E0000
|
||||
#define BF_ANADIG_PLL_MLB_VDDA_DELAY_CFG(v) (((v) << 17) & BM_ANADIG_PLL_MLB_VDDA_DELAY_CFG)
|
||||
#define BM_ANADIG_PLL_MLB_BYPASS 0x00010000
|
||||
#define BP_ANADIG_PLL_MLB_PHASE_SEL 12
|
||||
#define BM_ANADIG_PLL_MLB_PHASE_SEL 0x00003000
|
||||
#define BF_ANADIG_PLL_MLB_PHASE_SEL(v) (((v) << 12) & BM_ANADIG_PLL_MLB_PHASE_SEL)
|
||||
#define BM_ANADIG_PLL_MLB_HOLD_RING_OFF 0x00000800
|
||||
#define BM_ANADIG_PLL_MLB_DOUBLE_CP 0x00000400
|
||||
#define BM_ANADIG_PLL_MLB_HALF_CP 0x00000200
|
||||
|
||||
#define HW_ANADIG_PLL_ENET (0x000000e0)
|
||||
#define HW_ANADIG_PLL_ENET_SET (0x000000e4)
|
||||
#define HW_ANADIG_PLL_ENET_CLR (0x000000e8)
|
||||
#define HW_ANADIG_PLL_ENET_TOG (0x000000ec)
|
||||
|
||||
#define BM_ANADIG_PLL_ENET_LOCK 0x80000000
|
||||
#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
|
||||
#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
|
||||
#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
|
||||
#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
|
||||
#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
|
||||
#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
|
||||
#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
|
||||
#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
|
||||
#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
|
||||
#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
|
||||
#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
|
||||
#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
|
||||
#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
|
||||
#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
|
||||
#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
|
||||
#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
|
||||
#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
|
||||
#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
|
||||
#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
|
||||
#define BP_ANADIG_PLL_ENET_DIV_SELECT 0
|
||||
#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
|
||||
#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
|
||||
|
||||
#define HW_ANADIG_PFD_480 (0x000000f0)
|
||||
#define HW_ANADIG_PFD_480_SET (0x000000f4)
|
||||
#define HW_ANADIG_PFD_480_CLR (0x000000f8)
|
||||
#define HW_ANADIG_PFD_480_TOG (0x000000fc)
|
||||
|
||||
#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
|
||||
#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
|
||||
#define BP_ANADIG_PFD_480_PFD3_FRAC 24
|
||||
#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
|
||||
#define BF_ANADIG_PFD_480_PFD3_FRAC(v) (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
|
||||
#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
|
||||
#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
|
||||
#define BP_ANADIG_PFD_480_PFD2_FRAC 16
|
||||
#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
|
||||
#define BF_ANADIG_PFD_480_PFD2_FRAC(v) (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
|
||||
#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
|
||||
#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
|
||||
#define BP_ANADIG_PFD_480_PFD1_FRAC 8
|
||||
#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
|
||||
#define BF_ANADIG_PFD_480_PFD1_FRAC(v) (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
|
||||
#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
|
||||
#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
|
||||
#define BP_ANADIG_PFD_480_PFD0_FRAC 0
|
||||
#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
|
||||
#define BF_ANADIG_PFD_480_PFD0_FRAC(v) (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
|
||||
|
||||
#define HW_ANADIG_PFD_528 (0x00000100)
|
||||
#define HW_ANADIG_PFD_528_SET (0x00000104)
|
||||
#define HW_ANADIG_PFD_528_CLR (0x00000108)
|
||||
#define HW_ANADIG_PFD_528_TOG (0x0000010c)
|
||||
|
||||
#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
|
||||
#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
|
||||
#define BP_ANADIG_PFD_528_PFD3_FRAC 24
|
||||
#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
|
||||
#define BF_ANADIG_PFD_528_PFD3_FRAC(v) (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
|
||||
#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
|
||||
#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
|
||||
#define BP_ANADIG_PFD_528_PFD2_FRAC 16
|
||||
#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
|
||||
#define BF_ANADIG_PFD_528_PFD2_FRAC(v) (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
|
||||
#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
|
||||
#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
|
||||
#define BP_ANADIG_PFD_528_PFD1_FRAC 8
|
||||
#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
|
||||
#define BF_ANADIG_PFD_528_PFD1_FRAC(v) (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
|
||||
#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
|
||||
#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
|
||||
#define BP_ANADIG_PFD_528_PFD0_FRAC 0
|
||||
#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
|
||||
#define BF_ANADIG_PFD_528_PFD0_FRAC(v) (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
|
||||
|
||||
#define HW_ANADIG_REG_1P1 (0x00000110)
|
||||
#define HW_ANADIG_REG_1P1_SET (0x00000114)
|
||||
#define HW_ANADIG_REG_1P1_CLR (0x00000118)
|
||||
#define HW_ANADIG_REG_1P1_TOG (0x0000011c)
|
||||
|
||||
#define BM_ANADIG_REG_1P1_OK_VDD1P1 0x00020000
|
||||
#define BM_ANADIG_REG_1P1_BO_VDD1P1 0x00010000
|
||||
#define BP_ANADIG_REG_1P1_OUTPUT_TRG 8
|
||||
#define BM_ANADIG_REG_1P1_OUTPUT_TRG 0x00001F00
|
||||
#define BF_ANADIG_REG_1P1_OUTPUT_TRG(v) (((v) << 8) & BM_ANADIG_REG_1P1_OUTPUT_TRG)
|
||||
#define BP_ANADIG_REG_1P1_BO_OFFSET 4
|
||||
#define BM_ANADIG_REG_1P1_BO_OFFSET 0x00000070
|
||||
#define BF_ANADIG_REG_1P1_BO_OFFSET(v) (((v) << 4) & BM_ANADIG_REG_1P1_BO_OFFSET)
|
||||
#define BM_ANADIG_REG_1P1_ENABLE_PULLDOWN 0x00000008
|
||||
#define BM_ANADIG_REG_1P1_ENABLE_ILIMIT 0x00000004
|
||||
#define BM_ANADIG_REG_1P1_ENABLE_BO 0x00000002
|
||||
#define BM_ANADIG_REG_1P1_ENABLE_LINREG 0x00000001
|
||||
|
||||
#define HW_ANADIG_REG_3P0 (0x00000120)
|
||||
#define HW_ANADIG_REG_3P0_SET (0x00000124)
|
||||
#define HW_ANADIG_REG_3P0_CLR (0x00000128)
|
||||
#define HW_ANADIG_REG_3P0_TOG (0x0000012c)
|
||||
|
||||
#define BM_ANADIG_REG_3P0_OK_VDD3P0 0x00020000
|
||||
#define BM_ANADIG_REG_3P0_BO_VDD3P0 0x00010000
|
||||
#define BP_ANADIG_REG_3P0_OUTPUT_TRG 8
|
||||
#define BM_ANADIG_REG_3P0_OUTPUT_TRG 0x00001F00
|
||||
#define BF_ANADIG_REG_3P0_OUTPUT_TRG(v) (((v) << 8) & BM_ANADIG_REG_3P0_OUTPUT_TRG)
|
||||
#define BM_ANADIG_REG_3P0_VBUS_SEL 0x00000080
|
||||
#define BP_ANADIG_REG_3P0_BO_OFFSET 4
|
||||
#define BM_ANADIG_REG_3P0_BO_OFFSET 0x00000070
|
||||
#define BF_ANADIG_REG_3P0_BO_OFFSET(v) (((v) << 4) & BM_ANADIG_REG_3P0_BO_OFFSET)
|
||||
#define BM_ANADIG_REG_3P0_ENABLE_ILIMIT 0x00000004
|
||||
#define BM_ANADIG_REG_3P0_ENABLE_BO 0x00000002
|
||||
#define BM_ANADIG_REG_3P0_ENABLE_LINREG 0x00000001
|
||||
|
||||
#define HW_ANADIG_REG_2P5 (0x00000130)
|
||||
#define HW_ANADIG_REG_2P5_SET (0x00000134)
|
||||
#define HW_ANADIG_REG_2P5_CLR (0x00000138)
|
||||
#define HW_ANADIG_REG_2P5_TOG (0x0000013c)
|
||||
|
||||
#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x00040000
|
||||
#define BM_ANADIG_REG_2P5_OK_VDD2P5 0x00020000
|
||||
#define BM_ANADIG_REG_2P5_BO_VDD2P5 0x00010000
|
||||
#define BP_ANADIG_REG_2P5_OUTPUT_TRG 8
|
||||
#define BM_ANADIG_REG_2P5_OUTPUT_TRG 0x00001F00
|
||||
#define BF_ANADIG_REG_2P5_OUTPUT_TRG(v) (((v) << 8) & BM_ANADIG_REG_2P5_OUTPUT_TRG)
|
||||
#define BP_ANADIG_REG_2P5_BO_OFFSET 4
|
||||
#define BM_ANADIG_REG_2P5_BO_OFFSET 0x00000070
|
||||
#define BF_ANADIG_REG_2P5_BO_OFFSET(v) (((v) << 4) & BM_ANADIG_REG_2P5_BO_OFFSET)
|
||||
#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x00000008
|
||||
#define BM_ANADIG_REG_2P5_ENABLE_ILIMIT 0x00000004
|
||||
#define BM_ANADIG_REG_2P5_ENABLE_BO 0x00000002
|
||||
#define BM_ANADIG_REG_2P5_ENABLE_LINREG 0x00000001
|
||||
|
||||
#define HW_ANADIG_REG_CORE (0x00000140)
|
||||
#define HW_ANADIG_REG_CORE_SET (0x00000144)
|
||||
#define HW_ANADIG_REG_CORE_CLR (0x00000148)
|
||||
#define HW_ANADIG_REG_CORE_TOG (0x0000014c)
|
||||
|
||||
#define BM_ANADIG_REG_CORE_REF_SHIFT 0x80000000
|
||||
#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
|
||||
#define BP_ANADIG_REG_CORE_RAMP_RATE 27
|
||||
#define BM_ANADIG_REG_CORE_RAMP_RATE 0x18000000
|
||||
#define BF_ANADIG_REG_CORE_RAMP_RATE(v) (((v) << 27) & BM_ANADIG_REG_CORE_RAMP_RATE)
|
||||
#define BP_ANADIG_REG_CORE_REG2_ADJ 23
|
||||
#define BM_ANADIG_REG_CORE_REG2_ADJ 0x07800000
|
||||
#define BF_ANADIG_REG_CORE_REG2_ADJ(v) (((v) << 23) & BM_ANADIG_REG_CORE_REG2_ADJ)
|
||||
#define BP_ANADIG_REG_CORE_REG2_TRG 18
|
||||
#define BM_ANADIG_REG_CORE_REG2_TRG 0x007C0000
|
||||
#define BF_ANADIG_REG_CORE_REG2_TRG(v) (((v) << 18) & BM_ANADIG_REG_CORE_REG2_TRG)
|
||||
#define BP_ANADIG_REG_CORE_REG1_ADJ 14
|
||||
#define BM_ANADIG_REG_CORE_REG1_ADJ 0x0003C000
|
||||
#define BF_ANADIG_REG_CORE_REG1_ADJ(v) (((v) << 14) & BM_ANADIG_REG_CORE_REG1_ADJ)
|
||||
#define BP_ANADIG_REG_CORE_REG1_TRG 9
|
||||
#define BM_ANADIG_REG_CORE_REG1_TRG 0x00003E00
|
||||
#define BF_ANADIG_REG_CORE_REG1_TRG(v) (((v) << 9) & BM_ANADIG_REG_CORE_REG1_TRG)
|
||||
#define BP_ANADIG_REG_CORE_REG0_ADJ 5
|
||||
#define BM_ANADIG_REG_CORE_REG0_ADJ 0x000001E0
|
||||
#define BF_ANADIG_REG_CORE_REG0_ADJ(v) (((v) << 5) & BM_ANADIG_REG_CORE_REG0_ADJ)
|
||||
#define BP_ANADIG_REG_CORE_REG0_TRG 0
|
||||
#define BM_ANADIG_REG_CORE_REG0_TRG 0x0000001F
|
||||
#define BF_ANADIG_REG_CORE_REG0_TRG(v) (((v) << 0) & BM_ANADIG_REG_CORE_REG0_TRG)
|
||||
|
||||
#define HW_ANADIG_ANA_MISC0 (0x00000150)
|
||||
#define HW_ANADIG_ANA_MISC0_SET (0x00000154)
|
||||
#define HW_ANADIG_ANA_MISC0_CLR (0x00000158)
|
||||
#define HW_ANADIG_ANA_MISC0_TOG (0x0000015c)
|
||||
|
||||
#define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY 26
|
||||
#define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY 0x1C000000
|
||||
#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v) (((v) << 26) & BM_ANADIG_ANA_MISC0_CLKGATE_DELAY)
|
||||
#define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL 0x02000000
|
||||
#define BP_ANADIG_ANA_MISC0_ANAMUX 21
|
||||
#define BM_ANADIG_ANA_MISC0_ANAMUX 0x01E00000
|
||||
#define BF_ANADIG_ANA_MISC0_ANAMUX(v) (((v) << 21) & BM_ANADIG_ANA_MISC0_ANAMUX)
|
||||
#define BM_ANADIG_ANA_MISC0_ANAMUX_EN 0x00100000
|
||||
#define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 18
|
||||
#define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 0x000C0000
|
||||
#define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v) (((v) << 18) & BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
|
||||
#define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN 0x00020000
|
||||
#define BM_ANADIG_ANA_MISC0_OSC_XTALOK 0x00010000
|
||||
#define BP_ANADIG_ANA_MISC0_OSC_I 14
|
||||
#define BM_ANADIG_ANA_MISC0_OSC_I 0x0000C000
|
||||
#define BF_ANADIG_ANA_MISC0_OSC_I(v) (((v) << 14) & BM_ANADIG_ANA_MISC0_OSC_I)
|
||||
#define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN 0x00002000
|
||||
#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x00001000
|
||||
#define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 8
|
||||
#define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 0x00000300
|
||||
#define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v) (((v) << 8) & BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
|
||||
#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP 0x00000080
|
||||
#define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ 4
|
||||
#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x00000070
|
||||
#define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v) (((v) << 4) & BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
|
||||
#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
|
||||
#define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER 0x00000004
|
||||
#define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP 0x00000002
|
||||
#define BM_ANADIG_ANA_MISC0_REFTOP_PWD 0x00000001
|
||||
|
||||
#define HW_ANADIG_ANA_MISC1 (0x00000160)
|
||||
#define HW_ANADIG_ANA_MISC1_SET (0x00000164)
|
||||
#define HW_ANADIG_ANA_MISC1_CLR (0x00000168)
|
||||
#define HW_ANADIG_ANA_MISC1_TOG (0x0000016c)
|
||||
|
||||
#define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO 0x80000000
|
||||
#define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO 0x40000000
|
||||
#define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO 0x20000000
|
||||
#define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN 0x00002000
|
||||
#define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN 0x00001000
|
||||
#define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN 0x00000800
|
||||
#define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN 0x00000400
|
||||
#define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 5
|
||||
#define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 0x000003E0
|
||||
#define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v) (((v) << 5) & BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
|
||||
#define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0
|
||||
#define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0x0000001F
|
||||
#define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v) (((v) << 0) & BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
|
||||
|
||||
#define HW_ANADIG_ANA_MISC2 (0x00000170)
|
||||
#define HW_ANADIG_ANA_MISC2_SET (0x00000174)
|
||||
#define HW_ANADIG_ANA_MISC2_CLR (0x00000178)
|
||||
#define HW_ANADIG_ANA_MISC2_TOG (0x0000017c)
|
||||
|
||||
#define BP_ANADIG_ANA_MISC2_CONTROL3 30
|
||||
#define BM_ANADIG_ANA_MISC2_CONTROL3 0xC0000000
|
||||
#define BF_ANADIG_ANA_MISC2_CONTROL3(v) (((v) << 30) & BM_ANADIG_ANA_MISC2_CONTROL3)
|
||||
#define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME 28
|
||||
#define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME 0x30000000
|
||||
#define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v) (((v) << 28) & BM_ANADIG_ANA_MISC2_REG2_STEP_TIME)
|
||||
#define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME 26
|
||||
#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME 0x0C000000
|
||||
#define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v) (((v) << 26) & BM_ANADIG_ANA_MISC2_REG1_STEP_TIME)
|
||||
#define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME 24
|
||||
#define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME 0x03000000
|
||||
#define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v) (((v) << 24) & BM_ANADIG_ANA_MISC2_REG0_STEP_TIME)
|
||||
#define BM_ANADIG_ANA_MISC2_CONTROL2 0x00800000
|
||||
#define BM_ANADIG_ANA_MISC2_REG2_OK 0x00400000
|
||||
#define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO 0x00200000
|
||||
#define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS 0x00080000
|
||||
#define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET 16
|
||||
#define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET 0x00070000
|
||||
#define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v) (((v) << 16) & BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
|
||||
#define BM_ANADIG_ANA_MISC2_CONTROL1 0x00008000
|
||||
#define BM_ANADIG_ANA_MISC2_REG1_OK 0x00004000
|
||||
#define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO 0x00002000
|
||||
#define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS 0x00000800
|
||||
#define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET 8
|
||||
#define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET 0x00000700
|
||||
#define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v) (((v) << 8) & BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET)
|
||||
#define BM_ANADIG_ANA_MISC2_CONTROL0 0x00000080
|
||||
#define BM_ANADIG_ANA_MISC2_REG0_OK 0x00000040
|
||||
#define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO 0x00000020
|
||||
#define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS 0x00000008
|
||||
#define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0
|
||||
#define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0x00000007
|
||||
#define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v) (((v) << 0) & BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
|
||||
|
||||
#define HW_ANADIG_TEMPSENSE0 (0x00000180)
|
||||
#define HW_ANADIG_TEMPSENSE0_SET (0x00000184)
|
||||
#define HW_ANADIG_TEMPSENSE0_CLR (0x00000188)
|
||||
#define HW_ANADIG_TEMPSENSE0_TOG (0x0000018c)
|
||||
|
||||
#define BP_ANADIG_TEMPSENSE0_ALARM_VALUE 20
|
||||
#define BM_ANADIG_TEMPSENSE0_ALARM_VALUE 0xFFF00000
|
||||
#define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) (((v) << 20) & BM_ANADIG_TEMPSENSE0_ALARM_VALUE)
|
||||
#define BP_ANADIG_TEMPSENSE0_TEMP_VALUE 8
|
||||
#define BM_ANADIG_TEMPSENSE0_TEMP_VALUE 0x000FFF00
|
||||
#define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v) (((v) << 8) & BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
|
||||
#define BM_ANADIG_TEMPSENSE0_TEST 0x00000040
|
||||
#define BP_ANADIG_TEMPSENSE0_VBGADJ 3
|
||||
#define BM_ANADIG_TEMPSENSE0_VBGADJ 0x00000038
|
||||
#define BF_ANADIG_TEMPSENSE0_VBGADJ(v) (((v) << 3) & BM_ANADIG_TEMPSENSE0_VBGADJ)
|
||||
#define BM_ANADIG_TEMPSENSE0_FINISHED 0x00000004
|
||||
#define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP 0x00000002
|
||||
#define BM_ANADIG_TEMPSENSE0_POWER_DOWN 0x00000001
|
||||
|
||||
#define HW_ANADIG_TEMPSENSE1 (0x00000190)
|
||||
#define HW_ANADIG_TEMPSENSE1_SET (0x00000194)
|
||||
#define HW_ANADIG_TEMPSENSE1_CLR (0x00000198)
|
||||
#define HW_ANADIG_TEMPSENSE1_TOG (0x0000019c)
|
||||
|
||||
#define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ 0
|
||||
#define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ 0x0000FFFF
|
||||
#define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v) (((v) << 0) & BM_ANADIG_TEMPSENSE1_MEASURE_FREQ)
|
||||
|
||||
#define HW_ANADIG_USB1_VBUS_DETECT (0x000001a0)
|
||||
#define HW_ANADIG_USB1_VBUS_DETECT_SET (0x000001a4)
|
||||
#define HW_ANADIG_USB1_VBUS_DETECT_CLR (0x000001a8)
|
||||
#define HW_ANADIG_USB1_VBUS_DETECT_TOG (0x000001ac)
|
||||
|
||||
#define BM_ANADIG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR 0x80000000
|
||||
#define BM_ANADIG_USB1_VBUS_DETECT_CHARGE_VBUS 0x08000000
|
||||
#define BM_ANADIG_USB1_VBUS_DETECT_DISCHARGE_VBUS 0x04000000
|
||||
#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS 0x00100000
|
||||
#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_5VDETECT 0x00080000
|
||||
#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_TO_B 0x00040000
|
||||
#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE 0x00000080
|
||||
#define BM_ANADIG_USB1_VBUS_DETECT_AVALID_OVERRIDE 0x00000040
|
||||
#define BM_ANADIG_USB1_VBUS_DETECT_BVALID_OVERRIDE 0x00000020
|
||||
#define BM_ANADIG_USB1_VBUS_DETECT_SESSEND_OVERRIDE 0x00000010
|
||||
#define BM_ANADIG_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN 0x00000008
|
||||
#define BP_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH 0
|
||||
#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH 0x00000007
|
||||
#define BF_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH(v) (((v) << 0) & BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH)
|
||||
|
||||
#define HW_ANADIG_USB1_CHRG_DETECT (0x000001b0)
|
||||
#define HW_ANADIG_USB1_CHRG_DETECT_SET (0x000001b4)
|
||||
#define HW_ANADIG_USB1_CHRG_DETECT_CLR (0x000001b8)
|
||||
#define HW_ANADIG_USB1_CHRG_DETECT_TOG (0x000001bc)
|
||||
|
||||
#define BM_ANADIG_USB1_CHRG_DETECT_BGR_BIAS 0x00800000
|
||||
#define BM_ANADIG_USB1_CHRG_DETECT_EN_B 0x00100000
|
||||
#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B 0x00080000
|
||||
#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CONTACT 0x00040000
|
||||
#define BM_ANADIG_USB1_CHRG_DETECT_FORCE_DETECT 0x00000001
|
||||
|
||||
#define HW_ANADIG_USB1_VBUS_DET_STAT (0x000001c0)
|
||||
#define HW_ANADIG_USB1_VBUS_DET_STAT_SET (0x000001c4)
|
||||
#define HW_ANADIG_USB1_VBUS_DET_STAT_CLR (0x000001c8)
|
||||
#define HW_ANADIG_USB1_VBUS_DET_STAT_TOG (0x000001cc)
|
||||
|
||||
#define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID 0x00000008
|
||||
#define BM_ANADIG_USB1_VBUS_DET_STAT_AVALID 0x00000004
|
||||
#define BM_ANADIG_USB1_VBUS_DET_STAT_BVALID 0x00000002
|
||||
#define BM_ANADIG_USB1_VBUS_DET_STAT_SESSEND 0x00000001
|
||||
|
||||
#define HW_ANADIG_USB1_CHRG_DET_STAT (0x000001d0)
|
||||
#define HW_ANADIG_USB1_CHRG_DET_STAT_SET (0x000001d4)
|
||||
#define HW_ANADIG_USB1_CHRG_DET_STAT_CLR (0x000001d8)
|
||||
#define HW_ANADIG_USB1_CHRG_DET_STAT_TOG (0x000001dc)
|
||||
|
||||
#define BM_ANADIG_USB1_CHRG_DET_STAT_DP_STATE 0x00000008
|
||||
#define BM_ANADIG_USB1_CHRG_DET_STAT_DM_STATE 0x00000004
|
||||
#define BM_ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED 0x00000002
|
||||
#define BM_ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT 0x00000001
|
||||
|
||||
#define HW_ANADIG_USB1_LOOPBACK (0x000001e0)
|
||||
#define HW_ANADIG_USB1_LOOPBACK_SET (0x000001e4)
|
||||
#define HW_ANADIG_USB1_LOOPBACK_CLR (0x000001e8)
|
||||
#define HW_ANADIG_USB1_LOOPBACK_TOG (0x000001ec)
|
||||
|
||||
#define BM_ANADIG_USB1_LOOPBACK_UTMO_DIG_TST1 0x00000100
|
||||
#define BM_ANADIG_USB1_LOOPBACK_UTMO_DIG_TST0 0x00000080
|
||||
#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_HIZ 0x00000040
|
||||
#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN 0x00000020
|
||||
#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_LS_MODE 0x00000010
|
||||
#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_HS_MODE 0x00000008
|
||||
#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 0x00000004
|
||||
#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST0 0x00000002
|
||||
#define BM_ANADIG_USB1_LOOPBACK_UTMI_TESTSTART 0x00000001
|
||||
|
||||
#define HW_ANADIG_USB1_MISC (0x000001f0)
|
||||
#define HW_ANADIG_USB1_MISC_SET (0x000001f4)
|
||||
#define HW_ANADIG_USB1_MISC_CLR (0x000001f8)
|
||||
#define HW_ANADIG_USB1_MISC_TOG (0x000001fc)
|
||||
|
||||
#define BM_ANADIG_USB1_MISC_EN_CLK_UTMI 0x40000000
|
||||
#define BM_ANADIG_USB1_MISC_RX_VPIN_FS 0x20000000
|
||||
#define BM_ANADIG_USB1_MISC_RX_VMIN_FS 0x10000000
|
||||
#define BM_ANADIG_USB1_MISC_RX_RXD_FS 0x08000000
|
||||
#define BM_ANADIG_USB1_MISC_RX_SQUELCH 0x04000000
|
||||
#define BM_ANADIG_USB1_MISC_RX_DISCON_DET 0x02000000
|
||||
#define BM_ANADIG_USB1_MISC_RX_HS_DATA 0x01000000
|
||||
#define BM_ANADIG_USB1_MISC_EN_DEGLITCH 0x00000002
|
||||
#define BM_ANADIG_USB1_MISC_HS_USE_EXTERNAL_R 0x00000001
|
||||
|
||||
#define HW_ANADIG_USB2_VBUS_DETECT (0x00000200)
|
||||
#define HW_ANADIG_USB2_VBUS_DETECT_SET (0x00000204)
|
||||
#define HW_ANADIG_USB2_VBUS_DETECT_CLR (0x00000208)
|
||||
#define HW_ANADIG_USB2_VBUS_DETECT_TOG (0x0000020c)
|
||||
|
||||
#define BM_ANADIG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR 0x80000000
|
||||
#define BM_ANADIG_USB2_VBUS_DETECT_CHARGE_VBUS 0x08000000
|
||||
#define BM_ANADIG_USB2_VBUS_DETECT_DISCHARGE_VBUS 0x04000000
|
||||
#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS 0x00100000
|
||||
#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_5VDETECT 0x00080000
|
||||
#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_TO_B 0x00040000
|
||||
#define BP_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH 0
|
||||
#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH 0x00000007
|
||||
#define BF_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH(v) (((v) << 0) & BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH)
|
||||
|
||||
#define HW_ANADIG_USB2_CHRG_DETECT (0x00000210)
|
||||
#define HW_ANADIG_USB2_CHRG_DETECT_SET (0x00000214)
|
||||
#define HW_ANADIG_USB2_CHRG_DETECT_CLR (0x00000218)
|
||||
#define HW_ANADIG_USB2_CHRG_DETECT_TOG (0x0000021c)
|
||||
|
||||
#define BM_ANADIG_USB2_CHRG_DETECT_BGR_BIAS 0x00800000
|
||||
#define BM_ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
|
||||
#define BM_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
|
||||
#define BM_ANADIG_USB2_CHRG_DETECT_CHK_CONTACT 0x00040000
|
||||
#define BM_ANADIG_USB2_CHRG_DETECT_FORCE_DETECT 0x00000001
|
||||
|
||||
#define HW_ANADIG_USB2_VBUS_DET_STAT (0x00000220)
|
||||
#define HW_ANADIG_USB2_VBUS_DET_STAT_SET (0x00000224)
|
||||
#define HW_ANADIG_USB2_VBUS_DET_STAT_CLR (0x00000228)
|
||||
#define HW_ANADIG_USB2_VBUS_DET_STAT_TOG (0x0000022c)
|
||||
|
||||
#define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID 0x00000008
|
||||
#define BM_ANADIG_USB2_VBUS_DET_STAT_AVALID 0x00000004
|
||||
#define BM_ANADIG_USB2_VBUS_DET_STAT_BVALID 0x00000002
|
||||
#define BM_ANADIG_USB2_VBUS_DET_STAT_SESSEND 0x00000001
|
||||
|
||||
#define HW_ANADIG_USB2_CHRG_DET_STAT (0x00000230)
|
||||
#define HW_ANADIG_USB2_CHRG_DET_STAT_SET (0x00000234)
|
||||
#define HW_ANADIG_USB2_CHRG_DET_STAT_CLR (0x00000238)
|
||||
#define HW_ANADIG_USB2_CHRG_DET_STAT_TOG (0x0000023c)
|
||||
|
||||
#define BM_ANADIG_USB2_CHRG_DET_STAT_DP_STATE 0x00000008
|
||||
#define BM_ANADIG_USB2_CHRG_DET_STAT_DM_STATE 0x00000004
|
||||
#define BM_ANADIG_USB2_CHRG_DET_STAT_CHRG_DETECTED 0x00000002
|
||||
#define BM_ANADIG_USB2_CHRG_DET_STAT_PLUG_CONTACT 0x00000001
|
||||
|
||||
#define HW_ANADIG_USB2_LOOPBACK (0x00000240)
|
||||
#define HW_ANADIG_USB2_LOOPBACK_SET (0x00000244)
|
||||
#define HW_ANADIG_USB2_LOOPBACK_CLR (0x00000248)
|
||||
#define HW_ANADIG_USB2_LOOPBACK_TOG (0x0000024c)
|
||||
|
||||
#define BM_ANADIG_USB2_LOOPBACK_UTMO_DIG_TST1 0x00000100
|
||||
#define BM_ANADIG_USB2_LOOPBACK_UTMO_DIG_TST0 0x00000080
|
||||
#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_HIZ 0x00000040
|
||||
#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN 0x00000020
|
||||
#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_LS_MODE 0x00000010
|
||||
#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_HS_MODE 0x00000008
|
||||
#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 0x00000004
|
||||
#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST0 0x00000002
|
||||
#define BM_ANADIG_USB2_LOOPBACK_UTMI_TESTSTART 0x00000001
|
||||
|
||||
#define HW_ANADIG_USB2_MISC (0x00000250)
|
||||
#define HW_ANADIG_USB2_MISC_SET (0x00000254)
|
||||
#define HW_ANADIG_USB2_MISC_CLR (0x00000258)
|
||||
#define HW_ANADIG_USB2_MISC_TOG (0x0000025c)
|
||||
|
||||
#define BM_ANADIG_USB2_MISC_EN_CLK_UTMI 0x40000000
|
||||
#define BM_ANADIG_USB2_MISC_RX_VPIN_FS 0x20000000
|
||||
#define BM_ANADIG_USB2_MISC_RX_VMIN_FS 0x10000000
|
||||
#define BM_ANADIG_USB2_MISC_RX_RXD_FS 0x08000000
|
||||
#define BM_ANADIG_USB2_MISC_RX_SQUELCH 0x04000000
|
||||
#define BM_ANADIG_USB2_MISC_RX_DISCON_DET 0x02000000
|
||||
#define BM_ANADIG_USB2_MISC_RX_HS_DATA 0x01000000
|
||||
#define BM_ANADIG_USB2_MISC_EN_DEGLITCH 0x00000002
|
||||
#define BM_ANADIG_USB2_MISC_HS_USE_EXTERNAL_R 0x00000001
|
||||
|
||||
#define HW_ANADIG_DIGPROG (0x00000260)
|
||||
|
||||
#define BP_ANADIG_DIGPROG_MAJOR 8
|
||||
#define BM_ANADIG_DIGPROG_MAJOR 0x00FFFF00
|
||||
#define BF_ANADIG_DIGPROG_MAJOR(v) (((v) << 8) & BM_ANADIG_DIGPROG_MAJOR)
|
||||
#define BP_ANADIG_DIGPROG_MINOR 0
|
||||
#define BM_ANADIG_DIGPROG_MINOR 0x000000FF
|
||||
#define BF_ANADIG_DIGPROG_MINOR(v) (((v) << 0) & BM_ANADIG_DIGPROG_MINOR)
|
||||
#endif /* __ARCH_ARM___ANADIG_H */
|
|
@ -0,0 +1,132 @@
|
|||
#ifndef __MACH_IMX6_REGS_H
|
||||
#define __MACH_IMX6_REGS_H
|
||||
|
||||
#define IMX_TIM1_BASE 0x02098000
|
||||
#define IMX_WDT_BASE 0x020bc000
|
||||
#define IMX_IOMUXC_BASE 0x020e0000
|
||||
|
||||
#define GPT_TCTL 0x00
|
||||
#define GPT_TPRER 0x04
|
||||
#define GPT_TCMP 0x10
|
||||
#define GPT_TCR 0x1c
|
||||
#define GPT_TCN 0x24
|
||||
#define GPT_TSTAT 0x08
|
||||
|
||||
/* Part 2: Bitfields */
|
||||
#define TCTL_SWR (1<<15) /* Software reset */
|
||||
#define TCTL_FRR (1<<9) /* Freerun / restart */
|
||||
#define TCTL_CAP (3<<6) /* Capture Edge */
|
||||
#define TCTL_OM (1<<5) /* output mode */
|
||||
#define TCTL_IRQEN (1<<4) /* interrupt enable */
|
||||
#define TCTL_CLKSOURCE (6) /* Clock source bit position */
|
||||
#define TCTL_TEN (1) /* Timer enable */
|
||||
#define TPRER_PRES (0xff) /* Prescale */
|
||||
#define TSTAT_CAPT (1<<1) /* Capture event */
|
||||
#define TSTAT_COMP (1) /* Compare event */
|
||||
|
||||
#define MX6_AIPS1_ARB_BASE_ADDR 0x02000000
|
||||
#define MX6_AIPS2_ARB_BASE_ADDR 0x02100000
|
||||
|
||||
/* Defines for Blocks connected via AIPS (SkyBlue) */
|
||||
#define MX6_ATZ1_BASE_ADDR MX6_AIPS1_ARB_BASE_ADDR
|
||||
#define MX6_ATZ2_BASE_ADDR MX6_AIPS2_ARB_BASE_ADDR
|
||||
|
||||
#define IPU_CTRL_BASE_ADDR 0x02400000
|
||||
|
||||
/* slots 0,7 of SDMA reserved, therefore left unused in IPMUX3 */
|
||||
#define MX6_SPDIF_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x04000)
|
||||
#define MX6_ECSPI1_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x08000)
|
||||
#define MX6_ECSPI2_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x0C000)
|
||||
#define MX6_ECSPI3_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x10000)
|
||||
#define MX6_ECSPI4_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x14000)
|
||||
#define MX6_ECSPI5_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x18000)
|
||||
#define MX6_UART1_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x20000)
|
||||
#define MX6_ESAI1_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x24000)
|
||||
#define MX6_SSI1_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x28000)
|
||||
#define MX6_SSI2_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x2C000)
|
||||
#define MX6_SSI3_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x30000)
|
||||
#define MX6_ASRC_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x34000)
|
||||
#define MX6_SPBA_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x3C000)
|
||||
#define MX6_VPU_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x40000)
|
||||
|
||||
/* ATZ#1- On Platform */
|
||||
#define MX6_AIPS1_ON_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x7C000)
|
||||
|
||||
/* ATZ#1- Off Platform */
|
||||
#define MX6_AIPS1_OFF_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x80000)
|
||||
|
||||
#define MX6_PWM1_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x0000)
|
||||
#define MX6_PWM2_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x4000)
|
||||
#define MX6_PWM3_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x8000)
|
||||
#define MX6_PWM4_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0xC000)
|
||||
#define MX6_CAN1_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x10000)
|
||||
#define MX6_CAN2_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x14000)
|
||||
#define MX6_GPT_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x18000)
|
||||
#define MX6_GPIO1_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x1C000)
|
||||
#define MX6_GPIO2_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x20000)
|
||||
#define MX6_GPIO3_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x24000)
|
||||
#define MX6_GPIO4_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x28000)
|
||||
#define MX6_GPIO5_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x2C000)
|
||||
#define MX6_GPIO6_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x30000)
|
||||
#define MX6_GPIO7_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x34000)
|
||||
#define MX6_KPP_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x38000)
|
||||
#define MX6_WDOG1_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x3C000)
|
||||
#define MX6_WDOG2_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x40000)
|
||||
#define MX6_CCM_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x44000)
|
||||
#define MX6_ANATOP_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x48000)
|
||||
#define MX6_SNVS_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x4C000)
|
||||
#define MX6_EPIT1_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x50000)
|
||||
#define MX6_EPIT2_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x54000)
|
||||
#define MX6_SRC_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x58000)
|
||||
#define MX6_GPC_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x5C000)
|
||||
#define MX6_IOMUXC_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x60000)
|
||||
#define MX6_DCIC1_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x64000)
|
||||
#define MX6_DCIC2_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x68000)
|
||||
#define MX6_DMA_REQ_PORT_HOST_BASE_ADDR (MX6_AIPS1_OFF_BASE_ADDR + 0x6C000)
|
||||
|
||||
/* ATZ#2- On Platform */
|
||||
#define MX6_AIPS2_ON_BASE_ADDR (MX6_ATZ2_BASE_ADDR + 0x7C000)
|
||||
|
||||
/* ATZ#2- Off Platform */
|
||||
#define MX6_AIPS2_OFF_BASE_ADDR (MX6_ATZ2_BASE_ADDR + 0x80000)
|
||||
|
||||
/* ATZ#2 - Global enable (0) */
|
||||
#define MX6_CAAM_BASE_ADDR (MX6_ATZ2_BASE_ADDR)
|
||||
#define MX6_ARM_BASE_ADDR (MX6_ATZ2_BASE_ADDR + 0x40000)
|
||||
|
||||
#define MX6_USBOH3_PL301_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x0000)
|
||||
#define MX6_USBOH3_USB_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x4000)
|
||||
#define MX6_OTG_BASE_ADDR MX6_USBOH3_USB_BASE_ADDR
|
||||
#define MX6_ENET_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x8000)
|
||||
#define MX6_MLB_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0xC000)
|
||||
|
||||
#define MX6_USDHC1_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x10000)
|
||||
#define MX6_USDHC2_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x14000)
|
||||
#define MX6_USDHC3_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x18000)
|
||||
#define MX6_USDHC4_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x1C000)
|
||||
#define MX6_I2C1_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x20000)
|
||||
#define MX6_I2C2_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x24000)
|
||||
#define MX6_I2C3_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x28000)
|
||||
#define MX6_ROMCP_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x2C000)
|
||||
#define MX6_MMDC_P0_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x30000)
|
||||
#define MX6_MMDC_P1_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x34000)
|
||||
#define MX6_WEIM_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x38000)
|
||||
#define MX6_OCOTP_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x3C000)
|
||||
#define MX6_CSU_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x40000)
|
||||
#define MX6_IP2APB_PERFMON1_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x44000)
|
||||
#define MX6_IP2APB_PERFMON2_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x48000)
|
||||
#define MX6_IP2APB_PERFMON3_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x4C000)
|
||||
#define MX6_IP2APB_TZASC1_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x50000)
|
||||
#define MX6_IP2APB_TZASC2_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x54000)
|
||||
#define MX6_AUDMUX_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x58000)
|
||||
#define MX6_MIPI_CSI2_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x5C000)
|
||||
#define MX6_MIPI_DSI_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x60000)
|
||||
#define MX6_VDOA_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x64000)
|
||||
#define MX6_UART2_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x68000)
|
||||
#define MX6_UART3_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x6C000)
|
||||
#define MX6_UART4_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x70000)
|
||||
#define MX6_UART5_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x74000)
|
||||
#define MX6_IP2APB_USBPHY1_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x78000)
|
||||
#define MX6_IP2APB_USBPHY2_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x7C000)
|
||||
|
||||
#endif /* __MACH_IMX6_REGS_H */
|
|
@ -0,0 +1,6 @@
|
|||
#ifndef __MACH_IMX6_H
|
||||
#define __MACH_IMX6_H
|
||||
|
||||
void imx6_init_lowlevel(void);
|
||||
|
||||
#endif /* __MACH_IMX6_H */
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,393 @@
|
|||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm-generic/div64.h>
|
||||
#include <mach/imx-regs.h>
|
||||
#include <mach/clock-imx6.h>
|
||||
#include <mach/imx6-anadig.h>
|
||||
|
||||
enum pll_clocks {
|
||||
CPU_PLL1, /* System PLL */
|
||||
BUS_PLL2, /* System Bus PLL*/
|
||||
USBOTG_PLL3, /* OTG USB PLL */
|
||||
AUD_PLL4, /* Audio PLL */
|
||||
VID_PLL5, /* Video PLL */
|
||||
MLB_PLL6, /* MLB PLL */
|
||||
USBHOST_PLL7, /* Host USB PLL */
|
||||
ENET_PLL8, /* ENET PLL */
|
||||
};
|
||||
|
||||
#define SZ_DEC_1M 1000000
|
||||
|
||||
/* Out-of-reset PFDs and clock source definitions */
|
||||
#define PLL2_PFD0_FREQ 352000000
|
||||
#define PLL2_PFD1_FREQ 594000000
|
||||
#define PLL2_PFD2_FREQ 400000000
|
||||
#define PLL2_PFD2_DIV_FREQ 200000000
|
||||
#define PLL3_PFD0_FREQ 720000000
|
||||
#define PLL3_PFD1_FREQ 540000000
|
||||
#define PLL3_PFD2_FREQ 508200000
|
||||
#define PLL3_PFD3_FREQ 454700000
|
||||
#define PLL3_80M 80000000
|
||||
#define PLL3_60M 60000000
|
||||
|
||||
#define AHB_CLK_ROOT 132000000
|
||||
#define IPG_CLK_ROOT 66000000
|
||||
#define ENET_FREQ_0 25000000
|
||||
#define ENET_FREQ_1 50000000
|
||||
#define ENET_FREQ_2 100000000
|
||||
#define ENET_FREQ_3 125000000
|
||||
|
||||
#define CONFIG_MX6_HCLK_FREQ 24000000
|
||||
|
||||
static u32 __decode_pll(enum pll_clocks pll, u32 infreq)
|
||||
{
|
||||
u32 div;
|
||||
|
||||
switch (pll) {
|
||||
case CPU_PLL1:
|
||||
div = readl(MX6_ANATOP_BASE_ADDR + HW_ANADIG_PLL_SYS) &
|
||||
BM_ANADIG_PLL_SYS_DIV_SELECT;
|
||||
return infreq * (div >> 1);
|
||||
case BUS_PLL2:
|
||||
div = readl(MX6_ANATOP_BASE_ADDR + HW_ANADIG_PLL_528) &
|
||||
BM_ANADIG_PLL_528_DIV_SELECT;
|
||||
return infreq * (20 + (div << 1));
|
||||
case USBOTG_PLL3:
|
||||
div = readl(MX6_ANATOP_BASE_ADDR + HW_ANADIG_USB2_PLL_480_CTRL) &
|
||||
BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT;
|
||||
return infreq * (20 + (div << 1));
|
||||
case ENET_PLL8:
|
||||
div = readl(MX6_ANATOP_BASE_ADDR + HW_ANADIG_PLL_ENET) &
|
||||
BM_ANADIG_PLL_ENET_DIV_SELECT;
|
||||
switch (div) {
|
||||
default:
|
||||
case 0:
|
||||
return ENET_FREQ_0;
|
||||
case 1:
|
||||
return ENET_FREQ_1;
|
||||
case 2:
|
||||
return ENET_FREQ_2;
|
||||
case 3:
|
||||
return ENET_FREQ_3;
|
||||
}
|
||||
case AUD_PLL4:
|
||||
case VID_PLL5:
|
||||
case MLB_PLL6:
|
||||
case USBHOST_PLL7:
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static u32 __get_mcu_main_clk(void)
|
||||
{
|
||||
u32 reg, freq;
|
||||
reg = (__REG(MXC_CCM_CACRR) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
|
||||
MXC_CCM_CACRR_ARM_PODF_OFFSET;
|
||||
freq = __decode_pll(CPU_PLL1, CONFIG_MX6_HCLK_FREQ);
|
||||
return freq / (reg + 1);
|
||||
}
|
||||
|
||||
static u32 __get_periph_clk(void)
|
||||
{
|
||||
u32 reg;
|
||||
reg = __REG(MXC_CCM_CBCDR);
|
||||
if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
|
||||
reg = __REG(MXC_CCM_CBCMR);
|
||||
switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK) >>
|
||||
MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET) {
|
||||
case 0:
|
||||
return __decode_pll(USBOTG_PLL3, CONFIG_MX6_HCLK_FREQ);
|
||||
case 1:
|
||||
case 2:
|
||||
return CONFIG_MX6_HCLK_FREQ;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
} else {
|
||||
reg = __REG(MXC_CCM_CBCMR);
|
||||
switch ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) >>
|
||||
MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET) {
|
||||
default:
|
||||
case 0:
|
||||
return __decode_pll(BUS_PLL2, CONFIG_MX6_HCLK_FREQ);
|
||||
case 1:
|
||||
return PLL2_PFD2_FREQ;
|
||||
case 2:
|
||||
return PLL2_PFD0_FREQ;
|
||||
case 3:
|
||||
return PLL2_PFD2_DIV_FREQ;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static u32 __get_ipg_clk(void)
|
||||
{
|
||||
u32 ahb_podf, ipg_podf;
|
||||
|
||||
ahb_podf = __REG(MXC_CCM_CBCDR);
|
||||
ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
|
||||
MXC_CCM_CBCDR_IPG_PODF_OFFSET;
|
||||
ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
|
||||
MXC_CCM_CBCDR_AHB_PODF_OFFSET;
|
||||
return __get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
|
||||
}
|
||||
|
||||
u32 imx_get_gptclk(void)
|
||||
{
|
||||
return __get_ipg_clk();
|
||||
}
|
||||
|
||||
static u32 __get_ipg_per_clk(void)
|
||||
{
|
||||
u32 podf;
|
||||
u32 clk_root = __get_ipg_clk();
|
||||
|
||||
podf = __REG(MXC_CCM_CSCMR1) & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
|
||||
return clk_root / (podf + 1);
|
||||
}
|
||||
|
||||
u32 imx_get_uartclk(void)
|
||||
{
|
||||
u32 freq = PLL3_80M, reg, podf;
|
||||
|
||||
reg = __REG(MXC_CCM_CSCDR1);
|
||||
podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
|
||||
MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
|
||||
freq /= (podf + 1);
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
static u32 __get_cspi_clk(void)
|
||||
{
|
||||
u32 freq = PLL3_60M, reg, podf;
|
||||
|
||||
reg = __REG(MXC_CCM_CSCDR2);
|
||||
podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
|
||||
MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
|
||||
freq /= (podf + 1);
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
static u32 __get_axi_clk(void)
|
||||
{
|
||||
u32 clkroot;
|
||||
u32 cbcdr = __REG(MXC_CCM_CBCDR);
|
||||
u32 podf = (cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK) >>
|
||||
MXC_CCM_CBCDR_AXI_PODF_OFFSET;
|
||||
|
||||
if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
|
||||
if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
|
||||
clkroot = PLL2_PFD2_FREQ;
|
||||
else
|
||||
clkroot = PLL3_PFD1_FREQ;;
|
||||
} else
|
||||
clkroot = __get_periph_clk();
|
||||
|
||||
return clkroot / (podf + 1);
|
||||
}
|
||||
|
||||
static u32 __get_ahb_clk(void)
|
||||
{
|
||||
u32 cbcdr = __REG(MXC_CCM_CBCDR);
|
||||
u32 podf = (cbcdr & MXC_CCM_CBCDR_AHB_PODF_MASK) \
|
||||
>> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
|
||||
|
||||
return __get_periph_clk() / (podf + 1);
|
||||
}
|
||||
|
||||
static u32 __get_emi_slow_clk(void)
|
||||
{
|
||||
u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
|
||||
u32 emi_clk_sel = (cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK) >>
|
||||
MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
|
||||
u32 podf = (cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK) >>
|
||||
MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
|
||||
|
||||
switch (emi_clk_sel) {
|
||||
default:
|
||||
case 0:
|
||||
return __get_axi_clk() / (podf + 1);
|
||||
case 1:
|
||||
return __decode_pll(USBOTG_PLL3, CONFIG_MX6_HCLK_FREQ) /
|
||||
(podf + 1);
|
||||
case 2:
|
||||
return PLL2_PFD2_FREQ / (podf + 1);
|
||||
case 3:
|
||||
return PLL2_PFD0_FREQ / (podf + 1);
|
||||
}
|
||||
}
|
||||
|
||||
static u32 __get_nfc_clk(void)
|
||||
{
|
||||
u32 clkroot;
|
||||
u32 cs2cdr = __REG(MXC_CCM_CS2CDR);
|
||||
u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) \
|
||||
>> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
|
||||
u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) \
|
||||
>> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
|
||||
|
||||
switch ((cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
|
||||
MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET) {
|
||||
default:
|
||||
case 0:
|
||||
clkroot = PLL2_PFD0_FREQ;
|
||||
break;
|
||||
case 1:
|
||||
clkroot = __decode_pll(BUS_PLL2, CONFIG_MX6_HCLK_FREQ);
|
||||
break;
|
||||
case 2:
|
||||
clkroot = __decode_pll(USBOTG_PLL3, CONFIG_MX6_HCLK_FREQ);
|
||||
break;
|
||||
case 3:
|
||||
clkroot = PLL2_PFD2_FREQ;
|
||||
break;
|
||||
}
|
||||
|
||||
return clkroot / (pred+1) / (podf+1);
|
||||
}
|
||||
|
||||
static u32 __get_ddr_clk(void)
|
||||
{
|
||||
u32 cbcdr = __REG(MXC_CCM_CBCDR);
|
||||
u32 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
|
||||
MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
|
||||
|
||||
return __get_periph_clk() / (podf + 1);
|
||||
}
|
||||
|
||||
static u32 __get_usdhc1_clk(void)
|
||||
{
|
||||
u32 clkroot;
|
||||
u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
|
||||
u32 cscdr1 = __REG(MXC_CCM_CSCDR1);
|
||||
u32 podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
|
||||
MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
|
||||
|
||||
if (cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL)
|
||||
clkroot = PLL2_PFD0_FREQ;
|
||||
else
|
||||
clkroot = PLL2_PFD2_FREQ;
|
||||
|
||||
return clkroot / (podf + 1);
|
||||
}
|
||||
|
||||
static u32 __get_usdhc2_clk(void)
|
||||
{
|
||||
u32 clkroot;
|
||||
u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
|
||||
u32 cscdr1 = __REG(MXC_CCM_CSCDR1);
|
||||
u32 podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
|
||||
MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
|
||||
|
||||
if (cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL)
|
||||
clkroot = PLL2_PFD0_FREQ;
|
||||
else
|
||||
clkroot = PLL2_PFD2_FREQ;
|
||||
|
||||
return clkroot / (podf + 1);
|
||||
}
|
||||
|
||||
static u32 __get_usdhc3_clk(void)
|
||||
{
|
||||
u32 clkroot;
|
||||
u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
|
||||
u32 cscdr1 = __REG(MXC_CCM_CSCDR1);
|
||||
u32 podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
|
||||
MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
|
||||
|
||||
if (cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL)
|
||||
clkroot = PLL2_PFD0_FREQ;
|
||||
else
|
||||
clkroot = PLL2_PFD2_FREQ;
|
||||
|
||||
return clkroot / (podf + 1);
|
||||
}
|
||||
|
||||
static u32 __get_usdhc4_clk(void)
|
||||
{
|
||||
u32 clkroot;
|
||||
u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
|
||||
u32 cscdr1 = __REG(MXC_CCM_CSCDR1);
|
||||
u32 podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
|
||||
MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
|
||||
|
||||
if (cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL)
|
||||
clkroot = PLL2_PFD0_FREQ;
|
||||
else
|
||||
clkroot = PLL2_PFD2_FREQ;
|
||||
|
||||
return clkroot / (podf + 1);
|
||||
}
|
||||
|
||||
u32 imx_get_mmcclk(void)
|
||||
{
|
||||
return __get_usdhc3_clk();
|
||||
}
|
||||
|
||||
u32 imx_get_fecclk(void)
|
||||
{
|
||||
return __get_ipg_clk();
|
||||
}
|
||||
|
||||
void imx_dump_clocks(void)
|
||||
{
|
||||
u32 freq;
|
||||
|
||||
freq = __decode_pll(CPU_PLL1, CONFIG_MX6_HCLK_FREQ);
|
||||
printf("mx6q pll1: %d\n", freq);
|
||||
freq = __decode_pll(BUS_PLL2, CONFIG_MX6_HCLK_FREQ);
|
||||
printf("mx6q pll2: %d\n", freq);
|
||||
freq = __decode_pll(USBOTG_PLL3, CONFIG_MX6_HCLK_FREQ);
|
||||
printf("mx6q pll3: %d\n", freq);
|
||||
freq = __decode_pll(ENET_PLL8, CONFIG_MX6_HCLK_FREQ);
|
||||
printf("mx6q pll8: %d\n", freq);
|
||||
printf("mcu main: %d\n", __get_mcu_main_clk());
|
||||
printf("periph: %d\n", __get_periph_clk());
|
||||
printf("ipg: %d\n", __get_ipg_clk());
|
||||
printf("ipg per: %d\n", __get_ipg_per_clk());
|
||||
printf("cspi: %d\n", __get_cspi_clk());
|
||||
printf("axi: %d\n", __get_axi_clk());
|
||||
printf("ahb: %d\n", __get_ahb_clk());
|
||||
printf("emi slow: %d\n", __get_emi_slow_clk());
|
||||
printf("nfc: %d\n", __get_nfc_clk());
|
||||
printf("ddr: %d\n", __get_ddr_clk());
|
||||
printf("usdhc1: %d\n", __get_usdhc1_clk());
|
||||
printf("usdhc2: %d\n", __get_usdhc2_clk());
|
||||
printf("usdhc3: %d\n", __get_usdhc3_clk());
|
||||
printf("usdhc4: %d\n", __get_usdhc4_clk());
|
||||
}
|
||||
|
||||
void imx6_ipu_clk_enable(int di)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
if (di == 1) {
|
||||
reg = readl(MXC_CCM_CCGR3);
|
||||
reg |= 0xC033;
|
||||
writel(reg, MXC_CCM_CCGR3);
|
||||
} else {
|
||||
reg = readl(MXC_CCM_CCGR3);
|
||||
reg |= 0x300F;
|
||||
writel(reg, MXC_CCM_CCGR3);
|
||||
}
|
||||
|
||||
reg = readl(MX6_ANATOP_BASE_ADDR + 0xF0);
|
||||
reg &= ~0x00003F00;
|
||||
reg |= 0x00001300;
|
||||
writel(reg, MX6_ANATOP_BASE_ADDR + 0xF4);
|
||||
|
||||
reg = readl(MXC_CCM_CS2CDR);
|
||||
reg &= ~0x00007E00;
|
||||
reg |= 0x00001200;
|
||||
writel(reg, MXC_CCM_CS2CDR);
|
||||
|
||||
reg = readl(MXC_CCM_CSCMR2);
|
||||
reg |= 0x00000C00;
|
||||
writel(reg, MXC_CCM_CSCMR2);
|
||||
|
||||
reg = 0x0002A953;
|
||||
writel(reg, MXC_CCM_CHSCDR);
|
||||
}
|
|
@ -54,7 +54,7 @@ config MCI_IMX
|
|||
|
||||
config MCI_IMX_ESDHC
|
||||
bool "i.MX esdhc"
|
||||
depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51 || ARCH_IMX53
|
||||
depends on ARCH_IMX
|
||||
help
|
||||
Enable this entry to add support to read and write SD cards on a
|
||||
Freescale i.MX25/35/51 based system.
|
||||
|
|
|
@ -1,5 +1,10 @@
|
|||
|
||||
#if defined CONFIG_ARCH_IMX25 || defined CONFIG_ARCH_IMX35 || defined CONFIG_ARCH_IMX51 || defined CONFIG_ARCH_IMX53 || defined CONFIG_X86
|
||||
#if defined CONFIG_ARCH_IMX25 || \
|
||||
defined CONFIG_ARCH_IMX35 || \
|
||||
defined CONFIG_ARCH_IMX51 || \
|
||||
defined CONFIG_ARCH_IMX53 || \
|
||||
defined CONFIG_ARCH_IMX6 || \
|
||||
defined CONFIG_X86
|
||||
#include <mach/barebox.lds.h>
|
||||
#endif
|
||||
|
||||
|
|
Loading…
Reference in New Issue