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mini2440: Add PLL settings 

This is required in order to enable booting from NAND and using the generic
S3C2440 setup routines.

Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Juergen Beisert 2011-02-16 19:13:35 +01:00 committed by Sascha Hauer
parent fb14c8683c
commit 2fbca613d1
1 changed files with 22 additions and 0 deletions
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22
arch/arm/boards/mini2440/config.h
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@ -26,6 +26,28 @@
*/
#define S3C24XX_CLOCK_REFERENCE 12000000
/**
* Define the main clock configuration to be used in register CLKDIVN
*
* We must limit the frequency of the connected SDRAMs with the clock ratio
* setup to 1:4:8. This will result into FCLK:HCLK:PCLK = 405Mhz:102MHz:51MHz
*/
#define BOARD_SPECIFIC_CLKDIVN 0x05
/**
* Define the MPLL configuration to be used in register MPLLCON
*
* We want the MPLL to run at 405.0 MHz
*/
#define BOARD_SPECIFIC_MPLL ((0x7f << 12) + (2 << 4) + 1)
/**
* Define the UPLL configuration to be used in register UPLLCON
*
* We want the UPLL to run at 48.0 MHz
*/
#define BOARD_SPECIFIC_UPLL ((0x38 << 12) + (2 << 4) + 2)
/*
* Flash access timings
* Tacls = 0ns (but 20ns data setup time)