ARM: rework MMU support
In barebox we used 1MiB sections to map our SDRAM cachable. This has the drawback that we have to map our sdram twice: cached for normal sdram and uncached for DMA operations. As address space gets sparse on newer systems we are sometines unable to find a suitably big enough area for the dma coherent space. This patch changes the MMU code to use second level page tables. With it we can implement dma_alloc_coherent as normal malloc, we just have to remap the allocated area uncached afterwards and map it cached again after free(). This makes arm_create_section(), setup_dma_coherent() and mmu_enable() noops. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
f9f35ee938
commit
3100ea1466
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@ -1,10 +1,13 @@
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#include <common.h>
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#include <init.h>
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#include <asm/mmu.h>
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#include <errno.h>
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#include <sizes.h>
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#include <asm/memory.h>
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static unsigned long *ttb;
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void arm_create_section(unsigned long virt, unsigned long phys, int size_m,
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static void create_section(unsigned long virt, unsigned long phys, int size_m,
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unsigned int flags)
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{
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int i;
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@ -23,6 +26,33 @@ void arm_create_section(unsigned long virt, unsigned long phys, int size_m,
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);
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}
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/*
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* Do it the simple way for now and invalidate the entire
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* tlb
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*/
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static inline void tlb_invalidate(void)
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{
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asm volatile (
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"mov r0, #0\n"
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"mcr p15, 0, r0, c7, c10, 4; @ drain write buffer\n"
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"mcr p15, 0, r0, c8, c6, 0; @ invalidate D TLBs\n"
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"mcr p15, 0, r0, c8, c5, 0; @ invalidate I TLBs\n"
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:
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:
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: "r0"
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);
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}
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#ifdef CONFIG_CPU_V7
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#define PTE_FLAGS_CACHED (PTE_EXT_TEX(1) | PTE_BUFFERABLE | PTE_CACHEABLE)
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#define PTE_FLAGS_UNCACHED (0)
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#else
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#define PTE_FLAGS_CACHED (PTE_SMALL_AP_UNO_SRW | PTE_BUFFERABLE | PTE_CACHEABLE)
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#define PTE_FLAGS_UNCACHED PTE_SMALL_AP_UNO_SRW
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#endif
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#define PTE_MASK ((1 << 12) - 1)
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/*
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* Create a second level translation table for the given virtual address.
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* We initially create a flat uncached mapping on it.
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@ -38,11 +68,89 @@ static u32 *arm_create_pte(unsigned long virt)
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ttb[virt] = (unsigned long)table | PMD_TYPE_TABLE;
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for (i = 0; i < 256; i++)
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table[i] = virt | PTE_TYPE_SMALL | PTE_SMALL_AP_UNO_SRW;
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table[i] = virt | PTE_TYPE_SMALL | PTE_FLAGS_UNCACHED;
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return table;
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}
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static void remap_range(void *_start, size_t size, uint32_t flags)
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{
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u32 pteentry;
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struct arm_memory *mem;
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unsigned long start = (unsigned long)_start;
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u32 *p;
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int numentries, i;
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for_each_sdram_bank(mem) {
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if (start >= mem->start && start < mem->start + mem->size)
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goto found;
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}
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BUG();
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return;
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found:
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pteentry = (start - mem->start) >> PAGE_SHIFT;
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numentries = size >> PAGE_SHIFT;
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p = mem->ptes + pteentry;
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for (i = 0; i < numentries; i++) {
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p[i] &= ~PTE_MASK;
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p[i] |= flags | PTE_TYPE_SMALL;
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}
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dma_flush_range((unsigned long)p,
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(unsigned long)p + numentries * sizeof(u32));
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tlb_invalidate();
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}
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/*
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* remap the memory bank described by mem cachable and
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* bufferable
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*/
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static int arm_mmu_remap_sdram(struct arm_memory *mem)
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{
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unsigned long phys = (unsigned long)mem->start;
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unsigned long ttb_start = phys >> 20;
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unsigned long ttb_end = (phys + mem->size) >> 20;
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unsigned long num_ptes = mem->size >> 10;
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int i, pte;
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debug("remapping SDRAM from 0x%08lx (size 0x%08lx)\n",
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phys, mem->size);
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/*
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* We replace each 1MiB section in this range with second level page
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* tables, therefore we must have 1Mib aligment here.
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*/
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if ((phys & (SZ_1M - 1)) || (mem->size & (SZ_1M - 1)))
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return -EINVAL;
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mem->ptes = memalign(0x400, num_ptes * sizeof(u32));
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debug("ptes: 0x%p ttb_start: 0x%08lx ttb_end: 0x%08lx\n",
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mem->ptes, ttb_start, ttb_end);
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for (i = 0; i < num_ptes; i++) {
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mem->ptes[i] = (phys + i * 4096) | PTE_TYPE_SMALL |
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PTE_FLAGS_CACHED;
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}
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pte = 0;
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for (i = ttb_start; i < ttb_end; i++) {
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ttb[i] = (unsigned long)(&mem->ptes[pte]) | PMD_TYPE_TABLE |
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(0 << 4);
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pte += 256;
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}
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tlb_invalidate();
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return 0;
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}
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/*
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* We have 8 exception vectors and the table consists of absolute
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* jumps, so we need 8 * 4 bytes for the instructions and another
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@ -66,19 +174,21 @@ static void vectors_init(void)
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memset(vectors, 0, PAGE_SIZE);
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memcpy(vectors, &exception_vectors, ARM_VECTORS_SIZE);
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exc[0] = (u32)vectors | PTE_TYPE_SMALL | PTE_SMALL_AP_UNO_SRW;
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exc[0] = (u32)vectors | PTE_TYPE_SMALL | PTE_FLAGS_CACHED;
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}
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/*
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* Prepare MMU for usage and create a flat mapping. Board
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* code is responsible to remap the SDRAM cached
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* Prepare MMU for usage enable it.
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*/
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void mmu_init(void)
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int mmu_init(void)
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{
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struct arm_memory *mem;
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int i;
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ttb = memalign(0x10000, 0x4000);
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debug("ttb: 0x%p\n", ttb);
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/* Set the ttb register */
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asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb) /*:*/);
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@ -86,23 +196,36 @@ void mmu_init(void)
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i = 0x3;
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asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
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/* create a flat mapping */
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arm_create_section(0, 0, 4096, PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT);
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/* create a flat mapping using 1MiB sections */
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create_section(0, 0, 4096, PMD_SECT_AP_WRITE | PMD_SECT_AP_READ |
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PMD_TYPE_SECT);
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vectors_init();
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}
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/*
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* enable the MMU. Should be called after mmu_init()
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*/
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void mmu_enable(void)
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{
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/*
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* First remap sdram cached using sections.
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* This is to speed up the generation of 2nd level page tables
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* below
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*/
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for_each_sdram_bank(mem)
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create_section(mem->start, mem->start, mem->size >> 20,
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PMD_SECT_DEF_CACHED);
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asm volatile (
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"bl __mmu_cache_on;"
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:
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:
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: "r0", "r1", "r2", "r3", "r6", "r10", "r12", "cc", "memory"
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);
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/*
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* Now that we have the MMU and caches on remap sdram again using
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* page tables
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*/
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for_each_sdram_bank(mem)
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arm_mmu_remap_sdram(mem);
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return 0;
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}
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struct outer_cache_fns outer_cache;
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@ -125,39 +248,41 @@ void mmu_disable(void)
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);
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}
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/*
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* For boards which need coherent memory for DMA. The idea
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* is simple: Setup a uncached section containing your SDRAM
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* and call setup_dma_coherent() with the offset between the
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* cached and the uncached section. dma_alloc_coherent() then
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* works using normal malloc but returns the corresponding
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* pointer in the uncached area.
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*/
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static unsigned long dma_coherent_offset;
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void setup_dma_coherent(unsigned long offset)
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{
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dma_coherent_offset = offset;
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}
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#define PAGE_ALIGN(s) ((s) + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
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void *dma_alloc_coherent(size_t size)
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{
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return xmemalign(4096, size) + dma_coherent_offset;
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void *ret;
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size = PAGE_ALIGN(size);
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ret = xmemalign(4096, size);
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#ifdef CONFIG_MMU
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dma_inv_range((unsigned long)ret, (unsigned long)ret + size);
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remap_range(ret, size, PTE_FLAGS_UNCACHED);
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#endif
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return ret;
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}
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unsigned long virt_to_phys(void *virt)
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{
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return (unsigned long)virt - dma_coherent_offset;
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return (unsigned long)virt;
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}
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void *phys_to_virt(unsigned long phys)
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{
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return (void *)(phys + dma_coherent_offset);
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return (void *)phys;
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}
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void dma_free_coherent(void *mem, size_t size)
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{
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free(mem - dma_coherent_offset);
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#ifdef CONFIG_MMU
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remap_range(mem, size, PTE_FLAGS_CACHED);
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#endif
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free(mem);
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}
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void dma_clean_range(unsigned long start, unsigned long end)
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@ -3,19 +3,29 @@
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#include <asm/pgtable.h>
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#include <malloc.h>
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#include <errno.h>
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#define PMD_SECT_DEF_UNCACHED (PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT)
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#define PMD_SECT_DEF_CACHED (PMD_SECT_WB | PMD_SECT_DEF_UNCACHED)
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void mmu_init(void);
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void mmu_enable(void);
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void mmu_disable(void);
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void arm_create_section(unsigned long virt, unsigned long phys, int size_m,
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unsigned int flags);
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struct arm_memory;
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void setup_dma_coherent(unsigned long offset);
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static inline void mmu_enable(void)
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{
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}
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void mmu_disable(void);
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static inline void arm_create_section(unsigned long virt, unsigned long phys, int size_m,
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unsigned int flags)
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{
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}
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static inline void setup_dma_coherent(unsigned long offset)
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{
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}
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#ifdef CONFIG_MMU
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int mmu_init(void);
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void *dma_alloc_coherent(size_t size);
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void dma_free_coherent(void *mem, size_t size);
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@ -221,6 +221,7 @@ int run_shell(void);
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#define ULLONG_MAX (~0ULL)
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#define PAGE_SIZE 4096
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#define PAGE_SHIFT 12
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int memory_display(char *addr, ulong offs, ulong nbytes, int size);
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