ARM: i.MX5: Add IPU clocks
Add the clocks for the IPU on i.MX5. Since these are many only add them when the driver is enabled. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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5910c62a67
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311d656f1e
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@ -113,6 +113,71 @@ static const char *usb_phy_sel_str[] = {
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"usb_phy_podf",
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"usb_phy_podf",
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};
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};
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static const char *mx51_ipu_di0_sel[] = {
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"di_pred",
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"osc",
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"ckih1",
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"tve_di",
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};
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static const char *mx53_ipu_di0_sel[] = {
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"di_pred",
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"osc",
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"ckih1",
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"di_pll4_podf",
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"dummy",
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"ldb_di0_div",
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};
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static const char *mx53_ldb_di0_sel[] = {
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"pll3_sw",
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"pll4_sw",
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};
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static const char *mx51_ipu_di1_sel[] = {
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"di_pred",
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"osc",
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"ckih1",
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"tve_di",
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"ipp_di1",
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};
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static const char *mx53_ipu_di1_sel[] = {
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"di_pred",
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"osc",
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"ckih1",
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"tve_di",
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"ipp_di1",
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"ldb_di1_div",
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};
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static const char *mx53_ldb_di1_sel[] = {
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"pll3_sw",
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"pll4_sw",
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};
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static const char *mx51_tve_ext_sel[] = {
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"osc",
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"ckih1",
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};
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static const char *mx53_tve_ext_sel[] = {
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"pll4_sw",
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"ckih1",
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};
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static const char *mx51_tve_sel[] = {
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"tve_pred",
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"tve_ext_sel",
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};
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static const char *ipu_sel[] = {
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"axi_a",
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"axi_b",
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"emi_slow_gate",
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"ahb",
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};
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static void __init mx5_clocks_common_init(void __iomem *base, unsigned long rate_ckil,
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static void __init mx5_clocks_common_init(void __iomem *base, unsigned long rate_ckil,
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unsigned long rate_osc, unsigned long rate_ckih1,
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unsigned long rate_osc, unsigned long rate_ckih1,
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unsigned long rate_ckih2)
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unsigned long rate_ckih2)
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@ -184,7 +249,31 @@ static void __init mx5_clocks_common_init(void __iomem *base, unsigned long rate
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clks[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "pll1_sw", base + CCM_CACRR, 0, 3);
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clks[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "pll1_sw", base + CCM_CACRR, 0, 3);
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}
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}
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static void mx5_clocks_ipu_init(void __iomem *regs)
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{
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clks[IMX5_CLK_IPU_SEL] = imx_clk_mux("ipu_sel", regs + CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
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}
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#ifdef CONFIG_ARCH_IMX51
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#ifdef CONFIG_ARCH_IMX51
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static void mx51_clocks_ipu_init(void __iomem *regs)
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{
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clks[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux_p("ipu_di0_sel", regs + CCM_CSCMR2, 26, 3,
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mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
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clks[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux_p("ipu_di1_sel", regs + CCM_CSCMR2, 29, 3,
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mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
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clks[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_p("tve_ext_sel", regs + CCM_CSCMR1, 6, 1,
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mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel));
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clks[IMX5_CLK_TVE_SEL] = imx_clk_mux("tve_sel", regs + CCM_CSCMR1, 7, 1,
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mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
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clks[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "pll3_sw", regs + CCM_CDCDR, 28, 3);
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mx5_clocks_ipu_init(regs);
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clkdev_add_physbase(clks[IMX5_CLK_IPU_SEL], MX51_IPU_BASE_ADDR, "bus");
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clkdev_add_physbase(clks[IMX5_CLK_IPU_DI0_SEL], MX51_IPU_BASE_ADDR, "di0");
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clkdev_add_physbase(clks[IMX5_CLK_IPU_DI1_SEL], MX51_IPU_BASE_ADDR, "di1");
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}
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int __init mx51_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigned long rate_osc,
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int __init mx51_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigned long rate_osc,
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unsigned long rate_ckih1, unsigned long rate_ckih2)
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unsigned long rate_ckih1, unsigned long rate_ckih2)
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{
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{
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@ -212,6 +301,9 @@ int __init mx51_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigne
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clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_PWM1_BASE_ADDR, "per");
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clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_PWM1_BASE_ADDR, "per");
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clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_PWM2_BASE_ADDR, "per");
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clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_PWM2_BASE_ADDR, "per");
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if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3))
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mx51_clocks_ipu_init(regs);
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return 0;
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return 0;
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}
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}
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@ -248,6 +340,32 @@ core_initcall(imx51_ccm_init);
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#endif
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#endif
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#ifdef CONFIG_ARCH_IMX53
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#ifdef CONFIG_ARCH_IMX53
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static void mx53_clocks_ipu_init(void __iomem *regs)
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{
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clks[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
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clks[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider("ldb_di1_div", "ldb_di1_div_3_5", regs + CCM_CSCMR2, 11, 1);
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clks[IMX5_CLK_LDB_DI1_SEL] = imx_clk_mux_p("ldb_di1_sel", regs + CCM_CSCMR2, 9, 1,
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mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel));
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clks[IMX5_CLK_DI_PLL4_PODF] = imx_clk_divider("di_pll4_podf", "pll4_sw", regs + CCM_CDCDR, 16, 3);
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clks[IMX5_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
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clks[IMX5_CLK_LDB_DI0_DIV] = imx_clk_divider("ldb_di0_div", "ldb_di0_div_3_5", regs + CCM_CSCMR2, 10, 1);
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clks[IMX5_CLK_LDB_DI0_SEL] = imx_clk_mux_p("ldb_di0_sel", regs + CCM_CSCMR2, 8, 1,
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mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel));
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clks[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux_p("ipu_di0_sel", regs + CCM_CSCMR2, 26, 3,
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mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
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clks[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux_p("ipu_di1_sel", regs + CCM_CSCMR2, 29, 3,
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mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
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clks[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_p("tve_ext_sel", regs + CCM_CSCMR1, 6, 1,
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mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel));
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clks[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "tve_ext_sel", regs + CCM_CDCDR, 28, 3);
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mx5_clocks_ipu_init(regs);
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clkdev_add_physbase(clks[IMX5_CLK_IPU_SEL], MX53_IPU_BASE_ADDR, "bus");
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clkdev_add_physbase(clks[IMX5_CLK_IPU_DI0_SEL], MX53_IPU_BASE_ADDR, "di0");
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clkdev_add_physbase(clks[IMX5_CLK_IPU_DI1_SEL], MX53_IPU_BASE_ADDR, "di1");
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}
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int __init mx53_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigned long rate_osc,
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int __init mx53_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigned long rate_osc,
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unsigned long rate_ckih1, unsigned long rate_ckih2)
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unsigned long rate_ckih1, unsigned long rate_ckih2)
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{
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{
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@ -277,6 +395,9 @@ int __init mx53_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigne
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clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_PWM1_BASE_ADDR, "per");
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clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_PWM1_BASE_ADDR, "per");
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clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_PWM2_BASE_ADDR, "per");
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clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_PWM2_BASE_ADDR, "per");
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if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3))
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mx53_clocks_ipu_init(regs);
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return 0;
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return 0;
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}
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}
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@ -13,6 +13,8 @@
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#define MX51_IROM_BASE_ADDR 0x0
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#define MX51_IROM_BASE_ADDR 0x0
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#define MX51_IPU_BASE_ADDR 0x40000000
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/*
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/*
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* AIPS 1
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* AIPS 1
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*/
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*/
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@ -5,6 +5,7 @@
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#define MX53_SATA_BASE_ADDR 0x10000000
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#define MX53_SATA_BASE_ADDR 0x10000000
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#define MX53_IPU_BASE_ADDR 0x18000000
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/*
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/*
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* SPBA global module enabled #0
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* SPBA global module enabled #0
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*/
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*/
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