boards: phytec-som-am335x: Add phycard-som support
Add support for the phyCARD SOM. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
parent
eb657a510b
commit
3297df00d6
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@ -23,6 +23,10 @@ Currently, barebox supports the following SOMs and boards:
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- PBA-B-01
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- PBA-B-01
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- phyCARD
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- PCA-A-XS1
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Building phycore-som-am335x
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Building phycore-som-am335x
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---------------------------
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---------------------------
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@ -4,6 +4,7 @@
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* Device initialization for the following modules and board variants:
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* Device initialization for the following modules and board variants:
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* - phyCORE: PCM-953, phyBOARD-MAIA, phyBOARD-WEGA
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* - phyCORE: PCM-953, phyBOARD-MAIA, phyBOARD-WEGA
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* - phyFLEX: PBA-B-01
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* - phyFLEX: PBA-B-01
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* - phyCARD: PCA-A-XS1
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*
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*
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* This program is free software; you can redistribute it and/or
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* modify it under the terms of the GNU General Public License as
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@ -89,6 +90,11 @@ static int physom_devices_init(void)
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barebox_set_hostname("pfla03");
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barebox_set_hostname("pfla03");
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}
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}
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if (of_machine_is_compatible("phytec,phycard-am335x-som")) {
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armlinux_set_architecture(MACH_TYPE_PCAAXS1);
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barebox_set_hostname("pcaaxs1");
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}
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/* Register update handler */
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/* Register update handler */
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am33xx_bbu_spi_nor_mlo_register_handler("MLO.spi", "/dev/m25p0.xload");
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am33xx_bbu_spi_nor_mlo_register_handler("MLO.spi", "/dev/m25p0.xload");
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am33xx_bbu_spi_nor_register_handler("spi", "/dev/m25p0.barebox");
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am33xx_bbu_spi_nor_register_handler("spi", "/dev/m25p0.barebox");
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@ -131,3 +131,7 @@ PHYTEC_ENTRY(start_am33xx_phytec_phycore_no_spi_sdram, am335x_phytec_phycore_som
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PHYTEC_ENTRY_MLO(start_am33xx_phytec_phyflex_sram_256mb, am335x_phytec_phyflex_som_mlo, PHYFLEX_MT41K128M16JT_256MB);
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PHYTEC_ENTRY_MLO(start_am33xx_phytec_phyflex_sram_256mb, am335x_phytec_phyflex_som_mlo, PHYFLEX_MT41K128M16JT_256MB);
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PHYTEC_ENTRY_MLO(start_am33xx_phytec_phyflex_sram_512mb, am335x_phytec_phyflex_som_mlo, PHYFLEX_MT41K256M16HA_512MB);
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PHYTEC_ENTRY_MLO(start_am33xx_phytec_phyflex_sram_512mb, am335x_phytec_phyflex_som_mlo, PHYFLEX_MT41K256M16HA_512MB);
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PHYTEC_ENTRY(start_am33xx_phytec_phyflex_sdram, am335x_phytec_phyflex_som);
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PHYTEC_ENTRY(start_am33xx_phytec_phyflex_sdram, am335x_phytec_phyflex_som);
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/* phycard-som */
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PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycard_sram_256mb, am335x_phytec_phycard_som_mlo, PHYCARD_NT5CB128M16BP_256MB);
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PHYTEC_ENTRY(start_am33xx_phytec_phycard_sdram, am335x_phytec_phycard_som);
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@ -29,6 +29,8 @@ enum {
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PHYCORE_MT41J64M1615IT_128MB,
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PHYCORE_MT41J64M1615IT_128MB,
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PHYCORE_MT41J256M16HA15EIT_512MB,
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PHYCORE_MT41J256M16HA15EIT_512MB,
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PHYCORE_MT41J512M8125IT_2x512MB,
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PHYCORE_MT41J512M8125IT_2x512MB,
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PHYCARD_NT5CB128M16BP_256MB,
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};
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};
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struct am335x_sdram_timings physom_timings[] = {
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struct am335x_sdram_timings physom_timings[] = {
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@ -149,6 +151,27 @@ struct am335x_sdram_timings physom_timings[] = {
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.wr_slave_ratio0 = 0x80,
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.wr_slave_ratio0 = 0x80,
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},
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},
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},
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},
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/* 256MB */
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[PHYCARD_NT5CB128M16BP_256MB] = {
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.regs = {
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.emif_read_latency = 0x7,
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.emif_tim1 = 0x0AAAD4DB,
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.emif_tim2 = 0x26437FDA,
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.emif_tim3 = 0x501F83FF,
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.sdram_config = 0x61C052B2,
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.zq_config = 0x50074BE4,
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.sdram_ref_ctrl = 0x00000C30,
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},
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.data = {
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.rd_slave_ratio0 = 0x35,
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.wr_dqs_slave_ratio0 = 0x3A,
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.fifo_we_slave_ratio0 = 0x9b,
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.wr_slave_ratio0 = 0x73,
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.use_rank0_delay = 0x01,
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.dll_lock_diff0 = 0x0,
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},
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},
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};
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};
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#endif
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#endif
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@ -29,7 +29,9 @@ pbl-dtb-$(CONFIG_MACH_NVIDIA_JETSON) += tegra124-jetson-tk1.dtb.o
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pbl-dtb-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o
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pbl-dtb-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o
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pbl-dtb-$(CONFIG_MACH_PCAAXL3) += imx6q-phytec-pbaa03.dtb.o
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pbl-dtb-$(CONFIG_MACH_PCAAXL3) += imx6q-phytec-pbaa03.dtb.o
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pbl-dtb-$(CONFIG_MACH_PCM038) += imx27-phytec-phycore-rdk.dtb.o
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pbl-dtb-$(CONFIG_MACH_PCM038) += imx27-phytec-phycore-rdk.dtb.o
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pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += am335x-phytec-phyflex-som.dtb.o am335x-phytec-phyflex-som-mlo.dtb.o am335x-phytec-phycore-som.dtb.o am335x-phytec-phycore-som-no-spi.dtb.o am335x-phytec-phycore-som-mlo.dtb.o
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pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += am335x-phytec-phyflex-som.dtb.o am335x-phytec-phyflex-som-mlo.dtb.o \
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am335x-phytec-phycore-som.dtb.o am335x-phytec-phycore-som-no-spi.dtb.o am335x-phytec-phycore-som-mlo.dtb.o \
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am335x-phytec-phycard-som.dtb.o am335x-phytec-phycard-som-mlo.dtb.o
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pbl-dtb-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6s-phytec-pbab01.dtb.o imx6dl-phytec-pbab01.dtb.o imx6q-phytec-pbab01.dtb.o imx6q-phytec-phyboard-alcor.dtb.o imx6dl-phytec-phyboard-subra.dtb.o
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pbl-dtb-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6s-phytec-pbab01.dtb.o imx6dl-phytec-pbab01.dtb.o imx6q-phytec-pbab01.dtb.o imx6q-phytec-phyboard-alcor.dtb.o imx6dl-phytec-phyboard-subra.dtb.o
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pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o
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pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o
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pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o
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pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o
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@ -0,0 +1,28 @@
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/*
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* Copyright (C) 2015 Wadim Egorov <w.egorovphytec.de> PHYTEC Messtechnik GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "am33xx.dtsi"
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#include "am335x-phytec-phycard-som.dtsi"
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/ {
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model = "Phytec phyCARD AM335x";
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compatible = "phytec,phycard-am335x-som", "phytec,am335x-som", "ti,am33xx";
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};
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/* Keep all bootsources disabled, we enable and register them
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* later while booting.
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*/
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&mmc1 {
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status = "disabled";
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};
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&gpmc {
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status = "disabled";
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};
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@ -0,0 +1,20 @@
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/*
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* Copyright (C) 2015 Wadim Egorov <w.egorovphytec.de> PHYTEC Messtechnik GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "am33xx.dtsi"
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#include "am335x-phytec-phycard-som.dtsi"
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/ {
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model = "Phytec phyCARD AM335x";
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compatible = "phytec,phycard-am335x-som", "phytec,am335x-som", "ti,am33xx";
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};
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&eeprom {
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status = "okay";
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};
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@ -0,0 +1,228 @@
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/ {
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chosen {
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linux,stdout-path = &uart0;
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environment-nand {
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compatible = "barebox,environment";
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device-path = &nand, "partname:bareboxenv";
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status = "disabled";
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};
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};
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};
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&am33xx_pinmux {
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i2c0_pins: pinmux_i2c0_pins {
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pinctrl-single,pins = <
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0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
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0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
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>;
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};
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uart0_pins: pinmux_uart0_pins {
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pinctrl-single,pins = <
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0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
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0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
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>;
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};
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uart3_pins: pinmux_uart3 {
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pinctrl-single,pins = <
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0x134 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd3.uart3_rxd */
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0x138 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd2.uart3_txd */
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>;
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};
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mmc1_pins: pinmux_mmc1_pins {
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pinctrl-single,pins = <
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0xf0 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat3.mmc0_dat3 */
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0xf4 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat2.mmc0_dat2 */
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0xf8 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat1.mmc0_dat1 */
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0xfc (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat0.mmc0_dat0 */
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0x100 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_clk.mmc0_clk */
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0x104 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_cmd.mmc0_cmd */
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>;
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};
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emac_rmii1_pins: pinmux_emac_rmii1_pins {
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pinctrl-single,pins = <
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0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
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0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
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0x114 (PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */
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0x124 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
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0x128 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
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0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
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0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
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0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
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>;
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};
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nandflash_pins_s0: nandflash_pins_s0 {
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pinctrl-single,pins = <
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0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
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0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
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0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
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0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
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0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
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0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
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0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
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0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
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0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
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0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
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0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
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0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
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0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
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0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
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>;
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};
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davinci_mdio_default: davinci_mdio_default {
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pinctrl-single,pins = <
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/* MDIO */
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0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
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0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
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>;
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};
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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status = "okay";
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clock-frequency = <400000>;
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eeprom: 24c32@52 {
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status = "disabled";
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compatible = "atmel,24c32";
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pagesize = <32>;
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reg = <0x54>;
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};
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};
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&mmc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins>;
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status = "okay";
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_pins>;
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status = "okay";
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};
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&davinci_mdio {
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pinctrl-names = "default";
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pinctrl-0 = <&davinci_mdio_default>;
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status = "okay";
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};
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&phy_sel {
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rmii-clock-ext;
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};
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&cpsw_emac0 {
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phy_id = <&davinci_mdio>, <0>;
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phy-mode = "rmii";
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};
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&mac {
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pinctrl-names = "default";
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pinctrl-0 = <&emac_rmii1_pins>;
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slaves = <1>;
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status = "okay";
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};
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&gpmc {
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status = "okay";
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pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&nandflash_pins_s0>;
|
||||||
|
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
|
||||||
|
nand: nand@0,0 {
|
||||||
|
reg = <0 0 0>; /* CS0, offset 0 */
|
||||||
|
nand-bus-width = <8>;
|
||||||
|
ti,nand-ecc-opt = "bch8";
|
||||||
|
gpmc,device-nand = "true";
|
||||||
|
gpmc,device-width = <1>;
|
||||||
|
gpmc,sync-clk-ps = <0>;
|
||||||
|
gpmc,cs-on-ns = <0>;
|
||||||
|
gpmc,cs-rd-off-ns = <30>;
|
||||||
|
gpmc,cs-wr-off-ns = <30>;
|
||||||
|
gpmc,adv-on-ns = <0>;
|
||||||
|
gpmc,adv-rd-off-ns = <30>;
|
||||||
|
gpmc,adv-wr-off-ns = <30>;
|
||||||
|
gpmc,we-on-ns = <0>;
|
||||||
|
gpmc,we-off-ns = <20>;
|
||||||
|
gpmc,oe-on-ns = <10>;
|
||||||
|
gpmc,oe-off-ns = <30>;
|
||||||
|
gpmc,access-ns = <30>;
|
||||||
|
gpmc,rd-cycle-ns = <30>;
|
||||||
|
gpmc,wr-cycle-ns = <30>;
|
||||||
|
gpmc,wait-pin = <1>;
|
||||||
|
gpmc,wait-on-read = "true";
|
||||||
|
gpmc,wait-on-write = "true";
|
||||||
|
gpmc,bus-turnaround-ns = <0>;
|
||||||
|
gpmc,cycle2cycle-delay-ns = <50>;
|
||||||
|
gpmc,cycle2cycle-diffcsen;
|
||||||
|
gpmc,clk-activation-ns = <0>;
|
||||||
|
gpmc,wait-monitoring-ns = <0>;
|
||||||
|
gpmc,wr-access-ns = <0>;
|
||||||
|
gpmc,wr-data-mux-bus-ns = <0>;
|
||||||
|
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
elm_id = <&elm>;
|
||||||
|
|
||||||
|
partition@0 {
|
||||||
|
label = "xload";
|
||||||
|
reg = <0x0 0x20000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@1 {
|
||||||
|
label = "xload_backup1";
|
||||||
|
reg = <0x20000 0x20000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@2 {
|
||||||
|
label = "xload_backup2";
|
||||||
|
reg = <0x40000 0x20000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@3 {
|
||||||
|
label = "xload_backup3";
|
||||||
|
reg = <0x60000 0x20000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@4 {
|
||||||
|
label = "barebox";
|
||||||
|
reg = <0x80000 0x80000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@5 {
|
||||||
|
label = "bareboxenv";
|
||||||
|
reg = <0x100000 0x40000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@6 {
|
||||||
|
label = "oftree";
|
||||||
|
reg = <0x140000 0x40000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@7 {
|
||||||
|
label = "kernel";
|
||||||
|
reg = <0x180000 0x800000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@8 {
|
||||||
|
label = "root";
|
||||||
|
reg = <0x980000 0x0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -51,6 +51,14 @@ pblx-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += start_am33xx_phytec_phyflex_sram_512mb
|
||||||
FILE_barebox-am33xx-phytec-phyflex-mlo-512mb.img = start_am33xx_phytec_phyflex_sram_512mb.pblx.mlo
|
FILE_barebox-am33xx-phytec-phyflex-mlo-512mb.img = start_am33xx_phytec_phyflex_sram_512mb.pblx.mlo
|
||||||
am33xx-mlo-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phyflex-mlo-512mb.img
|
am33xx-mlo-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phyflex-mlo-512mb.img
|
||||||
|
|
||||||
|
pblx-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += start_am33xx_phytec_phycard_sdram
|
||||||
|
FILE_barebox-am33xx-phytec-phycard.img = start_am33xx_phytec_phycard_sdram.pblx
|
||||||
|
am33xx-barebox-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycard.img
|
||||||
|
|
||||||
|
pblx-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += start_am33xx_phytec_phycard_sram_256mb
|
||||||
|
FILE_barebox-am33xx-phytec-phycard-mlo-256mb.img = start_am33xx_phytec_phycard_sram_256mb.pblx.mlo
|
||||||
|
am33xx-mlo-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycard-mlo-256mb.img
|
||||||
|
|
||||||
pblx-$(CONFIG_MACH_BEAGLEBONE) += start_am33xx_beaglebone_sdram
|
pblx-$(CONFIG_MACH_BEAGLEBONE) += start_am33xx_beaglebone_sdram
|
||||||
FILE_barebox-am33xx-beaglebone.img = start_am33xx_beaglebone_sdram.pblx
|
FILE_barebox-am33xx-beaglebone.img = start_am33xx_beaglebone_sdram.pblx
|
||||||
am33xx-barebox-$(CONFIG_MACH_BEAGLEBONE) += barebox-am33xx-beaglebone.img
|
am33xx-barebox-$(CONFIG_MACH_BEAGLEBONE) += barebox-am33xx-beaglebone.img
|
||||||
|
|
Loading…
Reference in New Issue