PCM037: Add support for different memory amounts
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
5ccd3fd093
commit
32f9f72e9f
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@ -181,6 +181,7 @@ config IMX_CLKO
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Say y here if you want to have the clko command which lets you select the
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frequency to output on this pin.
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source arch/arm/mach-imx/Kconfig
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source arch/arm/mach-netx/Kconfig
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source arch/arm/mach-omap/Kconfig
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@ -0,0 +1,25 @@
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menu "Board specific settings "
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if MACH_PCM037
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choice
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prompt "SDRAM Bank0"
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config PCM037_SDRAM_BANK0_128MB
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bool "128MB"
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config PCM037_SDRAM_BANK0_256MB
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bool "256MB"
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endchoice
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choice
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prompt "SDRAM Bank1"
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config PCM037_SDRAM_BANK1_NONE
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bool "none"
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config PCM037_SDRAM_BANK1_128MB
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bool "128MB"
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config PCM037_SDRAM_BANK1_256MB
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bool "256MB"
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endchoice
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endif
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endmenu
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@ -23,17 +23,15 @@
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#include <asm/arch/imx-regs.h>
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.macro REG reg, val
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ldr r2, =\reg
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ldr r3, =\val
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str r3, [r2]
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.endm
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#define writel(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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str r1, [r0];
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.macro REG8 reg, val
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ldr r2, =\reg
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ldr r3, =\val
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strb r3, [r2]
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.endm
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#define writeb(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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strb r1, [r0];
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.macro DELAY loops
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ldr r2, =\loops
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@ -46,19 +44,25 @@
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.globl board_init_lowlevel
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board_init_lowlevel:
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REG IPU_CONF, IPU_CONF_DI_EN
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REG CCM_CCMR, 0x074B0BF5
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writel(IPU_CONF_DI_EN, IPU_CONF)
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writel(0x074B0BF5, CCM_CCMR)
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DELAY 0x40000
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REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
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REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
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writel(0x074B0BF5 | CCMR_MPE, CCM_CCMR)
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writel((0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS, CCM_CCMR)
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REG CCM_PDR0, PDR0_CSI_PODF(0xff1) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
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writel(PDR0_CSI_PODF(0xff1) | \
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PDR0_PER_PODF(7) | \
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PDR0_HSP_PODF(3) | \
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PDR0_NFC_PODF(5) | \
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PDR0_IPG_PODF(1) | \
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PDR0_MAX_PODF(3) | \
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PDR0_MCU_PODF(0), \
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CCM_PDR0)
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REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
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REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1)
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writel(PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd), CCM_MPCTL)
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writel(PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1), CCM_SPCTL)
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/* Skip SDRAM initialization if we run from RAM */
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cmp pc, #0x80000000
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@ -69,45 +73,72 @@ board_init_lowlevel:
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mov pc, lr
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1:
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REG 0x43FAC26C, 0 /* SDCLK */
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REG 0x43FAC270, 0 /* CAS */
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REG 0x43FAC274, 0 /* RAS */
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REG 0x43FAC27C, 0x1000 /* CS2 CSD0) */
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REG 0x43FAC284, 0 /* DQM3 */
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REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 0x288..0x2DC) */
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REG 0x43FAC28C, 0
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REG 0x43FAC290, 0
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REG 0x43FAC294, 0
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REG 0x43FAC298, 0
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REG 0x43FAC29C, 0
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REG 0x43FAC2A0, 0
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REG 0x43FAC2A4, 0
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REG 0x43FAC2A8, 0
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REG 0x43FAC2AC, 0
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REG 0x43FAC2B0, 0
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REG 0x43FAC2B4, 0
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REG 0x43FAC2B8, 0
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REG 0x43FAC2BC, 0
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REG 0x43FAC2C0, 0
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REG 0x43FAC2C4, 0
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REG 0x43FAC2C8, 0
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REG 0x43FAC2CC, 0
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REG 0x43FAC2D0, 0
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REG 0x43FAC2D4, 0
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REG 0x43FAC2D8, 0
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REG 0x43FAC2DC, 0
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REG 0xB8001010, 0x00000004
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REG 0xB8001004, 0x006ac73a
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REG 0xB8001000, 0x92100000
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REG 0x80000f00, 0x12344321
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REG 0xB8001000, 0xa2100000
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REG 0x80000000, 0x12344321
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REG 0x80000000, 0x12344321
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REG 0xB8001000, 0xb2100000
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REG8 0x80000033, 0xda
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REG8 0x81000000, 0xff
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REG 0xB8001000, 0x82226080
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REG 0x80000000, 0xDEADBEEF
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REG 0xB8001010, 0x0000000c
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/* Configure IOMUXC */
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writel(0, 0x43FAC26C)/* SDCLK */
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writel(0, 0x43FAC270) /* CAS */
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writel(0, 0x43FAC274) /* RAS */
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writel(0x1000, 0x43FAC27C )/* CS2 CSD0) */
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writel(0, 0x43FAC284) /* DQM3 */
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writel(0, 0x43FAC288) /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 0x288..0x2DC) */
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writel(0, 0x43FAC28C)
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writel(0, 0x43FAC290)
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writel(0, 0x43FAC294)
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writel(0, 0x43FAC298)
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writel(0, 0x43FAC29C)
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writel(0, 0x43FAC2A0)
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writel(0, 0x43FAC2A4)
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writel(0, 0x43FAC2A8)
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writel(0, 0x43FAC2AC)
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writel(0, 0x43FAC2B0)
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writel(0, 0x43FAC2B4)
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writel(0, 0x43FAC2B8)
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writel(0, 0x43FAC2BC)
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writel(0, 0x43FAC2C0)
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writel(0, 0x43FAC2C4)
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writel(0, 0x43FAC2C8)
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writel(0, 0x43FAC2CC)
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writel(0, 0x43FAC2D0)
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writel(0, 0x43FAC2D4)
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writel(0, 0x43FAC2D8)
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writel(0, 0x43FAC2DC)
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#if defined CONFIG_PCM037_SDRAM_BANK0_128MB
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#define ROWS0 ESDCTL0_ROW13
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#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB
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#define ROWS0 ESDCTL0_ROW14
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#endif
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writel(0x00000004, ESDMISC)
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writel(0x006ac73a, ESDCFG0)
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writel(0x90100000 | ROWS0, ESDCTL0)
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writel(0x12344321, IMX_SDRAM_CS0 + 0xf00)
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writel(0xa0100000 | ROWS0, ESDCTL0)
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writel(0x12344321, IMX_SDRAM_CS0)
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writel(0x12344321, IMX_SDRAM_CS0)
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writel(0xb0100000 | ROWS0, ESDCTL0)
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writeb(0xda, IMX_SDRAM_CS0 + 0x33)
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writeb(0xff, IMX_SDRAM_CS0 + 0x01000000)
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writel(0x80226080 | ROWS0, ESDCTL0)
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writel(0xDEADBEEF, IMX_SDRAM_CS0)
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writel(0x0000000c, ESDMISC)
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#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
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#if defined CONFIG_PCM037_SDRAM_BANK1_128MB
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#define ROWS1 ESDCTL0_ROW13
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#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB
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#define ROWS1 ESDCTL0_ROW14
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#endif
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writel(0x006ac73a, ESDCFG1)
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writel(0x90100000 | ROWS1, ESDCTL1)
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writel(0x12344321, IMX_SDRAM_CS1 + 0xf00)
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writel(0xa0100000 | ROWS1, ESDCTL1)
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writel(0x12344321, IMX_SDRAM_CS1)
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writel(0x12344321, IMX_SDRAM_CS1)
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writel(0xb0100000 | ROWS1, ESDCTL1)
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writeb(0xda, IMX_SDRAM_CS1 + 0x33)
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writeb(0xff, IMX_SDRAM_CS1 + 0x01000000)
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writel(0x80226080 | ROWS1, ESDCTL1)
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writel(0xDEADBEEF, IMX_SDRAM_CS1)
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writel(0x0000000c, ESDMISC)
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#endif
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mov pc, lr
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@ -69,19 +69,41 @@ static struct device_d network_dev = {
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.type = DEVICE_TYPE_ETHER,
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};
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/*
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* 128MiB of SDRAM, data width is 32 bit
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*/
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static struct device_d sdram_dev = {
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#if defined CONFIG_PCM037_SDRAM_BANK0_128MB
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#define SDRAM0 128
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#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB
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#define SDRAM0 256
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#endif
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static struct device_d sdram0_dev = {
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.name = "ram",
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.id = "ram0",
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.map_base = IMX_SDRAM_CS0,
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.size = 128 * 1024 * 1024, /* fix size */
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.size = SDRAM0 * 1024 * 1024, /* fix size */
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.type = DEVICE_TYPE_DRAM,
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};
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#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
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#if defined CONFIG_PCM037_SDRAM_BANK1_128MB
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#define SDRAM1 128
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#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB
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#define SDRAM1 256
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#endif
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static struct device_d sdram1_dev = {
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.name = "ram",
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.id = "ram1",
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.map_base = IMX_SDRAM_CS1,
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.size = SDRAM1 * 1024 * 1024, /* fix size */
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.type = DEVICE_TYPE_DRAM,
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};
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#endif
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struct imx_nand_platform_data nand_info = {
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.width = 1,
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.hw_ecc = 1,
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@ -127,8 +149,10 @@ static int imx31_devices_init(void)
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register_device(&nand_dev);
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register_device(&network_dev);
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register_device(&sdram_dev);
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register_device(&sdram0_dev);
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#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
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register_device(&sdram1_dev);
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#endif
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armlinux_set_bootparams((void *)0x80000100);
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armlinux_set_architecture(MACH_TYPE_PCM037);
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