arm: imx6: add Gateworks Ventana board
For now only the Quad 1GB variant is supported. Tested: - starting barebox over USB - writing barebox to NAND with barebox_update - starting Linux kernel over TFTP Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Lucas Stach
Sascha Hauer
parent
1dbf849de7
commit
33bd1c4ef5
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@ -48,6 +48,7 @@ obj-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += globalscale-mirabox/
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obj-$(CONFIG_MACH_GUF_CUPID) += guf-cupid/
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obj-$(CONFIG_MACH_GUF_SANTARO) += guf-santaro/
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obj-$(CONFIG_MACH_GUF_VINCELL) += guf-vincell/
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obj-$(CONFIG_MACH_GW_VENTANA) += gateworks-ventana/
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obj-$(CONFIG_MACH_HIGHBANK) += highbank/
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obj-$(CONFIG_MACH_IMX21ADS) += freescale-mx21-ads/
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obj-$(CONFIG_MACH_IMX233_OLINUXINO) += imx233-olinuxino/
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@ -0,0 +1,2 @@
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obj-y += board.o gsc.o
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lwl-y += lowlevel.o
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@ -0,0 +1,96 @@
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/*
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* Copyright (C) 2014 Lucas Stach, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <environment.h>
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#include <i2c/i2c.h>
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#include <init.h>
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#include <linux/marvell_phy.h>
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#include <linux/phy.h>
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#include <mach/bbu.h>
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#include <mach/imx6.h>
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#include <net.h>
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#include "gsc.h"
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static int gw54xx_devices_init(void)
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{
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struct i2c_client client;
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struct device_node *dnode;
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u8 reg;
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u8 mac[6];
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if (!of_machine_is_compatible("gw,imx6q-gw54xx"))
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return 0;
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client.adapter = i2c_get_adapter(0);
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if (!client.adapter) {
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pr_err("could not get system controller i2c bus\n");
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return -ENODEV;
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}
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/* disable the GSC boot watchdog */
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client.addr = GSC_SC_ADDR;
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gsc_i2c_read(&client, GSC_SC_CTRL1, ®, 1);
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reg |= GSC_SC_CTRL1_WDDIS;
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gsc_i2c_write(&client, GSC_SC_CTRL1, ®, 1);
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/* read MAC adresses from EEPROM and attach to eth devices */
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dnode = of_find_node_by_alias(of_get_root_node(), "ethernet0");
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if (dnode) {
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client.addr = GSC_EEPROM_ADDR;
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gsc_i2c_read(&client, 0x00, mac, 6);
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of_eth_register_ethaddr(dnode, mac);
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}
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dnode = of_find_node_by_alias(of_get_root_node(), "ethernet1");
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if (dnode) {
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client.addr = GSC_EEPROM_ADDR;
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gsc_i2c_read(&client, 0x06, mac, 6);
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of_eth_register_ethaddr(dnode, mac);
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}
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imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT);
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barebox_set_hostname("gw54xx");
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return 0;
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}
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device_initcall(gw54xx_devices_init);
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static int marvell_88e1510_phy_fixup(struct phy_device *dev)
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{
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u32 val;
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/* LED settings */
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phy_write(dev, 22, 3);
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val = phy_read(dev, 16);
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val &= 0xff00;
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val |= 0x0017;
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phy_write(dev, 16, val);
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phy_write(dev, 22, 0);
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return 0;
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}
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static int gw54xx_coredevices_init(void)
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{
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if (!of_machine_is_compatible("gw,imx6q-gw54xx"))
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return 0;
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phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK,
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marvell_88e1510_phy_fixup);
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return 0;
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}
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coredevice_initcall(gw54xx_coredevices_init);
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@ -0,0 +1,8 @@
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wm 32 MX6_CCM_CCGR0 0x00C03F3F
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wm 32 MX6_CCM_CCGR1 0x0030FC03
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wm 32 MX6_CCM_CCGR2 0x0FFFC000
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wm 32 MX6_CCM_CCGR3 0x3FF00000
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wm 32 MX6_CCM_CCGR4 0xFFFFF300
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wm 32 MX6_CCM_CCGR5 0x0F0000C3
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wm 32 MX6_CCM_CCGR6 0x000003FF
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wm 32 MX6_CCM_CCOSR 0x000000FB
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@ -0,0 +1,11 @@
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soc imx6
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loadaddr 0x20000000
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dcdofs 0x400
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#include <mach/imx6-ddr-regs.h>
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#include <mach/imx6q-ddr-regs.h>
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#include <mach/imx6-ccm-regs.h>
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#include "ram-base.imxcfg"
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#include "quad_128x64.imxcfg"
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#include "clocks.imxcfg"
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@ -0,0 +1,67 @@
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/*
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* Copyright (C) 2013 Gateworks Corporation
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* Copyright (C) 2014 Lucas Stach, Pengutronix
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* Author: Tim Harvey <tharvey@gateworks.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* The Gateworks System Controller will fail to ACK a master transaction if
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* it is busy, which can occur during its 1HZ timer tick while reading ADC's.
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* When this does occur, it will never be busy long enough to fail more than
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* 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with
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* 3 retries.
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*/
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#include <common.h>
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#include <i2c/i2c.h>
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#include "gsc.h"
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int gsc_i2c_read(struct i2c_client *client, u32 addr, u8 *buf, u16 count)
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{
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int retry = 3;
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int n = 0;
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int ret;
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while (n++ < retry) {
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ret = i2c_read_reg(client, addr, buf, count);
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if (!ret)
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break;
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pr_debug("GSC read failed\n");
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if (ret != -ENODEV)
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break;
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mdelay(10);
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}
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return ret;
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}
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int gsc_i2c_write(struct i2c_client *client, u32 addr, const u8 *buf, u16 count)
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{
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int retry = 3;
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int n = 0;
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int ret;
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while (n++ < retry) {
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ret = i2c_write_reg(client, addr, buf, count);
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if (!ret)
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break;
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pr_debug("GSC write failed\n");
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if (ret != -ENODEV)
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break;
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mdelay(10);
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}
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mdelay(100);
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return ret;
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}
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@ -0,0 +1,58 @@
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/*
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* Copyright (C) 2013 Gateworks Corporation
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* Copyright (C) 2014 Lucas Stach, Pengutronix
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* Author: Tim Harvey <tharvey@gateworks.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* i2c slave addresses */
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#define GSC_SC_ADDR 0x20
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#define GSC_RTC_ADDR 0x68
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#define GSC_HWMON_ADDR 0x29
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#define GSC_EEPROM_ADDR 0x51
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/* System Controller registers */
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#define GSC_SC_CTRL0 0x00
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#define GSC_SC_CTRL1 0x01
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#define GSC_SC_CTRL1_WDDIS (1 << 7)
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#define GSC_SC_STATUS 0x0a
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#define GSC_SC_FWVER 0x0e
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/* System Controller Interrupt bits */
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#define GSC_SC_IRQ_PB 0 /* Pushbutton switch */
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#define GSC_SC_IRQ_SECURE 1 /* Secure Key erase complete */
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#define GSC_SC_IRQ_EEPROM_WP 2 /* EEPROM write violation */
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#define GSC_SC_IRQ_GPIO 4 /* GPIO change */
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#define GSC_SC_IRQ_TAMPER 5 /* Tamper detect */
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#define GSC_SC_IRQ_WATCHDOG 6 /* Watchdog trip */
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#define GSC_SC_IRQ_PBLONG 7 /* Pushbutton long hold */
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/* Hardware Monitor registers */
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#define GSC_HWMON_TEMP 0x00
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#define GSC_HWMON_VIN 0x02
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#define GSC_HWMON_VDD_3P3 0x05
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#define GSC_HWMON_VBATT 0x08
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#define GSC_HWMON_VDD_5P0 0x0b
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#define GSC_HWMON_VDD_CORE 0x0e
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#define GSC_HWMON_VDD_HIGH 0x14
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#define GSC_HWMON_VDD_DDR 0x17
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#define GSC_HWMON_VDD_SOC 0x11
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#define GSC_HWMON_VDD_1P8 0x1d
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#define GSC_HWMON_VDD_2P5 0x23
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#define GSC_HWMON_VDD_1P0 0x20
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/*
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* I2C transactions to the GSC are done via these functions which
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* perform retries in the case of a busy GSC NAK'ing the transaction
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*/
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int gsc_i2c_read(struct i2c_client *client, u32 addr, u8 *buf, u16 count);
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int gsc_i2c_write(struct i2c_client *client, u32 addr, const u8 *buf, u16 count);
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@ -0,0 +1,18 @@
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#include <common.h>
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#include <sizes.h>
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#include <mach/generic.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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extern char __dtb_imx6q_gw54xx_start[];
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ENTRY_FUNCTION(start_imx6q_gw54xx_1gx64, r0, r1, r2)
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{
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void *fdt;
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imx6_cpu_lowlevel_init();
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fdt = __dtb_imx6q_gw54xx_start - get_runtime_offset();
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barebox_arm_entry(0x10000000, SZ_1G, fdt);
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}
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@ -0,0 +1,41 @@
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wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x00190017
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wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x00140026
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wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x0021001C
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wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x0011001D
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wm 32 MX6_MMDC_P0_MPDGCTRL0 0x43380347
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wm 32 MX6_MMDC_P0_MPDGCTRL1 0x433C034D
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wm 32 MX6_MMDC_P1_MPDGCTRL0 0x032C0324
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wm 32 MX6_MMDC_P1_MPDGCTRL1 0x03310232
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wm 32 MX6_MMDC_P0_MPRDDLCTL 0x3C313539
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wm 32 MX6_MMDC_P1_MPRDDLCTL 0x37343141
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wm 32 MX6_MMDC_P0_MPWRDLCTL 0x36393C39
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wm 32 MX6_MMDC_P1_MPWRDLCTL 0x42344438
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wm 32 MX6_MMDC_P0_MPODTCTRL 0x00022227
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wm 32 MX6_MMDC_P1_MPODTCTRL 0x00022227
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wm 32 MX6_MMDC_P0_MPMUR0 0x00000800
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wm 32 MX6_MMDC_P1_MPMUR0 0x00000800
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wm 32 MX6_MMDC_P0_MDSCR 0x00008000
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wm 32 MX6_MMDC_P0_MDCFG0 0x54597955
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wm 32 MX6_MMDC_P0_MDCFG1 0xFF328F64
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wm 32 MX6_MMDC_P0_MDCFG2 0x01FF00DB
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wm 32 MX6_MMDC_P0_MDOTC 0x09444040
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wm 32 MX6_MMDC_P0_MDASP 0x0000007F
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wm 32 MX6_MMDC_P0_MDMISC 0x00011740
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wm 32 MX6_MMDC_P0_MDOR 0x00591023
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wm 32 MX6_MMDC_P0_MDCTL 0x831A0000
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wm 32 MX6_MMDC_P0_MDSCR 0x02088032
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wm 32 MX6_MMDC_P0_MDSCR 0x00008033
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wm 32 MX6_MMDC_P0_MDSCR 0x00408031
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wm 32 MX6_MMDC_P0_MDSCR 0x09408030
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wm 32 MX6_MMDC_P0_MDSCR 0x04008040
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wm 32 MX6_MMDC_P0_MDPDC 0x00025576
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wm 32 MX6_MMDC_P0_MAPSR 0x00011006
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wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1390003
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wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xA1390003
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wm 32 MX6_MMDC_P0_MDREF 0x00007800
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wm 32 MX6_MMDC_P0_MDSCR 0x00000000
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@ -0,0 +1,56 @@
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wm 32 MX6_IOM_DRAM_SDQS0 0x00000030
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wm 32 MX6_IOM_DRAM_SDQS1 0x00000030
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wm 32 MX6_IOM_DRAM_SDQS2 0x00000030
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wm 32 MX6_IOM_DRAM_SDQS3 0x00000030
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wm 32 MX6_IOM_DRAM_SDQS4 0x00000030
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wm 32 MX6_IOM_DRAM_SDQS5 0x00000030
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wm 32 MX6_IOM_DRAM_SDQS6 0x00000030
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wm 32 MX6_IOM_DRAM_SDQS7 0x00000030
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wm 32 MX6_IOM_DRAM_DQM0 0x00020030
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wm 32 MX6_IOM_DRAM_DQM1 0x00020030
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wm 32 MX6_IOM_DRAM_DQM2 0x00020030
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wm 32 MX6_IOM_DRAM_DQM3 0x00020030
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wm 32 MX6_IOM_DRAM_DQM4 0x00020030
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wm 32 MX6_IOM_DRAM_DQM5 0x00020030
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wm 32 MX6_IOM_DRAM_DQM6 0x00020030
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wm 32 MX6_IOM_DRAM_DQM7 0x00020030
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wm 32 MX6_IOM_GRP_B0DS 0x00000030
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wm 32 MX6_IOM_GRP_B1DS 0x00000030
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wm 32 MX6_IOM_GRP_B2DS 0x00000030
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wm 32 MX6_IOM_GRP_B3DS 0x00000030
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wm 32 MX6_IOM_GRP_B4DS 0x00000030
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wm 32 MX6_IOM_GRP_B5DS 0x00000030
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wm 32 MX6_IOM_GRP_B6DS 0x00000030
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wm 32 MX6_IOM_GRP_B7DS 0x00000030
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wm 32 MX6_IOM_DRAM_CAS 0x00020030
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wm 32 MX6_IOM_DRAM_RAS 0x00020030
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wm 32 MX6_IOM_DRAM_SDCLK_0 0x00020030
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wm 32 MX6_IOM_DRAM_SDCLK_1 0x00020030
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wm 32 MX6_IOM_DRAM_RESET 0x00020030
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wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000
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wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000
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wm 32 MX6_IOM_DRAM_SDBA2 0x00000000
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wm 32 MX6_IOM_DRAM_SDODT0 0x00003030
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wm 32 MX6_IOM_DRAM_SDODT1 0x00003030
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wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000
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wm 32 MX6_IOM_DDRMODE_CTL 0x00020000
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wm 32 MX6_IOM_GRP_DDRPKE 0x00000000
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wm 32 MX6_IOM_GRP_ADDDS 0x00000030
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wm 32 MX6_IOM_GRP_CTLDS 0x00000030
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wm 32 MX6_IOM_GRP_DDRMODE 0x00020000
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wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333
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wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333
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wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333
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wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333
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wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333
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wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333
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wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333
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wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333
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@ -1,6 +1,7 @@
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CONFIG_ARCH_IMX=y
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CONFIG_IMX_MULTI_BOARDS=y
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CONFIG_MACH_EFIKA_MX_SMARTBOOK=y
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CONFIG_MACH_EMBEDSKY_E9=y
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CONFIG_MACH_FREESCALE_MX51_PDK=y
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CONFIG_MACH_FREESCALE_MX53_LOCO=y
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CONFIG_MACH_TQMA53=y
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@ -16,10 +17,10 @@ CONFIG_MACH_SABRELITE=y
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CONFIG_MACH_SABRESD=y
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CONFIG_MACH_NITROGEN6X=y
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CONFIG_MACH_SOLIDRUN_MICROSOM=y
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CONFIG_MACH_EMBEDSKY_E9=y
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CONFIG_MACH_EMBEST_RIOTBOARD=y
|
||||
CONFIG_MACH_UDOO=y
|
||||
CONFIG_MACH_VARISCITE_MX6=y
|
||||
CONFIG_MACH_GW_VENTANA=y
|
||||
CONFIG_IMX_IIM=y
|
||||
CONFIG_IMX_IIM_FUSE_BLOW=y
|
||||
CONFIG_IMX_OCOTP=y
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ pbl-dtb-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o
|
|||
pbl-dtb-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += kirkwood-guruplug-server-plus-bb.dtb.o
|
||||
pbl-dtb-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += armada-370-mirabox-bb.dtb.o
|
||||
pbl-dtb-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o
|
||||
pbl-dtb-$(CONFIG_MACH_GW_VENTANA) += imx6q-gw54xx.dtb.o
|
||||
pbl-dtb-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += armada-xp-gp-bb.dtb.o
|
||||
pbl-dtb-$(CONFIG_MACH_NITROGEN6X) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o
|
||||
pbl-dtb-$(CONFIG_MACH_NVIDIA_BEAVER) += tegra30-beaver.dtb.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright 2013 Gateworks Corporation
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-gw54xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Gateworks Ventana i.MX6 Quad GW54XX";
|
||||
compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright 2013 Gateworks Corporation
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <arm/imx6qdl-gw54xx.dtsi>
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
linux,stdout-path = &uart2;
|
||||
|
||||
environment@0 {
|
||||
compatible = "barebox,environment";
|
||||
device-path = &gpmi, "partname:barebox-environment";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpmi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "barebox";
|
||||
reg = <0x0 0x400000>;
|
||||
};
|
||||
|
||||
partition@1 {
|
||||
label = "barebox-environment";
|
||||
reg = <0x400000 0x20000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -291,6 +291,9 @@ config MACH_VARISCITE_MX6
|
|||
bool "Variscite i.MX6 Quad SOM"
|
||||
select ARCH_IMX6
|
||||
|
||||
config MACH_GW_VENTANA
|
||||
bool "Gateworks Ventana SBC"
|
||||
select ARCH_IMX6
|
||||
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -194,3 +194,8 @@ pblx-$(CONFIG_MACH_PCAAXL3) += start_phytec_pbaa03_2gib
|
|||
CFG_start_phytec_pbaa03_2gib.pblx.imximg = $(board)/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg
|
||||
FILE_barebox-phytec-pbaa03-2gib.img = start_phytec_pbaa03_2gib.pblx.imximg
|
||||
image-$(CONFIG_MACH_PCAAXL3) += barebox-phytec-pbaa03-2gib.img
|
||||
|
||||
pblx-$(CONFIG_MACH_GW_VENTANA) += start_imx6q_gw54xx_1gx64
|
||||
CFG_start_imx6q_gw54xx_1gx64.pblx.imximg = $(board)/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg
|
||||
FILE_barebox-gateworks-imx6q-ventana-1gx64.img = start_imx6q_gw54xx_1gx64.pblx.imximg
|
||||
image-$(CONFIG_MACH_GW_VENTANA) += barebox-gateworks-imx6q-ventana-1gx64.img
|
||||
|
|
|
|||
Loading…
Reference in New Issue