Merge branch 'for-next/socfpga'
This commit is contained in:
Sascha Hauer
commit
35405138c8
|
|
@ -45,15 +45,6 @@ handoff files. As these files are split up in the code base and generated
|
|||
explicitely for some specific U-boot code base, some manual work might be
|
||||
necessary.
|
||||
|
||||
The following files are generic and belong into the
|
||||
`arch/arm/mach-socfpga` directory tree:
|
||||
|
||||
* sequencer.c (Not for the faint of heart.)
|
||||
* sequencer.h
|
||||
* system.h
|
||||
|
||||
It should normally not be necessary to touch these if barebox is up-to-date.
|
||||
|
||||
The boardspecific files for `arch/arm/boards/<yourboard>` are:
|
||||
|
||||
* iocsr_config_cyclone5.c
|
||||
|
|
@ -78,3 +69,20 @@ To update the handoff files, the following procedure is necessary::
|
|||
7. Click ``Ok`` than ``Generate``
|
||||
8. Copy the files generated in `software/spl_bsp/generated/` to your
|
||||
board folder
|
||||
|
||||
The following files are generic and belong into the
|
||||
`arch/arm/mach-socfpga` directory tree:
|
||||
|
||||
* sdram_io.h
|
||||
* sequencer.c
|
||||
* sequencer.h
|
||||
* sequencer_defines.h
|
||||
* system.h
|
||||
* tclrpt.h
|
||||
|
||||
To add these files, run::
|
||||
|
||||
scripts/socfpga_get_sequencer <UBOOT-SRC> scripts/socfpga_sequencer_defines_defaults
|
||||
|
||||
where `<UBOOT-SRC>` is the directory where the Altera bsp-editor generated the u-boot
|
||||
directory. Refer to the Altera documentation for how to use the bsp-editor.
|
||||
|
|
|
|||
|
|
@ -83,9 +83,8 @@ static noinline void socrates_entry(void)
|
|||
|
||||
puts_ll("SDRAM calibration...\n");
|
||||
|
||||
ret = socfpga_sdram_calibration(inst_rom_init, inst_rom_init_size,
|
||||
ac_rom_init, ac_rom_init_size);
|
||||
if (ret)
|
||||
ret = socfpga_mem_calibration();
|
||||
if (!ret)
|
||||
hang();
|
||||
|
||||
puts_ll("done\n");
|
||||
|
|
|
|||
|
|
@ -83,9 +83,8 @@ static noinline void sockit_entry(void)
|
|||
|
||||
puts_ll("SDRAM calibration...\n");
|
||||
|
||||
ret = socfpga_sdram_calibration(inst_rom_init, inst_rom_init_size,
|
||||
ac_rom_init, ac_rom_init_size);
|
||||
if (ret)
|
||||
ret = socfpga_mem_calibration();
|
||||
if (!ret)
|
||||
hang();
|
||||
|
||||
puts_ll("done\n");
|
||||
|
|
|
|||
|
|
@ -28,8 +28,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
const uint32_t inst_rom_init_size = 127;
|
||||
const uint32_t inst_rom_init[127] =
|
||||
static const uint32_t inst_rom_init_size = 127;
|
||||
static const uint32_t inst_rom_init[127] =
|
||||
{
|
||||
0x80000,
|
||||
0x80680,
|
||||
|
|
|
|||
|
|
@ -123,11 +123,14 @@ void socfpga_cm_basic_init(const struct socfpga_cm_config *cfg)
|
|||
* Put all plls VCO registers back to reset value.
|
||||
* Some code might have messed with them.
|
||||
*/
|
||||
writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
|
||||
writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
|
||||
~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
|
||||
cm + CLKMGR_MAINPLLGRP_VCO_ADDRESS);
|
||||
writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
|
||||
writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
|
||||
~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
|
||||
cm + CLKMGR_PERPLLGRP_VCO_ADDRESS);
|
||||
writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
|
||||
writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
|
||||
~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
|
||||
cm + CLKMGR_SDRPLLGRP_VCO_ADDRESS);
|
||||
|
||||
/*
|
||||
|
|
@ -151,21 +154,27 @@ void socfpga_cm_basic_init(const struct socfpga_cm_config *cfg)
|
|||
* We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
|
||||
* with numerator and denominator.
|
||||
*/
|
||||
writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
|
||||
writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN,
|
||||
cm + CLKMGR_MAINPLLGRP_VCO_ADDRESS);
|
||||
writel(cfg->peri_vco_base | CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
|
||||
writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN,
|
||||
cm + CLKMGR_PERPLLGRP_VCO_ADDRESS);
|
||||
writel(cfg->sdram_vco_base | CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
|
||||
cm + CLKMGR_SDRPLLGRP_VCO_ADDRESS);
|
||||
writel(cfg->sdram_vco_base |
|
||||
CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
|
||||
CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
|
||||
CLEAR_BGP_EN_PWRDN,
|
||||
cm + CLKMGR_SDRPLLGRP_VCO_ADDRESS);
|
||||
|
||||
writel(cfg->mpuclk, cm + CLKMGR_MAINPLLGRP_MPUCLK_ADDRESS);
|
||||
writel(cfg->mainclk, cm + CLKMGR_MAINPLLGRP_MAINCLK_ADDRESS);
|
||||
writel(cfg->alteragrp_mpu, cm + CLKMGR_ALTERAGRP_MPUCLK);
|
||||
writel(cfg->dbgatclk, cm + CLKMGR_MAINPLLGRP_DBGATCLK_ADDRESS);
|
||||
writel(cfg->alteregrp_main, cm + CLKMGR_ALTERAGRP_MAINCLK);
|
||||
writel(cfg->cfg2fuser0clk, cm + CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_ADDRESS);
|
||||
writel(cfg->emac0clk, cm + CLKMGR_PERPLLGRP_EMAC0CLK_ADDRESS);
|
||||
writel(cfg->emac1clk, cm + CLKMGR_PERPLLGRP_EMAC1CLK_ADDRESS);
|
||||
writel(cfg->mainqspiclk, cm + CLKMGR_MAINPLLGRP_MAINQSPICLK_ADDRESS);
|
||||
writel(cfg->perqspiclk, cm + CLKMGR_PERPLLGRP_PERQSPICLK_ADDRESS);
|
||||
writel(cfg->mainnandsdmmcclk, cm + CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_ADDRESS);
|
||||
writel(cfg->pernandsdmmcclk, cm + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_ADDRESS);
|
||||
writel(cfg->perbaseclk, cm + CLKMGR_PERPLLGRP_PERBASECLK_ADDRESS);
|
||||
writel(cfg->s2fuser1clk, cm + CLKMGR_PERPLLGRP_S2FUSER1CLK_ADDRESS);
|
||||
|
|
@ -282,4 +291,8 @@ void socfpga_cm_basic_init(const struct socfpga_cm_config *cfg)
|
|||
writel(~0, cm + CLKMGR_MAINPLLGRP_EN_ADDRESS);
|
||||
writel(~0, cm + CLKMGR_PERPLLGRP_EN_ADDRESS);
|
||||
writel(~0, cm + CLKMGR_SDRPLLGRP_EN_ADDRESS);
|
||||
|
||||
val = readl(cm + CLKMGR_DBCTRL_ADDRESS);
|
||||
val |= CLKMGR_DBCTRL_STAYOSC1_MASK;
|
||||
writel(val, cm + CLKMGR_DBCTRL_ADDRESS);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -50,6 +50,10 @@ struct socfpga_cm_config {
|
|||
uint32_t ddr2xdqsclk;
|
||||
uint32_t ddrdqclk;
|
||||
uint32_t s2fuser2clk;
|
||||
|
||||
/* altera group */
|
||||
uint32_t alteragrp_mpu;
|
||||
uint32_t alteregrp_main;
|
||||
};
|
||||
|
||||
void socfpga_cm_basic_init(const struct socfpga_cm_config *cfg);
|
||||
|
|
@ -95,7 +99,10 @@ void socfpga_cm_basic_init(const struct socfpga_cm_config *cfg);
|
|||
#define CLKMGR_SDRPLLGRP_DDRDQCLK_ADDRESS 0xd0
|
||||
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_ADDRESS 0xd4
|
||||
#define CLKMGR_SDRPLLGRP_EN_ADDRESS 0xd8
|
||||
#define CLKMGR_ALTERAGRP_MPUCLK 0xe0
|
||||
#define CLKMGR_ALTERAGRP_MAINCLK 0xe4
|
||||
|
||||
#define CLKMGR_DBCTRL_STAYOSC1_MASK 0x00000001
|
||||
#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
|
||||
#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
|
||||
#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
|
||||
|
|
@ -185,4 +192,9 @@ void socfpga_cm_basic_init(const struct socfpga_cm_config *cfg);
|
|||
#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
|
||||
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
|
||||
|
||||
#define CLEAR_BGP_EN_PWRDN \
|
||||
(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
|
||||
CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
|
||||
CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
|
||||
|
||||
#endif /* _CLOCK_MANAGER_H_ */
|
||||
|
|
|
|||
|
|
@ -50,4 +50,7 @@ static struct socfpga_cm_config cm_default_cfg = {
|
|||
CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
|
||||
.s2fuser2clk = CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) |
|
||||
CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
|
||||
/* undocumented alteragrp */
|
||||
.alteragrp_mpu = CONFIG_HPS_ALTERAGRP_MPUCLK,
|
||||
.alteregrp_main = CONFIG_HPS_ALTERAGRP_MAINCLK,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Copyright Altera Corporation (C) 2012-2014. All rights reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Altera Corporation nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <mach/sdram.h>
|
||||
|
||||
#define MGR_SELECT_MASK 0xf8000
|
||||
|
||||
#define APB_BASE_SCC_MGR SDR_PHYGRP_SCCGRP_ADDRESS
|
||||
#define APB_BASE_PHY_MGR SDR_PHYGRP_PHYMGRGRP_ADDRESS
|
||||
#define APB_BASE_RW_MGR SDR_PHYGRP_RWMGRGRP_ADDRESS
|
||||
#define APB_BASE_DATA_MGR SDR_PHYGRP_DATAMGRGRP_ADDRESS
|
||||
#define APB_BASE_REG_FILE SDR_PHYGRP_REGFILEGRP_ADDRESS
|
||||
#define APB_BASE_MMR SDR_CTRLGRP_ADDRESS
|
||||
|
||||
#define __AVL_TO_APB(ADDR) \
|
||||
((((ADDR) & MGR_SELECT_MASK) == (BASE_PHY_MGR)) ? (APB_BASE_PHY_MGR) | (((ADDR) >> (14-6)) & (0x1<<6)) | ((ADDR) & 0x3f) : \
|
||||
(((ADDR) & MGR_SELECT_MASK) == (BASE_RW_MGR)) ? (APB_BASE_RW_MGR) | ((ADDR) & 0x1fff) : \
|
||||
(((ADDR) & MGR_SELECT_MASK) == (BASE_DATA_MGR)) ? (APB_BASE_DATA_MGR) | ((ADDR) & 0x7ff) : \
|
||||
(((ADDR) & MGR_SELECT_MASK) == (BASE_SCC_MGR)) ? (APB_BASE_SCC_MGR) | ((ADDR) & 0xfff) : \
|
||||
(((ADDR) & MGR_SELECT_MASK) == (BASE_REG_FILE)) ? (APB_BASE_REG_FILE) | ((ADDR) & 0x7ff) : \
|
||||
(((ADDR) & MGR_SELECT_MASK) == (BASE_MMR)) ? (APB_BASE_MMR) | ((ADDR) & 0xfff) : \
|
||||
-1)
|
||||
|
||||
#define IOWR_32DIRECT(BASE, OFFSET, DATA) \
|
||||
write_register(HPS_SDR_BASE, __AVL_TO_APB((uint32_t)((BASE) + (OFFSET))), DATA)
|
||||
|
||||
#define IORD_32DIRECT(BASE, OFFSET) \
|
||||
read_register(HPS_SDR_BASE, __AVL_TO_APB((uint32_t)((BASE) + (OFFSET))))
|
||||
#define write_register(BASE, OFFSET, DATA) \
|
||||
writel(DATA, ((BASE) + (OFFSET)))
|
||||
#define read_register(BASE, OFFSET) \
|
||||
readl((BASE) + (OFFSET))
|
||||
#define HPS_SDR_BASE 0xffc20000
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -2,70 +2,38 @@
|
|||
#define _SEQUENCER_H_
|
||||
|
||||
/*
|
||||
* Copyright Altera Corporation (C) 2012-2014. All rights reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Altera Corporation nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#define MRS_MIRROR_PING_PONG_ATSO 0
|
||||
#define DYNAMIC_CALIBRATION_MODE 0
|
||||
#define STATIC_QUICK_CALIBRATION 0
|
||||
#define DISABLE_GUARANTEED_READ 0
|
||||
#define STATIC_SKIP_CALIBRATION 0
|
||||
|
||||
#if ENABLE_ASSERT
|
||||
#define ERR_IE_TEXT "Internal Error: Sub-system: %s, File: %s, Line: %d\n%s%s"
|
||||
|
||||
#define ALTERA_INTERNAL_ERROR(string) \
|
||||
{err_report_internal_error(string, "SEQ", __FILE__, __LINE__); \
|
||||
exit(-1); }
|
||||
|
||||
#define ALTERA_ASSERT(condition) \
|
||||
if (!(condition)) {\
|
||||
ALTERA_INTERNAL_ERROR(#condition); }
|
||||
#define ALTERA_INFO_ASSERT(condition, text) \
|
||||
if (!(condition)) {\
|
||||
ALTERA_INTERNAL_ERROR(text); }
|
||||
|
||||
#else
|
||||
* Copyright Altera Corporation (C) 2012-2014. All rights reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Altera Corporation nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#define ALTERA_ASSERT(condition)
|
||||
#define ALTERA_INFO_ASSERT(condition, text)
|
||||
#define ALTERA_INFO_ASSERT(condition,text)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if RLDRAMII
|
||||
#define RW_MGR_NUM_DM_PER_WRITE_GROUP (1)
|
||||
#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (1)
|
||||
#else
|
||||
#define RW_MGR_NUM_DM_PER_WRITE_GROUP (RW_MGR_MEM_DATA_MASK_WIDTH \
|
||||
/ RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
|
||||
#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (RW_MGR_TRUE_MEM_DATA_MASK_WIDTH \
|
||||
/ RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
|
||||
#endif
|
||||
#define RW_MGR_NUM_DM_PER_WRITE_GROUP (RW_MGR_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
|
||||
#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (RW_MGR_TRUE_MEM_DATA_MASK_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
|
||||
|
||||
#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
|
||||
#define NUM_RANKS_PER_SHADOW_REG (RW_MGR_MEM_NUMBER_OF_RANKS / NUM_SHADOW_REGS)
|
||||
|
|
@ -75,11 +43,9 @@
|
|||
|
||||
#define RW_MGR_DI_BASE (BASE_RW_MGR + 0x0020)
|
||||
|
||||
#if DDR3
|
||||
#define DDR3_MR1_ODT_MASK 0xFFFFFD99
|
||||
#define DDR3_MR2_ODT_MASK 0xFFFFF9FF
|
||||
#define DDR3_AC_MIRR_MASK 0x020A8
|
||||
#endif /* DDR3 */
|
||||
|
||||
#define RW_MGR_LOAD_CNTR_0 BASE_RW_MGR + 0x0800
|
||||
#define RW_MGR_LOAD_CNTR_1 BASE_RW_MGR + 0x0804
|
||||
|
|
@ -142,10 +108,7 @@
|
|||
#define CAL_SUBSTAGE_REFRESH 1
|
||||
|
||||
#define MAX_RANKS (RW_MGR_MEM_NUMBER_OF_RANKS)
|
||||
#define MAX_DQS (RW_MGR_MEM_IF_WRITE_DQS_WIDTH > \
|
||||
RW_MGR_MEM_IF_READ_DQS_WIDTH ? \
|
||||
RW_MGR_MEM_IF_WRITE_DQS_WIDTH : \
|
||||
RW_MGR_MEM_IF_READ_DQS_WIDTH)
|
||||
#define MAX_DQS (RW_MGR_MEM_IF_WRITE_DQS_WIDTH > RW_MGR_MEM_IF_READ_DQS_WIDTH ? RW_MGR_MEM_IF_WRITE_DQS_WIDTH : RW_MGR_MEM_IF_READ_DQS_WIDTH)
|
||||
#define MAX_DQ (RW_MGR_MEM_DATA_WIDTH)
|
||||
#define MAX_DM (RW_MGR_MEM_DATA_MASK_WIDTH)
|
||||
|
||||
|
|
@ -158,19 +121,22 @@
|
|||
* - The remaining words are part of the transfer.
|
||||
*/
|
||||
|
||||
#define BASE_PTR_MGR SEQUENCER_PTR_MGR_INST_BASE
|
||||
#define BASE_PHY_MGR SDR_PHYGRP_PHYMGRGRP_ADDRESS
|
||||
#define BASE_RW_MGR SDR_PHYGRP_RWMGRGRP_ADDRESS
|
||||
#define BASE_DATA_MGR SDR_PHYGRP_DATAMGRGRP_ADDRESS
|
||||
#define BASE_SCC_MGR SDR_PHYGRP_SCCGRP_ADDRESS
|
||||
#define BASE_REG_FILE SDR_PHYGRP_REGFILEGRP_ADDRESS
|
||||
#define BASE_TIMER SEQUENCER_TIMER_INST_BASE
|
||||
#define BASE_MMR SDR_CTRLGRP_ADDRESS
|
||||
#define BASE_TRK_MGR (0x000D0000)
|
||||
/* Define the base address of each manager. */
|
||||
|
||||
/* MarkW: how should these base addresses be done for A-V? */
|
||||
#define BASE_PTR_MGR SEQUENCER_PTR_MGR_INST_BASE
|
||||
#define BASE_PHY_MGR (0x00088000)
|
||||
#define BASE_RW_MGR (0x00090000)
|
||||
#define BASE_DATA_MGR (0x00098000)
|
||||
#define BASE_SCC_MGR SEQUENCER_SCC_MGR_INST_BASE
|
||||
#define BASE_REG_FILE SEQUENCER_REG_FILE_INST_BASE
|
||||
#define BASE_TIMER SEQUENCER_TIMER_INST_BASE
|
||||
#define BASE_MMR (0x000C0000)
|
||||
#define BASE_TRK_MGR (0x000D0000)
|
||||
|
||||
/* Register file addresses. */
|
||||
#define REG_FILE_SIGNATURE (BASE_REG_FILE + 0x0000)
|
||||
#define REG_FILE_DEBUG_DATA_ADDR (BASE_REG_FILE + 0x0004)
|
||||
#define REG_FILE_SIGNATURE (BASE_REG_FILE + 0x0000)
|
||||
#define REG_FILE_DEBUG_DATA_ADDR (BASE_REG_FILE + 0x0004)
|
||||
#define REG_FILE_CUR_STAGE (BASE_REG_FILE + 0x0008)
|
||||
#define REG_FILE_FOM (BASE_REG_FILE + 0x000C)
|
||||
#define REG_FILE_FAILING_STAGE (BASE_REG_FILE + 0x0010)
|
||||
|
|
@ -184,37 +150,28 @@
|
|||
#define REG_FILE_TRK_RW_MGR_ADDR (BASE_REG_FILE + 0x002C)
|
||||
#define REG_FILE_TRK_READ_DQS_WIDTH (BASE_REG_FILE + 0x0030)
|
||||
#define REG_FILE_TRK_RFSH (BASE_REG_FILE + 0x0034)
|
||||
#define CTRL_CONFIG_REG (BASE_MMR + 0x0000)
|
||||
|
||||
/* PHY manager configuration registers. */
|
||||
|
||||
#define PHY_MGR_PHY_RLAT (BASE_PHY_MGR + 0x40 + 0x00)
|
||||
#define PHY_MGR_RESET_MEM_STBL (BASE_PHY_MGR + 0x40 + 0x04)
|
||||
#define PHY_MGR_MUX_SEL (BASE_PHY_MGR + 0x40 + 0x08)
|
||||
#define PHY_MGR_CAL_STATUS (BASE_PHY_MGR + 0x40 + 0x0c)
|
||||
#define PHY_MGR_CAL_DEBUG_INFO (BASE_PHY_MGR + 0x40 + 0x10)
|
||||
#define PHY_MGR_VFIFO_RD_EN_OVRD (BASE_PHY_MGR + 0x40 + 0x14)
|
||||
#if CALIBRATE_BIT_SLIPS
|
||||
#define PHY_MGR_FR_SHIFT (BASE_PHY_MGR + 0x40 + 0x20)
|
||||
#if MULTIPLE_AFI_WLAT
|
||||
#define PHY_MGR_AFI_WLAT (BASE_PHY_MGR + 0x40 + 0x20 + 4 * \
|
||||
RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
|
||||
#else
|
||||
#define PHY_MGR_AFI_WLAT (BASE_PHY_MGR + 0x40 + 0x18)
|
||||
#endif
|
||||
#else
|
||||
#define PHY_MGR_AFI_WLAT (BASE_PHY_MGR + 0x40 + 0x18)
|
||||
#endif
|
||||
#define PHY_MGR_AFI_RLAT (BASE_PHY_MGR + 0x40 + 0x1c)
|
||||
#define PHY_MGR_PHY_RLAT (BASE_PHY_MGR + 0x4000)
|
||||
#define PHY_MGR_RESET_MEM_STBL (BASE_PHY_MGR + 0x4004)
|
||||
#define PHY_MGR_MUX_SEL (BASE_PHY_MGR + 0x4008)
|
||||
#define PHY_MGR_CAL_STATUS (BASE_PHY_MGR + 0x400c)
|
||||
#define PHY_MGR_CAL_DEBUG_INFO (BASE_PHY_MGR + 0x4010)
|
||||
#define PHY_MGR_VFIFO_RD_EN_OVRD (BASE_PHY_MGR + 0x4014)
|
||||
#define PHY_MGR_AFI_WLAT (BASE_PHY_MGR + 0x4018)
|
||||
#define PHY_MGR_AFI_RLAT (BASE_PHY_MGR + 0x401c)
|
||||
|
||||
#define PHY_MGR_CAL_RESET (0)
|
||||
#define PHY_MGR_CAL_RESET (0)
|
||||
#define PHY_MGR_CAL_SUCCESS (1)
|
||||
#define PHY_MGR_CAL_FAIL (2)
|
||||
#define PHY_MGR_CAL_FAIL (2)
|
||||
|
||||
/* PHY manager command addresses. */
|
||||
|
||||
#define PHY_MGR_CMD_INC_VFIFO_FR (BASE_PHY_MGR + 0x0000)
|
||||
#define PHY_MGR_CMD_INC_VFIFO_HR (BASE_PHY_MGR + 0x0004)
|
||||
#define PHY_MGR_CMD_INC_VFIFO_HARD_PHY (BASE_PHY_MGR + 0x0004)
|
||||
#define PHY_MGR_CMD_INC_VFIFO_HARD_PHY (BASE_PHY_MGR + 0x0004)
|
||||
#define PHY_MGR_CMD_FIFO_RESET (BASE_PHY_MGR + 0x0008)
|
||||
#define PHY_MGR_CMD_INC_VFIFO_FR_HR (BASE_PHY_MGR + 0x000C)
|
||||
#define PHY_MGR_CMD_INC_VFIFO_QR (BASE_PHY_MGR + 0x0010)
|
||||
|
|
@ -227,25 +184,25 @@
|
|||
#define PHY_MGR_CALIB_SKIP_STEPS (BASE_PHY_MGR + 0x000c)
|
||||
#define PHY_MGR_CALIB_VFIFO_OFFSET (BASE_PHY_MGR + 0x0010)
|
||||
#define PHY_MGR_CALIB_LFIFO_OFFSET (BASE_PHY_MGR + 0x0014)
|
||||
#define PHY_MGR_RDIMM (BASE_PHY_MGR + 0x0018)
|
||||
#define PHY_MGR_MEM_T_WL (BASE_PHY_MGR + 0x001c)
|
||||
#define PHY_MGR_MEM_T_RL (BASE_PHY_MGR + 0x0020)
|
||||
#define PHY_MGR_RDIMM (BASE_PHY_MGR + 0x0018)
|
||||
#define PHY_MGR_MEM_T_WL (BASE_PHY_MGR + 0x001c)
|
||||
#define PHY_MGR_MEM_T_RL (BASE_PHY_MGR + 0x0020)
|
||||
|
||||
/* Data Manager */
|
||||
#define DATA_MGR_DRAM_CFG (BASE_DATA_MGR + 0x0000)
|
||||
#define DATA_MGR_MEM_T_WL (BASE_DATA_MGR + 0x0004)
|
||||
#define DATA_MGR_MEM_T_ADD (BASE_DATA_MGR + 0x0008)
|
||||
#define DATA_MGR_MEM_T_RL (BASE_DATA_MGR + 0x000C)
|
||||
#define DATA_MGR_MEM_T_RFC (BASE_DATA_MGR + 0x0010)
|
||||
#define DATA_MGR_MEM_T_REFI (BASE_DATA_MGR + 0x0014)
|
||||
#define DATA_MGR_MEM_T_WR (BASE_DATA_MGR + 0x0018)
|
||||
#define DATA_MGR_MEM_T_MRD (BASE_DATA_MGR + 0x001C)
|
||||
#define DATA_MGR_COL_WIDTH (BASE_DATA_MGR + 0x0020)
|
||||
#define DATA_MGR_ROW_WIDTH (BASE_DATA_MGR + 0x0024)
|
||||
#define DATA_MGR_BANK_WIDTH (BASE_DATA_MGR + 0x0028)
|
||||
#define DATA_MGR_CS_WIDTH (BASE_DATA_MGR + 0x002C)
|
||||
#define DATA_MGR_ITF_WIDTH (BASE_DATA_MGR + 0x0030)
|
||||
#define DATA_MGR_DVC_WIDTH (BASE_DATA_MGR + 0x0034)
|
||||
#define DATA_MGR_DRAM_CFG (BASE_DATA_MGR + 0x0000)
|
||||
#define DATA_MGR_MEM_T_WL (BASE_DATA_MGR + 0x0004)
|
||||
#define DATA_MGR_MEM_T_ADD (BASE_DATA_MGR + 0x0008)
|
||||
#define DATA_MGR_MEM_T_RL (BASE_DATA_MGR + 0x000C)
|
||||
#define DATA_MGR_MEM_T_RFC (BASE_DATA_MGR + 0x0010)
|
||||
#define DATA_MGR_MEM_T_REFI (BASE_DATA_MGR + 0x0014)
|
||||
#define DATA_MGR_MEM_T_WR (BASE_DATA_MGR + 0x0018)
|
||||
#define DATA_MGR_MEM_T_MRD (BASE_DATA_MGR + 0x001C)
|
||||
#define DATA_MGR_COL_WIDTH (BASE_DATA_MGR + 0x0020)
|
||||
#define DATA_MGR_ROW_WIDTH (BASE_DATA_MGR + 0x0024)
|
||||
#define DATA_MGR_BANK_WIDTH (BASE_DATA_MGR + 0x0028)
|
||||
#define DATA_MGR_CS_WIDTH (BASE_DATA_MGR + 0x002C)
|
||||
#define DATA_MGR_ITF_WIDTH (BASE_DATA_MGR + 0x0030)
|
||||
#define DATA_MGR_DVC_WIDTH (BASE_DATA_MGR + 0x0034)
|
||||
|
||||
#define MEM_T_WL_ADD DATA_MGR_MEM_T_WL
|
||||
#define MEM_T_RL_ADD DATA_MGR_MEM_T_RL
|
||||
|
|
@ -253,114 +210,75 @@
|
|||
#define CALIB_SKIP_DELAY_LOOPS (1 << 0)
|
||||
#define CALIB_SKIP_ALL_BITS_CHK (1 << 1)
|
||||
#define CALIB_SKIP_DELAY_SWEEPS (1 << 2)
|
||||
#define CALIB_SKIP_VFIFO (1 << 3)
|
||||
#define CALIB_SKIP_LFIFO (1 << 4)
|
||||
#define CALIB_SKIP_WLEVEL (1 << 5)
|
||||
#define CALIB_SKIP_WRITES (1 << 6)
|
||||
#define CALIB_SKIP_VFIFO (1 << 3)
|
||||
#define CALIB_SKIP_LFIFO (1 << 4)
|
||||
#define CALIB_SKIP_WLEVEL (1 << 5)
|
||||
#define CALIB_SKIP_WRITES (1 << 6)
|
||||
#define CALIB_SKIP_FULL_TEST (1 << 7)
|
||||
#define CALIB_SKIP_ALL (CALIB_SKIP_VFIFO | \
|
||||
CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | \
|
||||
CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST)
|
||||
#define CALIB_SKIP_ALL (CALIB_SKIP_VFIFO | CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST)
|
||||
#define CALIB_IN_RTL_SIM (1 << 8)
|
||||
|
||||
/* Scan chain manager command addresses */
|
||||
|
||||
#define WRITE_SCC_DQS_IN_DELAY(group, delay) \
|
||||
IOWR_32DIRECT(SCC_MGR_DQS_IN_DELAY, (group) << 2, delay)
|
||||
#define WRITE_SCC_DQS_EN_DELAY(group, delay) \
|
||||
IOWR_32DIRECT(SCC_MGR_DQS_EN_DELAY, (group) << 2, (delay) \
|
||||
+ IO_DQS_EN_DELAY_OFFSET)
|
||||
#define WRITE_SCC_DQS_EN_PHASE(group, phase) \
|
||||
IOWR_32DIRECT(SCC_MGR_DQS_EN_PHASE, (group) << 2, phase)
|
||||
#define WRITE_SCC_DQDQS_OUT_PHASE(group, phase) \
|
||||
IOWR_32DIRECT(SCC_MGR_DQDQS_OUT_PHASE, (group) << 2, phase)
|
||||
#define WRITE_SCC_OCT_OUT1_DELAY(group, delay) \
|
||||
IOWR_32DIRECT(SCC_MGR_OCT_OUT1_DELAY, (group) << 2, delay)
|
||||
#define WRITE_SCC_DQS_IN_DELAY(group, delay) IOWR_32DIRECT(SCC_MGR_DQS_IN_DELAY, (group) << 2, delay)
|
||||
#define WRITE_SCC_DQS_EN_DELAY(group, delay) IOWR_32DIRECT(SCC_MGR_DQS_EN_DELAY, (group) << 2, (delay) + IO_DQS_EN_DELAY_OFFSET)
|
||||
#define WRITE_SCC_DQS_EN_PHASE(group, phase) IOWR_32DIRECT(SCC_MGR_DQS_EN_PHASE, (group) << 2, phase)
|
||||
#define WRITE_SCC_DQDQS_OUT_PHASE(group, phase) IOWR_32DIRECT(SCC_MGR_DQDQS_OUT_PHASE, (group) << 2, phase)
|
||||
#define WRITE_SCC_OCT_OUT1_DELAY(group, delay) IOWR_32DIRECT(SCC_MGR_OCT_OUT1_DELAY, (group) << 2, delay)
|
||||
#define WRITE_SCC_OCT_OUT2_DELAY(group, delay)
|
||||
#define WRITE_SCC_DQS_BYPASS(group, bypass)
|
||||
|
||||
#define WRITE_SCC_DQ_OUT1_DELAY(pin, delay) \
|
||||
IOWR_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (pin) << 2, delay)
|
||||
#define WRITE_SCC_DQ_OUT1_DELAY(pin, delay) IOWR_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (pin) << 2, delay)
|
||||
|
||||
#define WRITE_SCC_DQ_OUT2_DELAY(pin, delay)
|
||||
|
||||
#define WRITE_SCC_DQ_IN_DELAY(pin, delay) \
|
||||
IOWR_32DIRECT(SCC_MGR_IO_IN_DELAY, (pin) << 2, delay)
|
||||
#define WRITE_SCC_DQ_IN_DELAY(pin, delay) IOWR_32DIRECT(SCC_MGR_IO_IN_DELAY, (pin) << 2, delay)
|
||||
|
||||
#define WRITE_SCC_DQ_BYPASS(pin, bypass)
|
||||
|
||||
#define WRITE_SCC_RFIFO_MODE(pin, mode)
|
||||
|
||||
#define WRITE_SCC_HHP_EXTRAS(value) \
|
||||
IOWR_32DIRECT(SCC_MGR_HHP_GLOBALS, SCC_MGR_HHP_EXTRAS_OFFSET, value)
|
||||
#define WRITE_SCC_HHP_DQSE_MAP(value) \
|
||||
IOWR_32DIRECT(SCC_MGR_HHP_GLOBALS, SCC_MGR_HHP_DQSE_MAP_OFFSET, value)
|
||||
#define WRITE_SCC_HHP_EXTRAS(value) IOWR_32DIRECT(SCC_MGR_HHP_GLOBALS, SCC_MGR_HHP_EXTRAS_OFFSET, value)
|
||||
#define WRITE_SCC_HHP_DQSE_MAP(value) IOWR_32DIRECT(SCC_MGR_HHP_GLOBALS, SCC_MGR_HHP_DQSE_MAP_OFFSET, value)
|
||||
|
||||
#define WRITE_SCC_DQS_IO_OUT1_DELAY(delay) \
|
||||
IOWR_32DIRECT(SCC_MGR_IO_OUT1_DELAY, \
|
||||
(RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2, delay)
|
||||
#define WRITE_SCC_DQS_IO_OUT1_DELAY(delay) IOWR_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2, delay)
|
||||
|
||||
#define WRITE_SCC_DQS_IO_OUT2_DELAY(delay)
|
||||
|
||||
#define WRITE_SCC_DQS_IO_IN_DELAY(delay) \
|
||||
IOWR_32DIRECT(SCC_MGR_IO_IN_DELAY, \
|
||||
(RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2, delay)
|
||||
#define WRITE_SCC_DQS_IO_IN_DELAY(delay) IOWR_32DIRECT(SCC_MGR_IO_IN_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2, delay)
|
||||
|
||||
#define WRITE_SCC_DM_IO_OUT1_DELAY(pin, delay) \
|
||||
IOWR_32DIRECT(SCC_MGR_IO_OUT1_DELAY, \
|
||||
(RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2, delay)
|
||||
#define WRITE_SCC_DM_IO_OUT1_DELAY(pin, delay) IOWR_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2, delay)
|
||||
|
||||
#define WRITE_SCC_DM_IO_OUT2_DELAY(pin, delay)
|
||||
|
||||
#define WRITE_SCC_DM_IO_IN_DELAY(pin, delay) \
|
||||
IOWR_32DIRECT(SCC_MGR_IO_IN_DELAY, \
|
||||
(RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2, delay)
|
||||
#define WRITE_SCC_DM_IO_IN_DELAY(pin, delay) IOWR_32DIRECT(SCC_MGR_IO_IN_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2, delay)
|
||||
|
||||
#define WRITE_SCC_DM_BYPASS(pin, bypass)
|
||||
|
||||
#define READ_SCC_DQS_IN_DELAY(group) \
|
||||
IORD_32DIRECT(SCC_MGR_DQS_IN_DELAY, (group) << 2)
|
||||
#define READ_SCC_DQS_EN_DELAY(group) \
|
||||
(IORD_32DIRECT(SCC_MGR_DQS_EN_DELAY, (group) << 2) \
|
||||
- IO_DQS_EN_DELAY_OFFSET)
|
||||
#define READ_SCC_DQS_EN_PHASE(group) \
|
||||
IORD_32DIRECT(SCC_MGR_DQS_EN_PHASE, (group) << 2)
|
||||
#define READ_SCC_DQDQS_OUT_PHASE(group) \
|
||||
IORD_32DIRECT(SCC_MGR_DQDQS_OUT_PHASE, (group) << 2)
|
||||
#define READ_SCC_OCT_OUT1_DELAY(group) \
|
||||
IORD_32DIRECT(SCC_MGR_OCT_OUT1_DELAY, \
|
||||
(group * RW_MGR_MEM_IF_READ_DQS_WIDTH / \
|
||||
RW_MGR_MEM_IF_WRITE_DQS_WIDTH) << 2)
|
||||
#define READ_SCC_DQS_IN_DELAY(group) IORD_32DIRECT(SCC_MGR_DQS_IN_DELAY, (group) << 2)
|
||||
#define READ_SCC_DQS_EN_DELAY(group) (IORD_32DIRECT(SCC_MGR_DQS_EN_DELAY, (group) << 2) - IO_DQS_EN_DELAY_OFFSET)
|
||||
#define READ_SCC_DQS_EN_PHASE(group) IORD_32DIRECT(SCC_MGR_DQS_EN_PHASE, (group) << 2)
|
||||
#define READ_SCC_DQDQS_OUT_PHASE(group) IORD_32DIRECT(SCC_MGR_DQDQS_OUT_PHASE, (group) << 2)
|
||||
#define READ_SCC_OCT_OUT1_DELAY(group) IORD_32DIRECT(SCC_MGR_OCT_OUT1_DELAY, (group * RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH) << 2)
|
||||
#define READ_SCC_OCT_OUT2_DELAY(group) 0
|
||||
#define READ_SCC_DQS_BYPASS(group) 0
|
||||
#define READ_SCC_DQS_BYPASS(group) 0
|
||||
|
||||
#define READ_SCC_DQ_OUT1_DELAY(pin) \
|
||||
IORD_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (pin) << 2)
|
||||
#define READ_SCC_DQ_OUT1_DELAY(pin) IORD_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (pin) << 2)
|
||||
#define READ_SCC_DQ_OUT2_DELAY(pin) 0
|
||||
#define READ_SCC_DQ_IN_DELAY(pin) \
|
||||
IORD_32DIRECT(SCC_MGR_IO_IN_DELAY, (pin) << 2)
|
||||
#define READ_SCC_DQ_IN_DELAY(pin) IORD_32DIRECT(SCC_MGR_IO_IN_DELAY, (pin) << 2)
|
||||
#define READ_SCC_DQ_BYPASS(pin) 0
|
||||
#define READ_SCC_RFIFO_MODE(pin) 0
|
||||
|
||||
#define READ_SCC_DQS_IO_OUT1_DELAY() \
|
||||
IORD_32DIRECT(SCC_MGR_IO_OUT1_DELAY, \
|
||||
(RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2)
|
||||
#define READ_SCC_DQS_IO_OUT1_DELAY() IORD_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2)
|
||||
#define READ_SCC_DQS_IO_OUT2_DELAY() 0
|
||||
#define READ_SCC_DQS_IO_IN_DELAY() \
|
||||
IORD_32DIRECT(SCC_MGR_IO_IN_DELAY, \
|
||||
(RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2)
|
||||
#define READ_SCC_DQS_IO_IN_DELAY() IORD_32DIRECT(SCC_MGR_IO_IN_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2)
|
||||
|
||||
#define READ_SCC_DM_IO_OUT1_DELAY(pin) \
|
||||
IORD_32DIRECT(SCC_MGR_IO_OUT1_DELAY, \
|
||||
(RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2)
|
||||
#define READ_SCC_DM_IO_OUT1_DELAY(pin) IORD_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2)
|
||||
#define READ_SCC_DM_IO_OUT2_DELAY(pin) 0
|
||||
#define READ_SCC_DM_IO_IN_DELAY(pin) \
|
||||
IORD_32DIRECT(SCC_MGR_IO_IN_DELAY, \
|
||||
(RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2)
|
||||
#define READ_SCC_DM_IO_IN_DELAY(pin) IORD_32DIRECT(SCC_MGR_IO_IN_DELAY, (RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2)
|
||||
#define READ_SCC_DM_BYPASS(pin) 0
|
||||
|
||||
|
||||
#define SCC_MGR_GROUP_COUNTER (BASE_SCC_MGR + 0x0000)
|
||||
#define SCC_MGR_DQS_IN_DELAY (BASE_SCC_MGR + 0x0100)
|
||||
#define SCC_MGR_DQS_EN_PHASE (BASE_SCC_MGR + 0x0200)
|
||||
|
|
@ -368,28 +286,27 @@
|
|||
#define SCC_MGR_DQDQS_OUT_PHASE (BASE_SCC_MGR + 0x0400)
|
||||
#define SCC_MGR_OCT_OUT1_DELAY (BASE_SCC_MGR + 0x0500)
|
||||
#define SCC_MGR_IO_OUT1_DELAY (BASE_SCC_MGR + 0x0700)
|
||||
#define SCC_MGR_IO_IN_DELAY (BASE_SCC_MGR + 0x0900)
|
||||
|
||||
#define SCC_MGR_IO_IN_DELAY (BASE_SCC_MGR + 0x0900)
|
||||
|
||||
/* HHP-HPS-specific versions of some commands */
|
||||
#define SCC_MGR_DQS_EN_DELAY_GATE (BASE_SCC_MGR + 0x0600)
|
||||
#define SCC_MGR_IO_OE_DELAY (BASE_SCC_MGR + 0x0800)
|
||||
#define SCC_MGR_HHP_GLOBALS (BASE_SCC_MGR + 0x0A00)
|
||||
#define SCC_MGR_HHP_RFILE (BASE_SCC_MGR + 0x0B00)
|
||||
#define SCC_MGR_HHP_GLOBALS (BASE_SCC_MGR + 0x0A00)
|
||||
#define SCC_MGR_HHP_RFILE (BASE_SCC_MGR + 0x0B00)
|
||||
|
||||
/* HHP-HPS-specific values */
|
||||
#define SCC_MGR_HHP_EXTRAS_OFFSET 0
|
||||
#define SCC_MGR_HHP_DQSE_MAP_OFFSET 1
|
||||
|
||||
#define SCC_MGR_DQS_ENA (BASE_SCC_MGR + 0x0E00)
|
||||
#define SCC_MGR_DQS_IO_ENA (BASE_SCC_MGR + 0x0E04)
|
||||
#define SCC_MGR_DQ_ENA (BASE_SCC_MGR + 0x0E08)
|
||||
#define SCC_MGR_DM_ENA (BASE_SCC_MGR + 0x0E0C)
|
||||
#define SCC_MGR_UPD (BASE_SCC_MGR + 0x0E20)
|
||||
#define SCC_MGR_ACTIVE_RANK (BASE_SCC_MGR + 0x0E40)
|
||||
#define SCC_MGR_DQS_ENA (BASE_SCC_MGR + 0x0E00)
|
||||
#define SCC_MGR_DQS_IO_ENA (BASE_SCC_MGR + 0x0E04)
|
||||
#define SCC_MGR_DQ_ENA (BASE_SCC_MGR + 0x0E08)
|
||||
#define SCC_MGR_DM_ENA (BASE_SCC_MGR + 0x0E0C)
|
||||
#define SCC_MGR_UPD (BASE_SCC_MGR + 0x0E20)
|
||||
#define SCC_MGR_ACTIVE_RANK (BASE_SCC_MGR + 0x0E40)
|
||||
#define SCC_MGR_AFI_CAL_INIT (BASE_SCC_MGR + 0x0D00)
|
||||
|
||||
/* PHY Debug mode flag constants */
|
||||
// PHY Debug mode flag constants
|
||||
#define PHY_DEBUG_IN_DEBUG_MODE 0x00000001
|
||||
#define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002
|
||||
#define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004
|
||||
|
|
@ -397,46 +314,44 @@
|
|||
#define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010
|
||||
#define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020
|
||||
|
||||
/* Init and Reset delay constants - Only use if defined by sequencer_defines.h,
|
||||
* otherwise, revert to defaults
|
||||
* Default for Tinit = (0+1) * ((202+1) * (2 * 131 + 1) + 1) = 53532 = 200.75us @ 266MHz
|
||||
*/
|
||||
// Init and Reset delay constants - Only use if defined by sequencer_defines.h,
|
||||
// otherwise, revert to defaults
|
||||
// Default for Tinit = (0+1) * ((202+1) * (2 * 131 + 1) + 1) = 53532 = 200.75us @ 266MHz
|
||||
#ifdef TINIT_CNTR0_VAL
|
||||
#define SEQ_TINIT_CNTR0_VAL TINIT_CNTR0_VAL
|
||||
#define SEQ_TINIT_CNTR0_VAL TINIT_CNTR0_VAL
|
||||
#else
|
||||
#define SEQ_TINIT_CNTR0_VAL 0
|
||||
#define SEQ_TINIT_CNTR0_VAL 0
|
||||
#endif
|
||||
|
||||
#ifdef TINIT_CNTR1_VAL
|
||||
#define SEQ_TINIT_CNTR1_VAL TINIT_CNTR1_VAL
|
||||
#define SEQ_TINIT_CNTR1_VAL TINIT_CNTR1_VAL
|
||||
#else
|
||||
#define SEQ_TINIT_CNTR1_VAL 202
|
||||
#define SEQ_TINIT_CNTR1_VAL 202
|
||||
#endif
|
||||
|
||||
#ifdef TINIT_CNTR2_VAL
|
||||
#define SEQ_TINIT_CNTR2_VAL TINIT_CNTR2_VAL
|
||||
#define SEQ_TINIT_CNTR2_VAL TINIT_CNTR2_VAL
|
||||
#else
|
||||
#define SEQ_TINIT_CNTR2_VAL 131
|
||||
#define SEQ_TINIT_CNTR2_VAL 131
|
||||
#endif
|
||||
|
||||
|
||||
/* Default for Treset = (2+1) * ((252+1) * (2 * 131 + 1) + 1) = 133563 = 500.86us @ 266MHz */
|
||||
// Default for Treset = (2+1) * ((252+1) * (2 * 131 + 1) + 1) = 133563 = 500.86us @ 266MHz
|
||||
#ifdef TRESET_CNTR0_VAL
|
||||
#define SEQ_TRESET_CNTR0_VAL TRESET_CNTR0_VAL
|
||||
#define SEQ_TRESET_CNTR0_VAL TRESET_CNTR0_VAL
|
||||
#else
|
||||
#define SEQ_TRESET_CNTR0_VAL 2
|
||||
#define SEQ_TRESET_CNTR0_VAL 2
|
||||
#endif
|
||||
|
||||
#ifdef TRESET_CNTR1_VAL
|
||||
#define SEQ_TRESET_CNTR1_VAL TRESET_CNTR1_VAL
|
||||
#define SEQ_TRESET_CNTR1_VAL TRESET_CNTR1_VAL
|
||||
#else
|
||||
#define SEQ_TRESET_CNTR1_VAL 252
|
||||
#define SEQ_TRESET_CNTR1_VAL 252
|
||||
#endif
|
||||
|
||||
#ifdef TRESET_CNTR2_VAL
|
||||
#define SEQ_TRESET_CNTR2_VAL TRESET_CNTR2_VAL
|
||||
#define SEQ_TRESET_CNTR2_VAL TRESET_CNTR2_VAL
|
||||
#else
|
||||
#define SEQ_TRESET_CNTR2_VAL 131
|
||||
#define SEQ_TRESET_CNTR2_VAL 131
|
||||
#endif
|
||||
|
||||
/* Bitfield type changes depending on protocol */
|
||||
|
|
@ -445,18 +360,32 @@ typedef uint32_t t_btfld;
|
|||
#define RW_MGR_INST_ROM_WRITE BASE_RW_MGR + 0x1800
|
||||
#define RW_MGR_AC_ROM_WRITE BASE_RW_MGR + 0x1C00
|
||||
|
||||
static const uint32_t inst_rom_init_size;
|
||||
static const uint32_t inst_rom_init[];
|
||||
static const uint32_t ac_rom_init_size;
|
||||
static const uint32_t ac_rom_init[];
|
||||
|
||||
/* parameter variable holder */
|
||||
|
||||
typedef struct param_type {
|
||||
t_btfld dm_correct_mask;
|
||||
t_btfld read_correct_mask;
|
||||
t_btfld read_correct_mask_vg;
|
||||
t_btfld write_correct_mask;
|
||||
t_btfld write_correct_mask_vg;
|
||||
|
||||
/* set a particular entry to 1 if we need to skip a particular rank */
|
||||
|
||||
uint32_t skip_ranks[MAX_RANKS];
|
||||
uint32_t skip_groups;
|
||||
uint32_t skip_shadow_regs[NUM_SHADOW_REGS];
|
||||
|
||||
/* set a particular entry to 1 if we need to skip a particular group */
|
||||
|
||||
uint32_t skip_groups;
|
||||
|
||||
/* set a particular entry to 1 if the shadow register (which represents a set of ranks) needs to be skipped */
|
||||
|
||||
uint32_t skip_shadow_regs[NUM_SHADOW_REGS];
|
||||
|
||||
} param_t;
|
||||
|
||||
/* global variable holder */
|
||||
|
|
@ -484,11 +413,33 @@ typedef struct gbl_type {
|
|||
uint32_t fom_in;
|
||||
uint32_t fom_out;
|
||||
|
||||
/*USER Number of RW Mgr NOP cycles between
|
||||
write command and write data */
|
||||
#if MULTIPLE_AFI_WLAT
|
||||
uint32_t rw_wl_nop_cycles_per_group[RW_MGR_MEM_IF_WRITE_DQS_WIDTH];
|
||||
#endif
|
||||
//USER Number of RW Mgr NOP cycles between write command and write data
|
||||
uint32_t rw_wl_nop_cycles;
|
||||
} gbl_t;
|
||||
|
||||
// External global variables
|
||||
static gbl_t *gbl;
|
||||
static param_t *param;
|
||||
|
||||
// External functions
|
||||
static uint32_t run_mem_calibrate(void);
|
||||
static void rw_mgr_mem_initialize(void);
|
||||
static void rw_mgr_mem_dll_lock_wait(void);
|
||||
static inline void scc_mgr_set_dq_in_delay(uint32_t write_group, uint32_t dq_in_group,
|
||||
uint32_t delay);
|
||||
static inline void scc_mgr_set_dq_out1_delay(uint32_t write_group, uint32_t dq_in_group,
|
||||
uint32_t delay);
|
||||
static inline void scc_mgr_set_dq_out2_delay(uint32_t write_group, uint32_t dq_in_group,
|
||||
uint32_t delay);
|
||||
static inline void scc_mgr_load_dq(uint32_t dq_in_group);
|
||||
static inline void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay);
|
||||
static inline void scc_mgr_load_dqs(uint32_t dqs);
|
||||
static void scc_mgr_set_group_dqs_io_and_oct_out1_gradual(uint32_t write_group, uint32_t delay);
|
||||
static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group, uint32_t delay);
|
||||
static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group, uint32_t phase);
|
||||
static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group, uint32_t phase);
|
||||
static inline void scc_mgr_set_dm_out1_delay(uint32_t write_group, uint32_t dm, uint32_t delay);
|
||||
static inline void scc_mgr_set_dm_out2_delay(uint32_t write_group, uint32_t dm, uint32_t delay);
|
||||
static inline void scc_mgr_load_dm(uint32_t dm);
|
||||
int sdram_calibration(void);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,6 @@
|
|||
#define TINIT_CNTR1_VAL 32
|
||||
#define TINIT_CNTR2_VAL 32
|
||||
#define TINIT_CNTR0_VAL 99
|
||||
#define TRESET_CNTR1_VAL 99
|
||||
#define TRESET_CNTR2_VAL 10
|
||||
#define TRESET_CNTR0_VAL 99
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* Copyright Altera Corporation (C) 2012-2014. All rights reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Altera Corporation nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#define SEQUENCER_DATA_MGR_INST_BASE 0x60000
|
||||
#define SEQUENCER_PHY_MGR_INST_BASE 0x48000
|
||||
#define SEQUENCER_PTR_MGR_INST_BASE 0x40000
|
||||
#define SEQUENCER_RAM_BASE 0x20000
|
||||
#define SEQUENCER_ROM_BASE 0x10000
|
||||
#define SEQUENCER_RW_MGR_INST_BASE 0x50000
|
||||
#define SEQUENCER_SCC_MGR_INST_BASE 0x58000
|
||||
#define SEQUENCER_REG_FILE_INST_BASE 0x70000
|
||||
#define SEQUENCER_TIMER_INST_BASE 0x78000
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
#ifndef TCLRPT_H_
|
||||
#define TCLRPT_H_
|
||||
/*
|
||||
* Copyright Altera Corporation (C) 2012-2014. All rights reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Altera Corporation nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "sequencer.h"
|
||||
|
||||
#define TCLRPT_SET(item, value)
|
||||
|
||||
// None of the rest of the file should be referenced if ENABLE_TCL_DEBUG is not
|
||||
// set (although it's not a problem if it is, but this helps catch errors)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
#!/bin/bash
|
||||
|
||||
if [ "$#" -lt "2" ]
|
||||
then
|
||||
echo "USAGE: $0 <UBOOT-SRC> <SEQUENCER_DEFINES>"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ubootsrc=$1
|
||||
sequencer_defines=$2
|
||||
bareboxsrc=.
|
||||
|
||||
cd ${bareboxsrc}
|
||||
|
||||
copy_source() {
|
||||
local src
|
||||
local tgt
|
||||
src=$1
|
||||
tgt=$2
|
||||
|
||||
echo "Merging source code $src to $tgt"
|
||||
|
||||
cp $src $tgt
|
||||
|
||||
unifdef -f ${sequencer_defines} $tgt -o $tgt
|
||||
|
||||
echo " Fixing extern/static keywords..."
|
||||
# Statify all global variables with missing static keyword
|
||||
sed -i 's/^\(extern \|static \|\)\([^*#\/ ][^(]* [^( ]*\((.*).*$\|=.*;.*$\)\)/static \2/g' $tgt
|
||||
sed -i 's/^extern /static /g' $tgt
|
||||
|
||||
echo " Translating altera int types..."
|
||||
# Replace altera types
|
||||
sed -i 's/alt_u32/uint32_t/g' $tgt
|
||||
sed -i 's/alt_u16/uint16_t/g' $tgt
|
||||
sed -i 's/alt_16/int16_t/g' $tgt
|
||||
sed -i 's/alt_32/int32_t/g' $tgt
|
||||
sed -i 's/alt_u8/uint8_t/g' $tgt
|
||||
sed -i 's/alt_8/int8_t/g' $tgt
|
||||
sed -i 's/#include "alt_types.h"//g' $tgt
|
||||
|
||||
echo " Fixing include pathes..."
|
||||
# Fix include pathes
|
||||
sed -i 's/#include <sdram.h>/#include <mach\/sdram.h>/g' $tgt
|
||||
sed -i 's/#include "sequencer_auto.h"//g' $tgt
|
||||
|
||||
echo " Automated readability fixup..."
|
||||
indent -npro -kr -i8 -ts8 -sob -l100 -ss -ncs -cp1 -il0 $tgt
|
||||
}
|
||||
|
||||
copy_source ${ubootsrc}/board/altera/socfpga/sdram/sequencer.c arch/arm/mach-socfpga/include/mach/sequencer.c
|
||||
sed -i 's/static int sdram_calibration(void)/static int socfpga_mem_calibration(void)/g' arch/arm/mach-socfpga/include/mach/sequencer.c
|
||||
|
||||
cat <<'EOF' > arch/arm/mach-socfpga/include/mach/sequencer_defines.h
|
||||
#define TINIT_CNTR1_VAL 32
|
||||
#define TINIT_CNTR2_VAL 32
|
||||
#define TINIT_CNTR0_VAL 99
|
||||
#define TRESET_CNTR1_VAL 99
|
||||
#define TRESET_CNTR2_VAL 10
|
||||
#define TRESET_CNTR0_VAL 99
|
||||
EOF
|
||||
|
||||
copy_source ${ubootsrc}/board/altera/socfpga/sdram/sequencer.h arch/arm/mach-socfpga/include/mach/sequencer.h
|
||||
copy_source ${ubootsrc}/board/altera/socfpga/sdram/tclrpt.h arch/arm/mach-socfpga/include/mach/tclrpt.h
|
||||
copy_source ${ubootsrc}/board/altera/socfpga/sdram/sdram_io.h arch/arm/mach-socfpga/include/mach/sdram_io.h
|
||||
cat <<'EOF' >> arch/arm/mach-socfpga/include/mach/sdram_io.h
|
||||
#define write_register(BASE, OFFSET, DATA) \
|
||||
writel(DATA, ((BASE) + (OFFSET)))
|
||||
#define read_register(BASE, OFFSET) \
|
||||
readl((BASE) + (OFFSET))
|
||||
#define HPS_SDR_BASE 0xffc20000
|
||||
EOF
|
||||
copy_source ${ubootsrc}/board/altera/socfpga/sdram/system.h arch/arm/mach-socfpga/include/mach/system.h
|
||||
|
||||
#unifdef -f ${sequencer_defines} ${ubootsrc}/board/altera/socfpga/sdram/tclrpt.c -o arch/arm/mach-socfpga/include/mach/tclrpt.c
|
||||
|
||||
echo "DONE"
|
||||
|
||||
|
|
@ -0,0 +1,144 @@
|
|||
/*
|
||||
Copyright (c) 2012, Altera Corporation
|
||||
All rights reserved.
|
||||
|
||||
SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
* Neither the name of Altera Corporation nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#define ENABLE_SWEEP_ALL_GROUPS 0
|
||||
#define ENABLE_DQSEN_SWEEP 0
|
||||
#define STATIC_QUICK_CALIBRATION 0
|
||||
#define DYNAMIC_CALIBRATION_MODE 0
|
||||
#define DISABLE_GUARANTEED_READ 0
|
||||
|
||||
#define ARRIAVGZ 0
|
||||
#define ARRIAV 0
|
||||
#define AVL_CLK_FREQ 67
|
||||
#define BFM_MODE 0
|
||||
#define BURST2 0
|
||||
#define CALIBRATE_BIT_SLIPS 0
|
||||
#define CALIB_LFIFO_OFFSET 8
|
||||
#define CALIB_VFIFO_OFFSET 6
|
||||
#define CYCLONEV 1
|
||||
#define DDR2 0
|
||||
#define DDR3 1
|
||||
#define DDRX 1
|
||||
#define DM_PINS_ENABLED 1
|
||||
#define ENABLE_ASSERT 0
|
||||
#define ENABLE_PRINTF_LOG 0
|
||||
#define ENABLE_BRINGUP_DEBUGGING 0
|
||||
#define ENABLE_DELAY_CHAIN_WRITE 0
|
||||
#define ENABLE_DQS_IN_CENTERING 1
|
||||
#define ENABLE_DQS_OUT_CENTERING 0
|
||||
#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0
|
||||
#define ENABLE_INST_ROM_WRITE 1
|
||||
#define ENABLE_MARGIN_REPORT_GEN 0
|
||||
#define ENABLE_NON_DESTRUCTIVE_CALIB 0
|
||||
#define ENABLE_SUPER_QUICK_CALIBRATION 0
|
||||
#define ENABLE_TCL_DEBUG 0
|
||||
#define FAKE_CAL_FAIL 0
|
||||
#define FULL_RATE 1
|
||||
#define GUARANTEED_READ_BRINGUP_TEST 0
|
||||
#define HALF_RATE 0
|
||||
#define HARD_PHY 1
|
||||
#define HARD_VFIFO 1
|
||||
#define HCX_COMPAT_MODE 0
|
||||
#define HHP_HPS_SIMULATION 0
|
||||
#define HHP_HPS_VERIFICATION 0
|
||||
#define HHP_HPS 1
|
||||
#define HPS_HW 1
|
||||
#define HR_DDIO_OUT_HAS_THREE_REGS 0
|
||||
#define IO_DELAY_PER_DCHAIN_TAP 25
|
||||
#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
|
||||
#define IO_DELAY_PER_OPA_TAP 312
|
||||
#define IO_DLL_CHAIN_LENGTH 8
|
||||
#define IO_DM_OUT_RESERVE 0
|
||||
#define IO_DQDQS_OUT_PHASE_MAX 0
|
||||
#define IO_DQS_EN_DELAY_MAX 31
|
||||
#define IO_DQS_EN_DELAY_OFFSET 0
|
||||
#define IO_DQS_EN_PHASE_MAX 7
|
||||
#define IO_DQS_IN_DELAY_MAX 31
|
||||
#define IO_DQS_IN_RESERVE 4
|
||||
#define IO_DQS_OUT_RESERVE 4
|
||||
#define IO_DQ_OUT_RESERVE 0
|
||||
#define IO_IO_IN_DELAY_MAX 31
|
||||
#define IO_IO_OUT1_DELAY_MAX 31
|
||||
#define IO_IO_OUT2_DELAY_MAX 0
|
||||
#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
|
||||
#define LPDDR1 0
|
||||
#define LPDDR2 0
|
||||
#define LRDIMM 0
|
||||
#define M10_DQ_WIDTH_8 0
|
||||
#define M10_DQ_WIDTH_16 0
|
||||
#define M10_DQ_WIDTH_24 0
|
||||
#define MARGIN_VARIATION_TEST 0
|
||||
#define MAX_LATENCY_COUNT_WIDTH 5
|
||||
#define MEM_ADDR_WIDTH 13
|
||||
#define MRS_MIRROR_PING_PONG_ATSO 0
|
||||
#define MULTIPLE_AFI_WLAT 0
|
||||
#define NUM_SHADOW_REGS 1
|
||||
#define QDRII 0
|
||||
#define QUARTER_RATE 0
|
||||
#define RDIMM 0
|
||||
#define READ_AFTER_WRITE_CALIBRATION 1
|
||||
#define READ_VALID_FIFO_SIZE 16
|
||||
#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c
|
||||
#define RLDRAM3 0
|
||||
#define RLDRAMII 0
|
||||
#define RLDRAMX 0
|
||||
#define RUNTIME_CAL_REPORT 0
|
||||
#define RW_MGR_MEM_ADDRESS_MIRRORING 0
|
||||
#define RW_MGR_MEM_ADDRESS_WIDTH 15
|
||||
#define RW_MGR_MEM_BANK_WIDTH 3
|
||||
#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1
|
||||
#define RW_MGR_MEM_CLK_EN_WIDTH 1
|
||||
#define RW_MGR_MEM_CONTROL_WIDTH 1
|
||||
#define RW_MGR_MEM_DATA_MASK_WIDTH 4
|
||||
#define RW_MGR_MEM_DATA_WIDTH 32
|
||||
#define RW_MGR_MEM_DQ_PER_READ_DQS 8
|
||||
#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
|
||||
#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
|
||||
#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
|
||||
#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
|
||||
#define RW_MGR_MEM_NUMBER_OF_RANKS 1
|
||||
#define RW_MGR_MEM_ODT_WIDTH 1
|
||||
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
|
||||
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
|
||||
#define RW_MGR_MR0_BL 1
|
||||
#define RW_MGR_MR0_CAS_LATENCY 3
|
||||
#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
|
||||
#define RW_MGR_WRITE_TO_DEBUG_READ 1.0
|
||||
#define SKEW_CALIBRATION 0
|
||||
#define STATIC_FULL_CALIBRATION 1
|
||||
#define STATIC_SIM_FILESET 0
|
||||
#define STATIC_SKIP_MEM_INIT 0
|
||||
#define STRATIXV 0
|
||||
#define TRACKING_ERROR_TEST 0
|
||||
#define TRACKING_WATCH_TEST 0
|
||||
#define TW0_CAPTURE_CLOCKS 0
|
||||
#define USE_DQS_TRACKING 1
|
||||
#define USE_SHADOW_REGS 0
|
||||
#define USE_USER_RDIMM_VALUE 0
|
||||
|
||||
Loading…
Reference in New Issue