arm: davinci: add dm644x clock and PSC support
This commit is contained in:
Jan Luebbe
parent
e90c4f9435
commit
3655aaa952
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@ -67,6 +67,8 @@ config ARCH_CLPS711X
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config ARCH_DAVINCI
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bool "TI Davinci"
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select CPU_ARM926T
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select CLKDEV_LOOKUP
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select HAVE_CLK
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select HAS_DEBUG_LL
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select GPIOLIB
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@ -4,6 +4,9 @@ config ARCH_TEXT_BASE
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hex
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default 0x82000000
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config ARCH_DAVINCI_DM644x
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bool
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choice
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prompt "Davinci Board type"
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@ -1 +1,2 @@
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obj-y += time.o
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obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o common.o clock.o psc.o
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@ -0,0 +1,577 @@
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/*
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* Clock and PLL control for DaVinci devices
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*
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* Copyright (C) 2006-2007 Texas Instruments.
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* Copyright (C) 2008-2009 Deep Root Systems, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <common.h>
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#include <io.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/sizes.h>
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#include <linux/clk.h>
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#include <mach/psc.h>
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#include "clock.h"
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static LIST_HEAD(clocks);
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static void __clk_enable(struct clk *clk)
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{
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if (clk->parent)
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__clk_enable(clk->parent);
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if (clk->usecount++ == 0) {
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if (clk->flags & CLK_PSC)
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davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
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true, clk->flags);
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else if (clk->clk_enable)
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if (clk->clk_enable)
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clk->clk_enable(clk);
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}
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}
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static void __clk_disable(struct clk *clk)
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{
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if (WARN_ON(clk->usecount == 0))
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return;
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if (--clk->usecount == 0) {
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if (!(clk->flags & CLK_PLL) && (clk->flags & CLK_PSC))
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davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
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false, clk->flags);
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else if (clk->clk_disable)
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if (clk->clk_disable)
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clk->clk_disable(clk);
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}
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if (clk->parent)
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__clk_disable(clk->parent);
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}
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int davinci_clk_reset(struct clk *clk, bool reset)
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{
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unsigned long flags;
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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if (clk->flags & CLK_PSC)
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davinci_psc_reset(clk->gpsc, clk->lpsc, reset);
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return 0;
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}
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EXPORT_SYMBOL(davinci_clk_reset);
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int davinci_clk_reset_assert(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk) || !clk->reset)
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return -EINVAL;
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return clk->reset(clk, true);
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}
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EXPORT_SYMBOL(davinci_clk_reset_assert);
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int davinci_clk_reset_deassert(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk) || !clk->reset)
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return -EINVAL;
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return clk->reset(clk, false);
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}
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EXPORT_SYMBOL(davinci_clk_reset_deassert);
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int clk_enable(struct clk *clk)
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{
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unsigned long flags;
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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__clk_enable(clk);
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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unsigned long flags;
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if (clk == NULL || IS_ERR(clk))
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return;
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__clk_disable(clk);
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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return clk->rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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#if 0
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long clk_round_rate(struct clk *clk, unsigned long rate)
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{
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if (clk == NULL || IS_ERR(clk))
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return 0;
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if (clk->round_rate)
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return clk->round_rate(clk, rate);
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return clk->rate;
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}
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EXPORT_SYMBOL(clk_round_rate);
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#endif
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/* Propagate rate to children */
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static void propagate_rate(struct clk *root)
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{
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struct clk *clk;
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list_for_each_entry(clk, &root->children, childnode) {
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if (clk->recalc)
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clk->rate = clk->recalc(clk);
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propagate_rate(clk);
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}
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}
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#if 0
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long flags;
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int ret = -EINVAL;
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if (clk == NULL || IS_ERR(clk))
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return ret;
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if (clk->set_rate)
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ret = clk->set_rate(clk, rate);
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if (ret == 0) {
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if (clk->recalc)
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clk->rate = clk->recalc(clk);
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propagate_rate(clk);
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}
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return ret;
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}
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EXPORT_SYMBOL(clk_set_rate);
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#endif
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int clk_set_parent(struct clk *clk, struct clk *parent)
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{
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unsigned long flags;
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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/* Cannot change parent on enabled clock */
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if (WARN_ON(clk->usecount))
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return -EINVAL;
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clk->parent = parent;
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list_del_init(&clk->childnode);
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list_add(&clk->childnode, &clk->parent->children);
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if (clk->recalc)
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clk->rate = clk->recalc(clk);
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propagate_rate(clk);
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return 0;
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}
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EXPORT_SYMBOL(clk_set_parent);
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int clk_register(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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if (WARN(clk->parent && !clk->parent->rate,
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"CLK: %s parent %s has no rate!\n",
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clk->name, clk->parent->name))
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return -EINVAL;
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INIT_LIST_HEAD(&clk->children);
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list_add_tail(&clk->node, &clocks);
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if (clk->parent)
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list_add_tail(&clk->childnode, &clk->parent->children);
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/* If rate is already set, use it */
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if (clk->rate)
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return 0;
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/* Else, see if there is a way to calculate it */
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if (clk->recalc)
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clk->rate = clk->recalc(clk);
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/* Otherwise, default to parent rate */
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else if (clk->parent)
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clk->rate = clk->parent->rate;
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return 0;
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}
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EXPORT_SYMBOL(clk_register);
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void clk_unregister(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk))
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return;
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list_del(&clk->node);
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list_del(&clk->childnode);
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}
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EXPORT_SYMBOL(clk_unregister);
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static unsigned long clk_sysclk_recalc(struct clk *clk)
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{
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u32 v, plldiv;
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struct pll_data *pll;
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unsigned long rate = clk->rate;
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/* If this is the PLL base clock, no more calculations needed */
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if (clk->pll_data)
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return rate;
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if (WARN_ON(!clk->parent))
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return rate;
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rate = clk->parent->rate;
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/* Otherwise, the parent must be a PLL */
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if (WARN_ON(!clk->parent->pll_data))
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return rate;
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pll = clk->parent->pll_data;
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/* If pre-PLL, source clock is before the multiplier and divider(s) */
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if (clk->flags & PRE_PLL)
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rate = pll->input_rate;
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if (!clk->div_reg)
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return rate;
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v = __raw_readl(pll->base + clk->div_reg);
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if (v & PLLDIV_EN) {
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plldiv = (v & pll->div_ratio_mask) + 1;
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if (plldiv)
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rate /= plldiv;
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}
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return rate;
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}
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int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
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{
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unsigned v;
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struct pll_data *pll;
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unsigned long input;
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unsigned ratio = 0;
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/* If this is the PLL base clock, wrong function to call */
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if (clk->pll_data)
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return -EINVAL;
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/* There must be a parent... */
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if (WARN_ON(!clk->parent))
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return -EINVAL;
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/* ... the parent must be a PLL... */
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if (WARN_ON(!clk->parent->pll_data))
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return -EINVAL;
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/* ... and this clock must have a divider. */
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if (WARN_ON(!clk->div_reg))
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return -EINVAL;
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pll = clk->parent->pll_data;
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input = clk->parent->rate;
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/* If pre-PLL, source clock is before the multiplier and divider(s) */
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if (clk->flags & PRE_PLL)
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input = pll->input_rate;
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if (input > rate) {
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/*
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* Can afford to provide an output little higher than requested
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* only if maximum rate supported by hardware on this sysclk
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* is known.
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*/
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if (clk->maxrate) {
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ratio = DIV_ROUND_CLOSEST(input, rate);
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if (input / ratio > clk->maxrate)
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ratio = 0;
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}
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if (ratio == 0)
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ratio = DIV_ROUND_UP(input, rate);
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ratio--;
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}
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if (ratio > pll->div_ratio_mask)
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return -EINVAL;
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do {
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v = __raw_readl(pll->base + PLLSTAT);
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} while (v & PLLSTAT_GOSTAT);
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v = __raw_readl(pll->base + clk->div_reg);
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v &= ~pll->div_ratio_mask;
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v |= ratio | PLLDIV_EN;
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__raw_writel(v, pll->base + clk->div_reg);
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v = __raw_readl(pll->base + PLLCMD);
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v |= PLLCMD_GOSET;
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__raw_writel(v, pll->base + PLLCMD);
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do {
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v = __raw_readl(pll->base + PLLSTAT);
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} while (v & PLLSTAT_GOSTAT);
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return 0;
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}
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EXPORT_SYMBOL(davinci_set_sysclk_rate);
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static unsigned long clk_leafclk_recalc(struct clk *clk)
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{
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if (WARN_ON(!clk->parent))
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return clk->rate;
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return clk->parent->rate;
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}
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int davinci_simple_set_rate(struct clk *clk, unsigned long rate)
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{
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clk->rate = rate;
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return 0;
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}
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static unsigned long clk_pllclk_recalc(struct clk *clk)
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{
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u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
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u8 bypass;
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struct pll_data *pll = clk->pll_data;
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unsigned long rate = clk->rate;
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ctrl = __raw_readl(pll->base + PLLCTL);
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rate = pll->input_rate = clk->parent->rate;
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if (ctrl & PLLCTL_PLLEN) {
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bypass = 0;
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mult = __raw_readl(pll->base + PLLM);
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//if (cpu_is_davinci_dm365())
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// mult = 2 * (mult & PLLM_PLLM_MASK);
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//else
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mult = (mult & PLLM_PLLM_MASK) + 1;
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} else
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bypass = 1;
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if (pll->flags & PLL_HAS_PREDIV) {
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prediv = __raw_readl(pll->base + PREDIV);
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if (prediv & PLLDIV_EN)
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prediv = (prediv & pll->div_ratio_mask) + 1;
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else
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prediv = 1;
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}
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if (pll->flags & PLL_HAS_POSTDIV) {
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postdiv = __raw_readl(pll->base + POSTDIV);
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if (postdiv & PLLDIV_EN)
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postdiv = (postdiv & pll->div_ratio_mask) + 1;
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else
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postdiv = 1;
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}
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if (!bypass) {
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rate /= prediv;
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rate *= mult;
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rate /= postdiv;
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}
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pr_debug("PLL%d: input = %lu MHz [ ",
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pll->num, clk->parent->rate / 1000000);
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if (bypass)
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pr_debug("bypass ");
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if (prediv > 1)
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pr_debug("/ %d ", prediv);
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if (mult > 1)
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pr_debug("* %d ", mult);
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if (postdiv > 1)
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pr_debug("/ %d ", postdiv);
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pr_debug("] --> %lu MHz output.\n", rate / 1000000);
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return rate;
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}
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/**
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* davinci_set_pllrate - set the output rate of a given PLL.
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*
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* Note: Currently tested to work with OMAP-L138 only.
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*
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* @pll: pll whose rate needs to be changed.
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* @prediv: The pre divider value. Passing 0 disables the pre-divider.
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* @pllm: The multiplier value. Passing 0 leads to multiply-by-one.
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* @postdiv: The post divider value. Passing 0 disables the post-divider.
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*/
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int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
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unsigned int mult, unsigned int postdiv)
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{
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u32 ctrl;
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unsigned int locktime;
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unsigned long flags;
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if (pll->base == NULL)
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return -EINVAL;
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/*
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* PLL lock time required per OMAP-L138 datasheet is
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* (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm)
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* as 4 and OSCIN cycle as 25 MHz.
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*/
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if (prediv) {
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locktime = ((2000 * prediv) / 100);
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prediv = (prediv - 1) | PLLDIV_EN;
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} else {
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locktime = PLL_LOCK_TIME;
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}
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if (postdiv)
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postdiv = (postdiv - 1) | PLLDIV_EN;
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if (mult)
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mult = mult - 1;
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ctrl = __raw_readl(pll->base + PLLCTL);
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/* Switch the PLL to bypass mode */
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ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
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__raw_writel(ctrl, pll->base + PLLCTL);
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udelay(PLL_BYPASS_TIME);
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/* Reset and enable PLL */
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ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
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__raw_writel(ctrl, pll->base + PLLCTL);
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if (pll->flags & PLL_HAS_PREDIV)
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__raw_writel(prediv, pll->base + PREDIV);
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__raw_writel(mult, pll->base + PLLM);
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if (pll->flags & PLL_HAS_POSTDIV)
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__raw_writel(postdiv, pll->base + POSTDIV);
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udelay(PLL_RESET_TIME);
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/* Bring PLL out of reset */
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ctrl |= PLLCTL_PLLRST;
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__raw_writel(ctrl, pll->base + PLLCTL);
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udelay(locktime);
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/* Remove PLL from bypass mode */
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ctrl |= PLLCTL_PLLEN;
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__raw_writel(ctrl, pll->base + PLLCTL);
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return 0;
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}
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EXPORT_SYMBOL(davinci_set_pllrate);
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/**
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* davinci_set_refclk_rate() - Set the reference clock rate
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* @rate: The new rate.
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*
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* Sets the reference clock rate to a given value. This will most likely
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* result in the entire clock tree getting updated.
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*
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* This is used to support boards which use a reference clock different
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* than that used by default in <soc>.c file. The reference clock rate
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* should be updated early in the boot process; ideally soon after the
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* clock tree has been initialized once with the default reference clock
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* rate (davinci_common_init()).
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*
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* Returns 0 on success, error otherwise.
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*/
|
||||
int davinci_set_refclk_rate(unsigned long rate)
|
||||
{
|
||||
struct clk *refclk;
|
||||
|
||||
refclk = clk_get(NULL, "ref");
|
||||
if (IS_ERR(refclk)) {
|
||||
pr_err("%s: failed to get reference clock\n", __func__);
|
||||
return PTR_ERR(refclk);
|
||||
}
|
||||
|
||||
clk_set_rate(refclk, rate);
|
||||
|
||||
clk_put(refclk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __init davinci_clk_init(struct clk_lookup *clocks)
|
||||
{
|
||||
struct clk_lookup *c;
|
||||
struct clk *clk;
|
||||
size_t num_clocks = 0;
|
||||
|
||||
for (c = clocks; c->clk; c++) {
|
||||
clk = c->clk;
|
||||
|
||||
if (!clk->recalc) {
|
||||
|
||||
/* Check if clock is a PLL */
|
||||
if (clk->pll_data)
|
||||
clk->recalc = clk_pllclk_recalc;
|
||||
|
||||
/* Else, if it is a PLL-derived clock */
|
||||
else if (clk->flags & CLK_PLL)
|
||||
clk->recalc = clk_sysclk_recalc;
|
||||
|
||||
/* Otherwise, it is a leaf clock (PSC clock) */
|
||||
else if (clk->parent)
|
||||
clk->recalc = clk_leafclk_recalc;
|
||||
}
|
||||
|
||||
if (clk->pll_data) {
|
||||
struct pll_data *pll = clk->pll_data;
|
||||
|
||||
if (!pll->div_ratio_mask)
|
||||
pll->div_ratio_mask = PLLDIV_RATIO_MASK;
|
||||
|
||||
if (pll->phys_base && !pll->base) {
|
||||
pll->base = pll->phys_base;
|
||||
WARN_ON(!pll->base);
|
||||
}
|
||||
}
|
||||
|
||||
if (clk->recalc)
|
||||
clk->rate = clk->recalc(clk);
|
||||
|
||||
if (clk->lpsc)
|
||||
clk->flags |= CLK_PSC;
|
||||
|
||||
if (clk->flags & PSC_LRST)
|
||||
clk->reset = davinci_clk_reset;
|
||||
|
||||
clk_register(clk);
|
||||
num_clocks++;
|
||||
|
||||
/* Turn on clocks that Linux doesn't otherwise manage */
|
||||
if (clk->flags & ALWAYS_ENABLED)
|
||||
clk_enable(clk);
|
||||
}
|
||||
|
||||
clkdev_add_table(clocks, num_clocks);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,137 @@
|
|||
/*
|
||||
* TI DaVinci clock definitions
|
||||
*
|
||||
* Copyright (C) 2006-2007 Texas Instruments.
|
||||
* Copyright (C) 2008-2009 Deep Root Systems, LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_DAVINCI_CLOCK_H
|
||||
#define __ARCH_ARM_DAVINCI_CLOCK_H
|
||||
|
||||
#define DAVINCI_PLL1_BASE 0x01c40800
|
||||
#define DAVINCI_PLL2_BASE 0x01c40c00
|
||||
#define MAX_PLL 2
|
||||
|
||||
/* PLL/Reset register offsets */
|
||||
#define PLLCTL 0x100
|
||||
#define PLLCTL_PLLEN BIT(0)
|
||||
#define PLLCTL_PLLPWRDN BIT(1)
|
||||
#define PLLCTL_PLLRST BIT(3)
|
||||
#define PLLCTL_PLLDIS BIT(4)
|
||||
#define PLLCTL_PLLENSRC BIT(5)
|
||||
#define PLLCTL_CLKMODE BIT(8)
|
||||
|
||||
#define PLLM 0x110
|
||||
#define PLLM_PLLM_MASK 0xff
|
||||
|
||||
#define PREDIV 0x114
|
||||
#define PLLDIV1 0x118
|
||||
#define PLLDIV2 0x11c
|
||||
#define PLLDIV3 0x120
|
||||
#define POSTDIV 0x128
|
||||
#define BPDIV 0x12c
|
||||
#define PLLCMD 0x138
|
||||
#define PLLSTAT 0x13c
|
||||
#define PLLALNCTL 0x140
|
||||
#define PLLDCHANGE 0x144
|
||||
#define PLLCKEN 0x148
|
||||
#define PLLCKSTAT 0x14c
|
||||
#define PLLSYSTAT 0x150
|
||||
#define PLLDIV4 0x160
|
||||
#define PLLDIV5 0x164
|
||||
#define PLLDIV6 0x168
|
||||
#define PLLDIV7 0x16c
|
||||
#define PLLDIV8 0x170
|
||||
#define PLLDIV9 0x174
|
||||
#define PLLDIV_EN BIT(15)
|
||||
#define PLLDIV_RATIO_MASK 0x1f
|
||||
|
||||
/*
|
||||
* OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
|
||||
* cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
|
||||
* ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
|
||||
* is ~25MHz. Units are micro seconds.
|
||||
*/
|
||||
#define PLL_BYPASS_TIME 1
|
||||
/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
|
||||
#define PLL_RESET_TIME 1
|
||||
/*
|
||||
* From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
|
||||
* Units are micro seconds.
|
||||
*/
|
||||
#define PLL_LOCK_TIME 20
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#include <linux/list.h>
|
||||
#include <linux/clkdev.h>
|
||||
|
||||
#define PLLSTAT_GOSTAT BIT(0)
|
||||
#define PLLCMD_GOSET BIT(0)
|
||||
|
||||
struct pll_data {
|
||||
u32 phys_base;
|
||||
void __iomem *base;
|
||||
u32 num;
|
||||
u32 flags;
|
||||
u32 input_rate;
|
||||
u32 div_ratio_mask;
|
||||
};
|
||||
#define PLL_HAS_PREDIV 0x01
|
||||
#define PLL_HAS_POSTDIV 0x02
|
||||
|
||||
struct clk {
|
||||
struct list_head node;
|
||||
struct module *owner;
|
||||
const char *name;
|
||||
unsigned long rate;
|
||||
unsigned long maxrate; /* H/W supported max rate */
|
||||
u8 usecount;
|
||||
u8 lpsc;
|
||||
u8 gpsc;
|
||||
u8 domain;
|
||||
u32 flags;
|
||||
struct clk *parent;
|
||||
struct list_head children; /* list of children */
|
||||
struct list_head childnode; /* parent's child list node */
|
||||
struct pll_data *pll_data;
|
||||
u32 div_reg;
|
||||
unsigned long (*recalc) (struct clk *);
|
||||
int (*set_rate) (struct clk *clk, unsigned long rate);
|
||||
int (*round_rate) (struct clk *clk, unsigned long rate);
|
||||
int (*reset) (struct clk *clk, bool reset);
|
||||
void (*clk_enable) (struct clk *clk);
|
||||
void (*clk_disable) (struct clk *clk);
|
||||
};
|
||||
|
||||
/* Clock flags: SoC-specific flags start at BIT(16) */
|
||||
#define ALWAYS_ENABLED BIT(1)
|
||||
#define CLK_PSC BIT(2)
|
||||
#define CLK_PLL BIT(3) /* PLL-derived clock */
|
||||
#define PRE_PLL BIT(4) /* source is before PLL mult/div */
|
||||
#define PSC_SWRSTDISABLE BIT(5) /* Disable state is SwRstDisable */
|
||||
#define PSC_FORCE BIT(6) /* Force module state transtition */
|
||||
#define PSC_LRST BIT(8) /* Use local reset on enable/disable */
|
||||
|
||||
#define CLK(dev, con, ck) \
|
||||
{ \
|
||||
.dev_id = dev, \
|
||||
.con_id = con, \
|
||||
.clk = ck, \
|
||||
} \
|
||||
|
||||
int davinci_clk_init(struct clk_lookup *clocks);
|
||||
int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
|
||||
unsigned int mult, unsigned int postdiv);
|
||||
int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
|
||||
int davinci_set_refclk_rate(unsigned long rate);
|
||||
int davinci_simple_set_rate(struct clk *clk, unsigned long rate);
|
||||
int davinci_clk_reset(struct clk *clk, bool reset);
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* Code commons to all DaVinci SoCs.
|
||||
*
|
||||
* Author: Mark A. Greer <mgreer@mvista.com>
|
||||
*
|
||||
* 2009 (c) MontaVista Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#include <mach/common.h>
|
||||
|
||||
#include "clock.h"
|
||||
|
||||
struct davinci_soc_info davinci_soc_info;
|
||||
EXPORT_SYMBOL(davinci_soc_info);
|
||||
|
||||
void davinci_common_init(struct davinci_soc_info *soc_info)
|
||||
{
|
||||
memcpy(&davinci_soc_info, soc_info, sizeof(struct davinci_soc_info));
|
||||
davinci_clk_init(davinci_soc_info.cpu_clks);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,378 @@
|
|||
/*
|
||||
* TI DaVinci DM644x chip specific setup
|
||||
*
|
||||
* Author: Kevin Hilman, Deep Root Systems, LLC
|
||||
*
|
||||
* 2007 (c) Deep Root Systems, LLC. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
#include <mach/common.h>
|
||||
#include <mach/psc.h>
|
||||
#include "clock.h"
|
||||
|
||||
#define DM644X_REF_FREQ 27000000
|
||||
|
||||
#define DM644X_EMAC_BASE 0x01c80000
|
||||
#define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
|
||||
#define DM644X_EMAC_CNTRL_OFFSET 0x0000
|
||||
#define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000
|
||||
#define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
|
||||
#define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
|
||||
|
||||
static struct pll_data pll1_data = {
|
||||
.num = 1,
|
||||
.phys_base = DAVINCI_PLL1_BASE,
|
||||
};
|
||||
|
||||
static struct pll_data pll2_data = {
|
||||
.num = 2,
|
||||
.phys_base = DAVINCI_PLL2_BASE,
|
||||
};
|
||||
|
||||
static struct clk ref_clk = {
|
||||
.name = "ref_clk",
|
||||
.rate = DM644X_REF_FREQ,
|
||||
};
|
||||
|
||||
static struct clk pll1_clk = {
|
||||
.name = "pll1",
|
||||
.parent = &ref_clk,
|
||||
.pll_data = &pll1_data,
|
||||
.flags = CLK_PLL,
|
||||
};
|
||||
|
||||
static struct clk pll1_sysclk1 = {
|
||||
.name = "pll1_sysclk1",
|
||||
.parent = &pll1_clk,
|
||||
.flags = CLK_PLL,
|
||||
.div_reg = PLLDIV1,
|
||||
};
|
||||
|
||||
static struct clk pll1_sysclk2 = {
|
||||
.name = "pll1_sysclk2",
|
||||
.parent = &pll1_clk,
|
||||
.flags = CLK_PLL,
|
||||
.div_reg = PLLDIV2,
|
||||
};
|
||||
|
||||
static struct clk pll1_sysclk3 = {
|
||||
.name = "pll1_sysclk3",
|
||||
.parent = &pll1_clk,
|
||||
.flags = CLK_PLL,
|
||||
.div_reg = PLLDIV3,
|
||||
};
|
||||
|
||||
static struct clk pll1_sysclk5 = {
|
||||
.name = "pll1_sysclk5",
|
||||
.parent = &pll1_clk,
|
||||
.flags = CLK_PLL,
|
||||
.div_reg = PLLDIV5,
|
||||
};
|
||||
|
||||
static struct clk pll1_aux_clk = {
|
||||
.name = "pll1_aux_clk",
|
||||
.parent = &pll1_clk,
|
||||
.flags = CLK_PLL | PRE_PLL,
|
||||
};
|
||||
|
||||
static struct clk pll1_sysclkbp = {
|
||||
.name = "pll1_sysclkbp",
|
||||
.parent = &pll1_clk,
|
||||
.flags = CLK_PLL | PRE_PLL,
|
||||
.div_reg = BPDIV
|
||||
};
|
||||
|
||||
static struct clk pll2_clk = {
|
||||
.name = "pll2",
|
||||
.parent = &ref_clk,
|
||||
.pll_data = &pll2_data,
|
||||
.flags = CLK_PLL,
|
||||
};
|
||||
|
||||
static struct clk pll2_sysclk1 = {
|
||||
.name = "pll2_sysclk1",
|
||||
.parent = &pll2_clk,
|
||||
.flags = CLK_PLL,
|
||||
.div_reg = PLLDIV1,
|
||||
};
|
||||
|
||||
static struct clk pll2_sysclk2 = {
|
||||
.name = "pll2_sysclk2",
|
||||
.parent = &pll2_clk,
|
||||
.flags = CLK_PLL,
|
||||
.div_reg = PLLDIV2,
|
||||
};
|
||||
|
||||
static struct clk pll2_sysclkbp = {
|
||||
.name = "pll2_sysclkbp",
|
||||
.parent = &pll2_clk,
|
||||
.flags = CLK_PLL | PRE_PLL,
|
||||
.div_reg = BPDIV
|
||||
};
|
||||
|
||||
static struct clk dsp_clk = {
|
||||
.name = "dsp",
|
||||
.parent = &pll1_sysclk1,
|
||||
.lpsc = DAVINCI_LPSC_GEM,
|
||||
.domain = DAVINCI_GPSC_DSPDOMAIN,
|
||||
.usecount = 1, /* REVISIT how to disable? */
|
||||
};
|
||||
|
||||
static struct clk arm_clk = {
|
||||
.name = "arm",
|
||||
.parent = &pll1_sysclk2,
|
||||
.lpsc = DAVINCI_LPSC_ARM,
|
||||
.flags = ALWAYS_ENABLED,
|
||||
};
|
||||
|
||||
static struct clk vicp_clk = {
|
||||
.name = "vicp",
|
||||
.parent = &pll1_sysclk2,
|
||||
.lpsc = DAVINCI_LPSC_IMCOP,
|
||||
.domain = DAVINCI_GPSC_DSPDOMAIN,
|
||||
.usecount = 1, /* REVISIT how to disable? */
|
||||
};
|
||||
|
||||
static struct clk vpss_master_clk = {
|
||||
.name = "vpss_master",
|
||||
.parent = &pll1_sysclk3,
|
||||
.lpsc = DAVINCI_LPSC_VPSSMSTR,
|
||||
.flags = CLK_PSC,
|
||||
};
|
||||
|
||||
static struct clk vpss_slave_clk = {
|
||||
.name = "vpss_slave",
|
||||
.parent = &pll1_sysclk3,
|
||||
.lpsc = DAVINCI_LPSC_VPSSSLV,
|
||||
};
|
||||
|
||||
static struct clk uart0_clk = {
|
||||
.name = "uart0",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_UART0,
|
||||
};
|
||||
|
||||
static struct clk uart1_clk = {
|
||||
.name = "uart1",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_UART1,
|
||||
};
|
||||
|
||||
static struct clk uart2_clk = {
|
||||
.name = "uart2",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_UART2,
|
||||
};
|
||||
|
||||
static struct clk emac_clk = {
|
||||
.name = "emac",
|
||||
.parent = &pll1_sysclk5,
|
||||
.lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
|
||||
};
|
||||
|
||||
static struct clk i2c_clk = {
|
||||
.name = "i2c",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_I2C,
|
||||
};
|
||||
|
||||
static struct clk ide_clk = {
|
||||
.name = "ide",
|
||||
.parent = &pll1_sysclk5,
|
||||
.lpsc = DAVINCI_LPSC_ATA,
|
||||
};
|
||||
|
||||
static struct clk asp_clk = {
|
||||
.name = "asp0",
|
||||
.parent = &pll1_sysclk5,
|
||||
.lpsc = DAVINCI_LPSC_McBSP,
|
||||
};
|
||||
|
||||
static struct clk mmcsd_clk = {
|
||||
.name = "mmcsd",
|
||||
.parent = &pll1_sysclk5,
|
||||
.lpsc = DAVINCI_LPSC_MMC_SD,
|
||||
};
|
||||
|
||||
static struct clk spi_clk = {
|
||||
.name = "spi",
|
||||
.parent = &pll1_sysclk5,
|
||||
.lpsc = DAVINCI_LPSC_SPI,
|
||||
};
|
||||
|
||||
static struct clk gpio_clk = {
|
||||
.name = "gpio",
|
||||
.parent = &pll1_sysclk5,
|
||||
.lpsc = DAVINCI_LPSC_GPIO,
|
||||
};
|
||||
|
||||
static struct clk usb_clk = {
|
||||
.name = "usb",
|
||||
.parent = &pll1_sysclk5,
|
||||
.lpsc = DAVINCI_LPSC_USB,
|
||||
};
|
||||
|
||||
static struct clk vlynq_clk = {
|
||||
.name = "vlynq",
|
||||
.parent = &pll1_sysclk5,
|
||||
.lpsc = DAVINCI_LPSC_VLYNQ,
|
||||
};
|
||||
|
||||
static struct clk aemif_clk = {
|
||||
.name = "aemif",
|
||||
.parent = &pll1_sysclk5,
|
||||
.lpsc = DAVINCI_LPSC_AEMIF,
|
||||
};
|
||||
|
||||
static struct clk pwm0_clk = {
|
||||
.name = "pwm0",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_PWM0,
|
||||
};
|
||||
|
||||
static struct clk pwm1_clk = {
|
||||
.name = "pwm1",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_PWM1,
|
||||
};
|
||||
|
||||
static struct clk pwm2_clk = {
|
||||
.name = "pwm2",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_PWM2,
|
||||
};
|
||||
|
||||
static struct clk timer0_clk = {
|
||||
.name = "timer0",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_TIMER0,
|
||||
};
|
||||
|
||||
static struct clk timer1_clk = {
|
||||
.name = "timer1",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_TIMER1,
|
||||
};
|
||||
|
||||
static struct clk timer2_clk = {
|
||||
.name = "timer2",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_TIMER2,
|
||||
.usecount = 1, /* REVISIT: why can't this be disabled? */
|
||||
};
|
||||
|
||||
static struct clk_lookup dm644x_clks[] = {
|
||||
CLK(NULL, "ref", &ref_clk),
|
||||
CLK(NULL, "pll1", &pll1_clk),
|
||||
CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
|
||||
CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
|
||||
CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
|
||||
CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
|
||||
CLK(NULL, "pll1_aux", &pll1_aux_clk),
|
||||
CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
|
||||
CLK(NULL, "pll2", &pll2_clk),
|
||||
CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
|
||||
CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
|
||||
CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
|
||||
CLK(NULL, "dsp", &dsp_clk),
|
||||
CLK(NULL, "arm", &arm_clk),
|
||||
CLK(NULL, "vicp", &vicp_clk),
|
||||
CLK("vpss", "master", &vpss_master_clk),
|
||||
CLK("vpss", "slave", &vpss_slave_clk),
|
||||
CLK(NULL, "arm", &arm_clk),
|
||||
//CLK("serial8250.0", NULL, &uart0_clk),
|
||||
CLK("1c20000.serial", NULL, &uart0_clk),
|
||||
CLK("serial8250.1", NULL, &uart1_clk),
|
||||
CLK("serial8250.2", NULL, &uart2_clk),
|
||||
//CLK("davinci_emac.1", NULL, &emac_clk),
|
||||
CLK("davinci_emac0", NULL, &emac_clk),
|
||||
CLK("davinci_mdio.0", "fck", &emac_clk),
|
||||
CLK("i2c_davinci.1", NULL, &i2c_clk),
|
||||
CLK("palm_bk3710", NULL, &ide_clk),
|
||||
CLK("davinci-mcbsp", NULL, &asp_clk),
|
||||
CLK("dm6441-mmc.0", NULL, &mmcsd_clk),
|
||||
CLK(NULL, "spi", &spi_clk),
|
||||
CLK(NULL, "gpio", &gpio_clk),
|
||||
CLK(NULL, "usb", &usb_clk),
|
||||
CLK(NULL, "vlynq", &vlynq_clk),
|
||||
CLK(NULL, "aemif", &aemif_clk),
|
||||
CLK(NULL, "pwm0", &pwm0_clk),
|
||||
CLK(NULL, "pwm1", &pwm1_clk),
|
||||
CLK(NULL, "pwm2", &pwm2_clk),
|
||||
CLK(NULL, "timer0", &timer0_clk),
|
||||
CLK(NULL, "timer1", &timer1_clk),
|
||||
//CLK("davinci-wdt", NULL, &timer2_clk),
|
||||
CLK("1c21c00.wdt", NULL, &timer2_clk),
|
||||
CLK(NULL, NULL, NULL),
|
||||
};
|
||||
|
||||
#if 0
|
||||
static struct emac_platform_data dm644x_emac_pdata = {
|
||||
.ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
|
||||
.ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
|
||||
.ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET,
|
||||
.ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE,
|
||||
.version = EMAC_VERSION_1,
|
||||
};
|
||||
|
||||
static struct resource dm644x_emac_resources[] = {
|
||||
{
|
||||
.start = DM644X_EMAC_BASE,
|
||||
.end = DM644X_EMAC_BASE + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_EMACINT,
|
||||
.end = IRQ_EMACINT,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device dm644x_emac_device = {
|
||||
.name = "davinci_emac",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = &dm644x_emac_pdata,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(dm644x_emac_resources),
|
||||
.resource = dm644x_emac_resources,
|
||||
};
|
||||
|
||||
static struct resource dm644x_mdio_resources[] = {
|
||||
{
|
||||
.start = DM644X_EMAC_MDIO_BASE,
|
||||
.end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device dm644x_mdio_device = {
|
||||
.name = "davinci_mdio",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(dm644x_mdio_resources),
|
||||
.resource = dm644x_mdio_resources,
|
||||
};
|
||||
#endif
|
||||
|
||||
static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
|
||||
|
||||
static struct davinci_soc_info davinci_soc_info_dm644x = {
|
||||
.cpu_clks = dm644x_clks,
|
||||
.psc_bases = dm644x_psc_bases,
|
||||
.psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
|
||||
};
|
||||
|
||||
static int dm644x_init(void)
|
||||
{
|
||||
davinci_common_init(&davinci_soc_info_dm644x);
|
||||
|
||||
return 0;
|
||||
}
|
||||
postcore_initcall(dm644x_init);
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* Header for code common to all DaVinci machines.
|
||||
*
|
||||
* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
|
||||
*
|
||||
* 2007 (c) MontaVista Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H
|
||||
#define __ARCH_ARM_MACH_DAVINCI_COMMON_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct davinci_soc_info {
|
||||
struct clk_lookup *cpu_clks;
|
||||
u32 *psc_bases;
|
||||
unsigned long psc_bases_num;
|
||||
};
|
||||
|
||||
extern struct davinci_soc_info davinci_soc_info;
|
||||
void davinci_common_init(struct davinci_soc_info *soc_info);
|
||||
|
||||
#endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */
|
||||
|
|
@ -0,0 +1,218 @@
|
|||
/*
|
||||
* DaVinci Power & Sleep Controller (PSC) defines
|
||||
*
|
||||
* Copyright (C) 2006 Texas Instruments.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
#ifndef __ASM_ARCH_PSC_H
|
||||
#define __ASM_ARCH_PSC_H
|
||||
|
||||
#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000
|
||||
|
||||
/* Power and Sleep Controller (PSC) Domains */
|
||||
#define DAVINCI_GPSC_ARMDOMAIN 0
|
||||
#define DAVINCI_GPSC_DSPDOMAIN 1
|
||||
|
||||
#define DAVINCI_LPSC_VPSSMSTR 0
|
||||
#define DAVINCI_LPSC_VPSSSLV 1
|
||||
#define DAVINCI_LPSC_TPCC 2
|
||||
#define DAVINCI_LPSC_TPTC0 3
|
||||
#define DAVINCI_LPSC_TPTC1 4
|
||||
#define DAVINCI_LPSC_EMAC 5
|
||||
#define DAVINCI_LPSC_EMAC_WRAPPER 6
|
||||
#define DAVINCI_LPSC_USB 9
|
||||
#define DAVINCI_LPSC_ATA 10
|
||||
#define DAVINCI_LPSC_VLYNQ 11
|
||||
#define DAVINCI_LPSC_UHPI 12
|
||||
#define DAVINCI_LPSC_DDR_EMIF 13
|
||||
#define DAVINCI_LPSC_AEMIF 14
|
||||
#define DAVINCI_LPSC_MMC_SD 15
|
||||
#define DAVINCI_LPSC_McBSP 17
|
||||
#define DAVINCI_LPSC_I2C 18
|
||||
#define DAVINCI_LPSC_UART0 19
|
||||
#define DAVINCI_LPSC_UART1 20
|
||||
#define DAVINCI_LPSC_UART2 21
|
||||
#define DAVINCI_LPSC_SPI 22
|
||||
#define DAVINCI_LPSC_PWM0 23
|
||||
#define DAVINCI_LPSC_PWM1 24
|
||||
#define DAVINCI_LPSC_PWM2 25
|
||||
#define DAVINCI_LPSC_GPIO 26
|
||||
#define DAVINCI_LPSC_TIMER0 27
|
||||
#define DAVINCI_LPSC_TIMER1 28
|
||||
#define DAVINCI_LPSC_TIMER2 29
|
||||
#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
|
||||
#define DAVINCI_LPSC_ARM 31
|
||||
#define DAVINCI_LPSC_SCR2 32
|
||||
#define DAVINCI_LPSC_SCR3 33
|
||||
#define DAVINCI_LPSC_SCR4 34
|
||||
#define DAVINCI_LPSC_CROSSBAR 35
|
||||
#define DAVINCI_LPSC_CFG27 36
|
||||
#define DAVINCI_LPSC_CFG3 37
|
||||
#define DAVINCI_LPSC_CFG5 38
|
||||
#define DAVINCI_LPSC_GEM 39
|
||||
#define DAVINCI_LPSC_IMCOP 40
|
||||
|
||||
#define DM355_LPSC_TIMER3 5
|
||||
#define DM355_LPSC_SPI1 6
|
||||
#define DM355_LPSC_MMC_SD1 7
|
||||
#define DM355_LPSC_McBSP1 8
|
||||
#define DM355_LPSC_PWM3 10
|
||||
#define DM355_LPSC_SPI2 11
|
||||
#define DM355_LPSC_RTO 12
|
||||
#define DM355_LPSC_VPSS_DAC 41
|
||||
|
||||
/* DM365 */
|
||||
#define DM365_LPSC_TIMER3 5
|
||||
#define DM365_LPSC_SPI1 6
|
||||
#define DM365_LPSC_MMC_SD1 7
|
||||
#define DM365_LPSC_McBSP1 8
|
||||
#define DM365_LPSC_PWM3 10
|
||||
#define DM365_LPSC_SPI2 11
|
||||
#define DM365_LPSC_RTO 12
|
||||
#define DM365_LPSC_TIMER4 17
|
||||
#define DM365_LPSC_SPI0 22
|
||||
#define DM365_LPSC_SPI3 38
|
||||
#define DM365_LPSC_SPI4 39
|
||||
#define DM365_LPSC_EMAC 40
|
||||
#define DM365_LPSC_VOICE_CODEC 44
|
||||
#define DM365_LPSC_DAC_CLK 46
|
||||
#define DM365_LPSC_VPSSMSTR 47
|
||||
#define DM365_LPSC_MJCP 50
|
||||
|
||||
/*
|
||||
* LPSC Assignments
|
||||
*/
|
||||
#define DM646X_LPSC_ARM 0
|
||||
#define DM646X_LPSC_C64X_CPU 1
|
||||
#define DM646X_LPSC_HDVICP0 2
|
||||
#define DM646X_LPSC_HDVICP1 3
|
||||
#define DM646X_LPSC_TPCC 4
|
||||
#define DM646X_LPSC_TPTC0 5
|
||||
#define DM646X_LPSC_TPTC1 6
|
||||
#define DM646X_LPSC_TPTC2 7
|
||||
#define DM646X_LPSC_TPTC3 8
|
||||
#define DM646X_LPSC_PCI 13
|
||||
#define DM646X_LPSC_EMAC 14
|
||||
#define DM646X_LPSC_VDCE 15
|
||||
#define DM646X_LPSC_VPSSMSTR 16
|
||||
#define DM646X_LPSC_VPSSSLV 17
|
||||
#define DM646X_LPSC_TSIF0 18
|
||||
#define DM646X_LPSC_TSIF1 19
|
||||
#define DM646X_LPSC_DDR_EMIF 20
|
||||
#define DM646X_LPSC_AEMIF 21
|
||||
#define DM646X_LPSC_McASP0 22
|
||||
#define DM646X_LPSC_McASP1 23
|
||||
#define DM646X_LPSC_CRGEN0 24
|
||||
#define DM646X_LPSC_CRGEN1 25
|
||||
#define DM646X_LPSC_UART0 26
|
||||
#define DM646X_LPSC_UART1 27
|
||||
#define DM646X_LPSC_UART2 28
|
||||
#define DM646X_LPSC_PWM0 29
|
||||
#define DM646X_LPSC_PWM1 30
|
||||
#define DM646X_LPSC_I2C 31
|
||||
#define DM646X_LPSC_SPI 32
|
||||
#define DM646X_LPSC_GPIO 33
|
||||
#define DM646X_LPSC_TIMER0 34
|
||||
#define DM646X_LPSC_TIMER1 35
|
||||
#define DM646X_LPSC_ARM_INTC 45
|
||||
|
||||
/* PSC0 defines */
|
||||
#define DA8XX_LPSC0_TPCC 0
|
||||
#define DA8XX_LPSC0_TPTC0 1
|
||||
#define DA8XX_LPSC0_TPTC1 2
|
||||
#define DA8XX_LPSC0_EMIF25 3
|
||||
#define DA8XX_LPSC0_SPI0 4
|
||||
#define DA8XX_LPSC0_MMC_SD 5
|
||||
#define DA8XX_LPSC0_AINTC 6
|
||||
#define DA8XX_LPSC0_ARM_RAM_ROM 7
|
||||
#define DA8XX_LPSC0_SECU_MGR 8
|
||||
#define DA8XX_LPSC0_UART0 9
|
||||
#define DA8XX_LPSC0_SCR0_SS 10
|
||||
#define DA8XX_LPSC0_SCR1_SS 11
|
||||
#define DA8XX_LPSC0_SCR2_SS 12
|
||||
#define DA8XX_LPSC0_PRUSS 13
|
||||
#define DA8XX_LPSC0_ARM 14
|
||||
#define DA8XX_LPSC0_GEM 15
|
||||
|
||||
/* PSC1 defines */
|
||||
#define DA850_LPSC1_TPCC1 0
|
||||
#define DA8XX_LPSC1_USB20 1
|
||||
#define DA8XX_LPSC1_USB11 2
|
||||
#define DA8XX_LPSC1_GPIO 3
|
||||
#define DA8XX_LPSC1_UHPI 4
|
||||
#define DA8XX_LPSC1_CPGMAC 5
|
||||
#define DA8XX_LPSC1_EMIF3C 6
|
||||
#define DA8XX_LPSC1_McASP0 7
|
||||
#define DA830_LPSC1_McASP1 8
|
||||
#define DA850_LPSC1_SATA 8
|
||||
#define DA830_LPSC1_McASP2 9
|
||||
#define DA850_LPSC1_VPIF 9
|
||||
#define DA8XX_LPSC1_SPI1 10
|
||||
#define DA8XX_LPSC1_I2C 11
|
||||
#define DA8XX_LPSC1_UART1 12
|
||||
#define DA8XX_LPSC1_UART2 13
|
||||
#define DA8XX_LPSC1_LCDC 16
|
||||
#define DA8XX_LPSC1_PWM 17
|
||||
#define DA850_LPSC1_MMC_SD1 18
|
||||
#define DA8XX_LPSC1_ECAP 20
|
||||
#define DA830_LPSC1_EQEP 21
|
||||
#define DA850_LPSC1_TPTC2 21
|
||||
#define DA8XX_LPSC1_SCR_P0_SS 24
|
||||
#define DA8XX_LPSC1_SCR_P1_SS 25
|
||||
#define DA8XX_LPSC1_CR_P3_SS 26
|
||||
#define DA8XX_LPSC1_L3_CBA_RAM 31
|
||||
|
||||
/* PSC register offsets */
|
||||
#define EPCPR 0x070
|
||||
#define PTCMD 0x120
|
||||
#define PTSTAT 0x128
|
||||
#define PDSTAT 0x200
|
||||
#define PDCTL 0x300
|
||||
#define MDSTAT 0x800
|
||||
#define MDCTL 0xA00
|
||||
|
||||
/* PSC module states */
|
||||
#define PSC_STATE_SWRSTDISABLE 0
|
||||
#define PSC_STATE_SYNCRST 1
|
||||
#define PSC_STATE_DISABLE 2
|
||||
#define PSC_STATE_ENABLE 3
|
||||
|
||||
#define MDSTAT_STATE_MASK 0x3f
|
||||
#define PDSTAT_STATE_MASK 0x1f
|
||||
#define MDCTL_LRST BIT(8)
|
||||
#define MDCTL_EMUIHBIE BIT(10)
|
||||
#define MDCTL_FORCE BIT(31)
|
||||
#define PDCTL_NEXT BIT(0)
|
||||
#define PDCTL_EPCGOOD BIT(8)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
|
||||
extern void davinci_psc_reset(unsigned int ctlr, unsigned int id,
|
||||
bool reset);
|
||||
extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
|
||||
unsigned int id, bool enable, u32 flags);
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ARCH_PSC_H */
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
/*
|
||||
* TI DaVinci Power and Sleep Controller (PSC)
|
||||
*
|
||||
* Copyright (C) 2006 Texas Instruments.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <io.h>
|
||||
|
||||
#include <linux/sizes.h>
|
||||
|
||||
#include <mach/common.h>
|
||||
#include <mach/psc.h>
|
||||
|
||||
#include "clock.h"
|
||||
|
||||
/* Control "reset" line associated with PSC domain */
|
||||
void davinci_psc_reset(unsigned int ctlr, unsigned int id, bool reset)
|
||||
{
|
||||
u32 mdctl;
|
||||
void __iomem *psc_base;
|
||||
struct davinci_soc_info *soc_info = &davinci_soc_info;
|
||||
|
||||
if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
|
||||
pr_warn("PSC: Bad psc data: 0x%x[%d]\n",
|
||||
(int)soc_info->psc_bases, ctlr);
|
||||
return;
|
||||
}
|
||||
|
||||
psc_base = soc_info->psc_bases[ctlr];
|
||||
|
||||
mdctl = readl(psc_base + MDCTL + 4 * id);
|
||||
if (reset)
|
||||
mdctl &= ~MDCTL_LRST;
|
||||
else
|
||||
mdctl |= MDCTL_LRST;
|
||||
writel(mdctl, psc_base + MDCTL + 4 * id);
|
||||
}
|
||||
|
||||
/* Enable or disable a PSC domain */
|
||||
void davinci_psc_config(unsigned int domain, unsigned int ctlr,
|
||||
unsigned int id, bool enable, u32 flags)
|
||||
{
|
||||
u32 epcpr, ptcmd, ptstat, pdstat, pdctl, mdstat, mdctl;
|
||||
void __iomem *psc_base;
|
||||
struct davinci_soc_info *soc_info = &davinci_soc_info;
|
||||
u32 next_state = PSC_STATE_ENABLE;
|
||||
|
||||
if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
|
||||
pr_warn("PSC: Bad psc data: 0x%x[%d]\n",
|
||||
(int)soc_info->psc_bases, ctlr);
|
||||
return;
|
||||
}
|
||||
|
||||
psc_base = soc_info->psc_bases[ctlr];
|
||||
|
||||
if (!enable) {
|
||||
if (flags & PSC_SWRSTDISABLE)
|
||||
next_state = PSC_STATE_SWRSTDISABLE;
|
||||
else
|
||||
next_state = PSC_STATE_DISABLE;
|
||||
}
|
||||
|
||||
mdctl = readl(psc_base + MDCTL + 4 * id);
|
||||
mdctl &= ~MDSTAT_STATE_MASK;
|
||||
mdctl |= next_state;
|
||||
if (flags & PSC_FORCE)
|
||||
mdctl |= MDCTL_FORCE;
|
||||
|
||||
switch (id) {
|
||||
#ifdef CONFIG_SOC_DM644X
|
||||
/* Special treatment for some modules as for sprue14 p.7.4.2 */
|
||||
case DAVINCI_LPSC_VPSSSLV:
|
||||
case DAVINCI_LPSC_EMAC:
|
||||
case DAVINCI_LPSC_EMAC_WRAPPER:
|
||||
case DAVINCI_LPSC_MDIO:
|
||||
case DAVINCI_LPSC_USB:
|
||||
case DAVINCI_LPSC_ATA:
|
||||
case DAVINCI_LPSC_VLYNQ:
|
||||
case DAVINCI_LPSC_UHPI:
|
||||
case DAVINCI_LPSC_DDR_EMIF:
|
||||
case DAVINCI_LPSC_AEMIF:
|
||||
case DAVINCI_LPSC_MMC_SD:
|
||||
case DAVINCI_LPSC_MEMSTICK:
|
||||
case DAVINCI_LPSC_McBSP:
|
||||
case DAVINCI_LPSC_GPIO:
|
||||
mdctl |= MDCTL_EMUIHBIE;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
|
||||
writel(mdctl, psc_base + MDCTL + 4 * id);
|
||||
|
||||
pdstat = readl(psc_base + PDSTAT + 4 * domain);
|
||||
if ((pdstat & PDSTAT_STATE_MASK) == 0) {
|
||||
pdctl = readl(psc_base + PDCTL + 4 * domain);
|
||||
pdctl |= PDCTL_NEXT;
|
||||
writel(pdctl, psc_base + PDCTL + 4 * domain);
|
||||
|
||||
ptcmd = 1 << domain;
|
||||
writel(ptcmd, psc_base + PTCMD);
|
||||
|
||||
do {
|
||||
epcpr = readl(psc_base + EPCPR);
|
||||
} while ((((epcpr >> domain) & 1) == 0));
|
||||
|
||||
pdctl = readl(psc_base + PDCTL + 4 * domain);
|
||||
pdctl |= PDCTL_EPCGOOD;
|
||||
writel(pdctl, psc_base + PDCTL + 4 * domain);
|
||||
} else {
|
||||
ptcmd = 1 << domain;
|
||||
writel(ptcmd, psc_base + PTCMD);
|
||||
}
|
||||
|
||||
do {
|
||||
ptstat = readl(psc_base + PTSTAT);
|
||||
} while (!(((ptstat >> domain) & 1) == 0));
|
||||
|
||||
do {
|
||||
mdstat = readl(psc_base + MDSTAT + 4 * id);
|
||||
} while (!((mdstat & MDSTAT_STATE_MASK) == next_state));
|
||||
}
|
||||
Loading…
Reference in New Issue