MIPS: ath79: add pbl_ar9331_ddr1_config macro
See also u-boot_mod/u-boot/cpu/mips/ar7240/hornet_ddr_init.S See also this openocd commit: commit f59d2d9ecfee8899df531b87b7acaa468725f238 Author: Oleksij Rempel <linux@rempel-privat.de> Date: Fri Jan 30 13:05:31 2015 +0100 tcl/target|board: add config Atheros ar9331 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -67,6 +67,49 @@
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#define DDR_EMR2 (DDR_BASE | AR933X_DDR_DDR_EMR2)
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#define DDR_EMR2 (DDR_BASE | AR933X_DDR_DDR_EMR2)
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#define DDR_EMR3 (DDR_BASE | AR933X_DDR_DDR_EMR3)
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#define DDR_EMR3 (DDR_BASE | AR933X_DDR_DDR_EMR3)
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.macro pbl_ar9331_ddr1_config
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.set push
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.set noreorder
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pbl_reg_writel 0x7fbc8cd0, DDR_CONFIG
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pbl_reg_writel 0x9dd0e6a8, DDR_CONFIG2
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pbl_reg_writel DDR_CTRL_PREA, DDR_CTRL
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/* 0x133: on reset Mode Register value */
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pbl_reg_writel 0x133, DDR_MODE
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pbl_reg_writel DDR_CTRL_MRS, DDR_CTRL
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/*
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* DDR_EXT_MODE[1] = 1: Reduced Drive Strength
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* DDR_EXT_MODE[0] = 0: Enable DLL
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*/
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pbl_reg_writel 0x2, DDR_EXT_MODE
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pbl_reg_writel DDR_CTRL_EMRS, DDR_CTRL
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pbl_reg_writel DDR_CTRL_PREA, DDR_CTRL
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/* DLL out of reset, CAS Latency 3 */
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pbl_reg_writel 0x33, DDR_MODE
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pbl_reg_writel DDR_CTRL_MRS, DDR_CTRL
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/* Refresh control. Bit 14 is enable. Bits<13:0> Refresh time */
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pbl_reg_writel 0x4186, DDR_REFRESH
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/* This register is used along with DQ Lane 0; DQ[7:0], DQS_0 */
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pbl_reg_writel 0x8, DDR_TAP_CTRL0
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/* This register is used along with DQ Lane 1; DQ[15:8], DQS_1 */
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pbl_reg_writel 0x9, DDR_TAP_CTRL1
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/*
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* DDR read and capture bit mask.
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* Each bit represents a cycle of valid data.
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* 0xff: use 16-bit DDR
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*/
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pbl_reg_writel 0xff, DDR_RD_DATA
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.set pop
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.endm
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.macro pbl_ar9331_ddr2_config
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.macro pbl_ar9331_ddr2_config
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.set push
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.set push
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.set noreorder
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.set noreorder
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