ARM i.MX: add 2-bit gate clock support
Based on kernel clk-gate2 and barebox clk-gate implementations. Signed-off-by: Dmitry Lavnikevich <d.lavnikevich@sam-solutions.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -15,7 +15,7 @@ obj-$(CONFIG_IMX_IIM) += iim.o
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obj-$(CONFIG_IMX_OCOTP) += ocotp.o
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obj-$(CONFIG_NAND_IMX) += nand.o
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lwl-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o
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obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-pfd.o
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obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-pfd.o clk-gate2.o
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obj-y += devices.o imx.o esdctl.o
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obj-y += boot.o
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obj-$(CONFIG_BAREBOX_UPDATE) += imx-bbu-internal.o
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@ -0,0 +1,142 @@
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/*
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* clk-gate2.c - barebox 2-bit clock support. Based on Linux clk support
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <io.h>
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#include <malloc.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include "clk.h"
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struct clk_gate2 {
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struct clk clk;
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void __iomem *reg;
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int shift;
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const char *parent;
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#define CLK_GATE_INVERTED (1 << 0)
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unsigned flags;
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};
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#define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
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static int clk_gate2_enable(struct clk *clk)
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{
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struct clk_gate2 *g = to_clk_gate2(clk);
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u32 val;
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val = readl(g->reg);
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if (g->flags & CLK_GATE_INVERTED)
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val &= ~(3 << g->shift);
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else
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val |= 3 << g->shift;
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writel(val, g->reg);
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return 0;
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}
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static void clk_gate2_disable(struct clk *clk)
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{
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struct clk_gate2 *g = to_clk_gate2(clk);
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u32 val;
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val = readl(g->reg);
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if (g->flags & CLK_GATE_INVERTED)
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val |= 3 << g->shift;
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else
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val &= ~(3 << g->shift);
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writel(val, g->reg);
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}
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static int clk_gate2_is_enabled(struct clk *clk)
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{
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struct clk_gate2 *g = to_clk_gate2(clk);
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u32 val;
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val = readl(g->reg);
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if (val & (1 << g->shift))
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return g->flags & CLK_GATE_INVERTED ? 0 : 1;
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else
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return g->flags & CLK_GATE_INVERTED ? 1 : 0;
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}
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static struct clk_ops clk_gate2_ops = {
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.enable = clk_gate2_enable,
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.disable = clk_gate2_disable,
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.is_enabled = clk_gate2_is_enabled,
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};
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struct clk *clk_gate2_alloc(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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struct clk_gate2 *g = xzalloc(sizeof(*g));
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g->parent = parent;
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g->reg = reg;
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g->shift = shift;
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g->clk.ops = &clk_gate2_ops;
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g->clk.name = name;
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g->clk.parent_names = &g->parent;
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g->clk.num_parents = 1;
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return &g->clk;
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}
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void clk_gate2_free(struct clk *clk)
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{
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struct clk_gate2 *g = to_clk_gate2(clk);
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free(g);
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}
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struct clk *clk_gate2(const char *name, const char *parent, void __iomem *reg,
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u8 shift)
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{
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struct clk *g;
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int ret;
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g = clk_gate2_alloc(name , parent, reg, shift);
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ret = clk_register(g);
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if (ret) {
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free(to_clk_gate2(g));
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return ERR_PTR(ret);
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}
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return g;
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}
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struct clk *clk_gate2_inverted(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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struct clk *clk;
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struct clk_gate2 *g;
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clk = clk_gate2(name, parent, reg, shift);
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if (IS_ERR(clk))
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return clk;
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g = to_clk_gate2(clk);
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g->flags = CLK_GATE_INVERTED;
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return clk;
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}
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@ -1,6 +1,9 @@
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#ifndef __IMX_CLK_H
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#define __IMX_CLK_H
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struct clk *clk_gate2(const char *name, const char *parent, void __iomem *reg,
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u8 shift);
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static inline struct clk *imx_clk_divider(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width)
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{
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@ -39,6 +42,12 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent,
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return clk_gate(name, parent, reg, shift, CLK_SET_RATE_PARENT, 0);
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}
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static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_gate2(name, parent, reg, shift);
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}
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struct clk *imx_clk_pllv1(const char *name, const char *parent,
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void __iomem *base);
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