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dts: update to v4.9-rc3 

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer 2016-11-15 09:02:29 +01:00
parent c580e8422c
commit 37beaba455
16 changed files with 80 additions and 65 deletions
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16
dts/Bindings/clock/uniphier-clock.txt
View File

@ -24,7 +24,7 @@ Example:
reg = <0x61840000 0x4000>;
clock {
compatible = "socionext,uniphier-ld20-clock";
compatible = "socionext,uniphier-ld11-clock";
#clock-cells = <1>;
};
@ -43,8 +43,8 @@ Provided clocks:
21: USB3 ch1 PHY1
Media I/O (MIO) clock
---------------------
Media I/O (MIO) clock, SD clock
-------------------------------
Required properties:
- compatible: should be one of the following:
@ -52,10 +52,10 @@ Required properties:
"socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
"socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
"socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
"socionext,uniphier-pro5-mio-clock" - for Pro5 SoC.
"socionext,uniphier-pxs2-mio-clock" - for PXs2/LD6b SoC.
"socionext,uniphier-pro5-sd-clock" - for Pro5 SoC.
"socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
"socionext,uniphier-ld20-mio-clock" - for LD20 SoC.
"socionext,uniphier-ld20-sd-clock" - for LD20 SoC.
- #clock-cells: should be 1.
Example:
@ -66,7 +66,7 @@ Example:
reg = <0x59810000 0x800>;
clock {
compatible = "socionext,uniphier-ld20-mio-clock";
compatible = "socionext,uniphier-ld11-mio-clock";
#clock-cells = <1>;
};
@ -112,7 +112,7 @@ Example:
reg = <0x59820000 0x200>;
clock {
compatible = "socionext,uniphier-ld20-peri-clock";
compatible = "socionext,uniphier-ld11-peri-clock";
#clock-cells = <1>;
};

62
dts/Bindings/reset/uniphier-reset.txt
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@ -6,25 +6,25 @@ System reset
Required properties:
- compatible: should be one of the following:
"socionext,uniphier-sld3-reset" - for PH1-sLD3 SoC.
"socionext,uniphier-ld4-reset" - for PH1-LD4 SoC.
"socionext,uniphier-pro4-reset" - for PH1-Pro4 SoC.
"socionext,uniphier-sld8-reset" - for PH1-sLD8 SoC.
"socionext,uniphier-pro5-reset" - for PH1-Pro5 SoC.
"socionext,uniphier-pxs2-reset" - for ProXstream2/PH1-LD6b SoC.
"socionext,uniphier-ld11-reset" - for PH1-LD11 SoC.
"socionext,uniphier-ld20-reset" - for PH1-LD20 SoC.
"socionext,uniphier-sld3-reset" - for sLD3 SoC.
"socionext,uniphier-ld4-reset" - for LD4 SoC.
"socionext,uniphier-pro4-reset" - for Pro4 SoC.
"socionext,uniphier-sld8-reset" - for sLD8 SoC.
"socionext,uniphier-pro5-reset" - for Pro5 SoC.
"socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-reset" - for LD11 SoC.
"socionext,uniphier-ld20-reset" - for LD20 SoC.
- #reset-cells: should be 1.
Example:
sysctrl@61840000 {
compatible = "socionext,uniphier-ld20-sysctrl",
compatible = "socionext,uniphier-ld11-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x4000>;
reset {
compatible = "socionext,uniphier-ld20-reset";
compatible = "socionext,uniphier-ld11-reset";
#reset-cells = <1>;
};
@ -32,30 +32,30 @@ Example:
};
Media I/O (MIO) reset
---------------------
Media I/O (MIO) reset, SD reset
-------------------------------
Required properties:
- compatible: should be one of the following:
"socionext,uniphier-sld3-mio-reset" - for PH1-sLD3 SoC.
"socionext,uniphier-ld4-mio-reset" - for PH1-LD4 SoC.
"socionext,uniphier-pro4-mio-reset" - for PH1-Pro4 SoC.
"socionext,uniphier-sld8-mio-reset" - for PH1-sLD8 SoC.
"socionext,uniphier-pro5-mio-reset" - for PH1-Pro5 SoC.
"socionext,uniphier-pxs2-mio-reset" - for ProXstream2/PH1-LD6b SoC.
"socionext,uniphier-ld11-mio-reset" - for PH1-LD11 SoC.
"socionext,uniphier-ld20-mio-reset" - for PH1-LD20 SoC.
"socionext,uniphier-sld3-mio-reset" - for sLD3 SoC.
"socionext,uniphier-ld4-mio-reset" - for LD4 SoC.
"socionext,uniphier-pro4-mio-reset" - for Pro4 SoC.
"socionext,uniphier-sld8-mio-reset" - for sLD8 SoC.
"socionext,uniphier-pro5-sd-reset" - for Pro5 SoC.
"socionext,uniphier-pxs2-sd-reset" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-mio-reset" - for LD11 SoC.
"socionext,uniphier-ld20-sd-reset" - for LD20 SoC.
- #reset-cells: should be 1.
Example:
mioctrl@59810000 {
compatible = "socionext,uniphier-ld20-mioctrl",
compatible = "socionext,uniphier-ld11-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
reset {
compatible = "socionext,uniphier-ld20-mio-reset";
compatible = "socionext,uniphier-ld11-mio-reset";
#reset-cells = <1>;
};
@ -68,24 +68,24 @@ Peripheral reset
Required properties:
- compatible: should be one of the following:
"socionext,uniphier-ld4-peri-reset" - for PH1-LD4 SoC.
"socionext,uniphier-pro4-peri-reset" - for PH1-Pro4 SoC.
"socionext,uniphier-sld8-peri-reset" - for PH1-sLD8 SoC.
"socionext,uniphier-pro5-peri-reset" - for PH1-Pro5 SoC.
"socionext,uniphier-pxs2-peri-reset" - for ProXstream2/PH1-LD6b SoC.
"socionext,uniphier-ld11-peri-reset" - for PH1-LD11 SoC.
"socionext,uniphier-ld20-peri-reset" - for PH1-LD20 SoC.
"socionext,uniphier-ld4-peri-reset" - for LD4 SoC.
"socionext,uniphier-pro4-peri-reset" - for Pro4 SoC.
"socionext,uniphier-sld8-peri-reset" - for sLD8 SoC.
"socionext,uniphier-pro5-peri-reset" - for Pro5 SoC.
"socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-peri-reset" - for LD11 SoC.
"socionext,uniphier-ld20-peri-reset" - for LD20 SoC.
- #reset-cells: should be 1.
Example:
perictrl@59820000 {
compatible = "socionext,uniphier-ld20-perictrl",
compatible = "socionext,uniphier-ld11-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
reset {
compatible = "socionext,uniphier-ld20-peri-reset";
compatible = "socionext,uniphier-ld11-peri-reset";
#reset-cells = <1>;
};

4
dts/Bindings/serial/cdns,uart.txt
View File

@ -1,7 +1,9 @@
Binding for Cadence UART Controller
Required properties:
- compatible : should be "cdns,uart-r1p8", or "xlnx,xuartps"
- compatible :
Use "xlnx,xuartps","cdns,uart-r1p8" for Zynq-7xxx SoC.
Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC.
- reg: Should contain UART controller registers location and length.
- interrupts: Should contain UART controller interrupts.
- clocks: Must contain phandles to the UART clocks

8
dts/Bindings/serial/renesas,sci-serial.txt
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@ -9,6 +9,14 @@ Required properties:
- "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART.
- "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART.
- "renesas,scifb-r8a7740" for R8A7740 (R-Mobile A1) SCIFB compatible UART.
- "renesas,scif-r8a7743" for R8A7743 (RZ/G1M) SCIF compatible UART.
- "renesas,scifa-r8a7743" for R8A7743 (RZ/G1M) SCIFA compatible UART.
- "renesas,scifb-r8a7743" for R8A7743 (RZ/G1M) SCIFB compatible UART.
- "renesas,hscif-r8a7743" for R8A7743 (RZ/G1M) HSCIF compatible UART.
- "renesas,scif-r8a7745" for R8A7745 (RZ/G1E) SCIF compatible UART.
- "renesas,scifa-r8a7745" for R8A7745 (RZ/G1E) SCIFA compatible UART.
- "renesas,scifb-r8a7745" for R8A7745 (RZ/G1E) SCIFB compatible UART.
- "renesas,hscif-r8a7745" for R8A7745 (RZ/G1E) HSCIF compatible UART.
- "renesas,scif-r8a7778" for R8A7778 (R-Car M1) SCIF compatible UART.
- "renesas,scif-r8a7779" for R8A7779 (R-Car H1) SCIF compatible UART.
- "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART.

5
dts/Bindings/usb/dwc2.txt
View File

@ -28,10 +28,7 @@ Refer to phy/phy-bindings.txt for generic phy consumer properties
- g-use-dma: enable dma usage in gadget driver.
- g-rx-fifo-size: size of rx fifo size in gadget mode.
- g-np-tx-fifo-size: size of non-periodic tx fifo size in gadget mode.
Deprecated properties:
- g-tx-fifo-size: size of periodic tx fifo per endpoint (except ep0)
in gadget mode.
- g-tx-fifo-size: size of periodic tx fifo per endpoint (except ep0) in gadget mode.
Example:

15
dts/src/arm/ste-snowball.dts
View File

@ -239,14 +239,25 @@
arm,primecell-periphid = <0x10480180>;
max-frequency = <100000000>;
bus-width = <4>;
cap-sd-highspeed;
cap-mmc-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
/* All direction control is used */
st,sig-dir-cmd;
st,sig-dir-dat0;
st,sig-dir-dat2;
st,sig-dir-dat31;
st,sig-pin-fbclk;
full-pwr-cycle;
vmmc-supply = <&ab8500_ldo_aux3_reg>;
vqmmc-supply = <&vmmci>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdi0_default_mode>;
pinctrl-1 = <&sdi0_sleep_mode>;
cd-gpios = <&gpio6 26 GPIO_ACTIVE_LOW>; // 218
/* GPIO218 MMC_CD */
cd-gpios = <&gpio6 26 GPIO_ACTIVE_LOW>;
status = "okay";
};
@ -549,7 +560,7 @@
/* VMMCI level-shifter enable */
snowball_cfg3 {
pins = "GPIO217_AH12";
ste,config = <&gpio_out_lo>;
ste,config = <&gpio_out_hi>;
};
/* VMMCI level-shifter voltage select */
snowball_cfg4 {

4
dts/src/arm/uniphier-pro5.dtsi
View File

@ -184,11 +184,11 @@
};
&mio_clk {
compatible = "socionext,uniphier-pro5-mio-clock";
compatible = "socionext,uniphier-pro5-sd-clock";
};
&mio_rst {
compatible = "socionext,uniphier-pro5-mio-reset";
compatible = "socionext,uniphier-pro5-sd-reset";
};
&peri_clk {

4
dts/src/arm/uniphier-pxs2.dtsi
View File

@ -197,11 +197,11 @@
};
&mio_clk {
compatible = "socionext,uniphier-pxs2-mio-clock";
compatible = "socionext,uniphier-pxs2-sd-clock";
};
&mio_rst {
compatible = "socionext,uniphier-pxs2-mio-reset";
compatible = "socionext,uniphier-pxs2-sd-reset";
};
&peri_clk {

2
dts/src/arm/vf500.dtsi
View File

@ -70,7 +70,7 @@
global_timer: timer@40002200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x40002200 0x20>;
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
interrupt-parent = <&intc>;
clocks = <&clks VF610_CLK_PLATFORM_BUS>;
};

2
dts/src/arm64/broadcom/ns2-svk.dts
View File

@ -164,6 +164,8 @@
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-bus-width = <16>;
brcm,nand-oob-sector-size = <16>;
#address-cells = <1>;
#size-cells = <1>;
};

1
dts/src/arm64/freescale/fsl-ls1043a.dtsi
View File

@ -123,6 +123,7 @@
<1 14 0xf08>, /* Physical Non-Secure PPI */
<1 11 0xf08>, /* Virtual PPI */
<1 10 0xf08>; /* Hypervisor PPI */
fsl,erratum-a008585;
};
pmu {

1
dts/src/arm64/freescale/fsl-ls2080a.dtsi
View File

@ -195,6 +195,7 @@
<1 14 4>, /* Physical Non-Secure PPI, active-low */
<1 11 4>, /* Virtual PPI, active-low */
<1 10 4>; /* Hypervisor PPI, active-low */
fsl,erratum-a008585;
};
pmu {

2
dts/src/arm64/marvell/armada-cp110-master.dtsi
View File

@ -131,7 +131,7 @@
#address-cells = <0x1>;
#size-cells = <0x0>;
cell-index = <1>;
clocks = <&cpm_syscon0 0 3>;
clocks = <&cpm_syscon0 1 21>;
status = "disabled";
};

3
dts/src/arm64/rockchip/rk3368-geekbox.dts
View File

@ -116,7 +116,6 @@
cap-mmc-highspeed;
clock-frequency = <150000000>;
disable-wp;
keep-power-in-suspend;
non-removable;
num-slots = <1>;
vmmc-supply = <&vcc_io>;
@ -258,8 +257,6 @@
};
vcc_sd: SWITCH_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_sd";
};

4
dts/src/arm64/rockchip/rk3368-orion-r68-meta.dts
View File

@ -152,8 +152,6 @@
gpio = <&gpio3 11 GPIO_ACTIVE_LOW>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_io>;
};
@ -201,7 +199,6 @@
bus-width = <8>;
cap-mmc-highspeed;
disable-wp;
keep-power-in-suspend;
mmc-pwrseq = <&emmc_pwrseq>;
mmc-hs200-1_2v;
mmc-hs200-1_8v;
@ -350,7 +347,6 @@
clock-freq-min-max = <400000 50000000>;
cap-sd-highspeed;
card-detect-delay = <200>;
keep-power-in-suspend;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;

12
dts/src/arm64/socionext/uniphier-ld20.dtsi
View File

@ -257,18 +257,18 @@
reg = <0x59801000 0x400>;
};
mioctrl@59810000 {
compatible = "socionext,uniphier-mioctrl",
sdctrl@59810000 {
compatible = "socionext,uniphier-ld20-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
mio_clk: clock {
compatible = "socionext,uniphier-ld20-mio-clock";
sd_clk: clock {
compatible = "socionext,uniphier-ld20-sd-clock";
#clock-cells = <1>;
};
mio_rst: reset {
compatible = "socionext,uniphier-ld20-mio-reset";
sd_rst: reset {
compatible = "socionext,uniphier-ld20-sd-reset";
#reset-cells = <1>;
};
};