* Patch by Greg Ungerer, 19 May 2005:
add support for the KS8695P (ARM 922 based) CPU * Patch by Steven Scholz, 19 May 2005: Add support for CONFIG_SERIAL_TAG on ARM boards
This commit is contained in:
wdenk
parent
7680c140af
commit
3a574cbe72
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@ -2,6 +2,13 @@
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Changes for U-Boot 1.1.3:
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======================================================================
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* Patches by Greg Ungerer, 19 May 2005:
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- add support for the KS8695P (ARM 922 based) CPU
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- add support for the OpenGear CM4008, CM4116 and CM4148 boards
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* Patch by Steven Scholz, 19 May 2005:
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Add support for CONFIG_SERIAL_TAG on ARM boards
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* Add PCI support for Sorcery board.
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Code cleanup (especially Sorcery / Alaska / Yukon serial driver).
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4
CREDITS
4
CREDITS
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@ -394,6 +394,10 @@ N: Rune Torgersen
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E: <runet@innovsys.com>
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D: Support for Motorola MPC8266ADS board
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N: Greg Ungerer
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E: greg.ungerer@opengear.com
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D: Support for ks8695 CPU, and OpenGear cmXXXX boards
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N: David Updegraff
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E: dave@cray.com
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D: Port to Cray L1 board; DHCP vendor extensions
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@ -413,6 +413,12 @@ Andrea Scian <andrea.scian@dave-tech.it>
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B2 ARM7TDMI (S3C44B0X)
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Greg Ungerer <greg.ungerer@opengear.com>
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cm4008 ks8695p
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cm4116 ks8695p
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cm4148 ks8695p
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Alex Züpke <azu@sysgo.de>
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lart SA1100
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@ -0,0 +1,43 @@
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#
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# (C) Copyright 2000-2005
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(SOC).a
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OBJS = interrupts.o serial.o
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SOBJS = lowlevel_init.o
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all: .depend $(LIB)
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS) $(SOBJS)
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#########################################################################
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.depend: Makefile $(OBJS:.o=.c)
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$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
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sinclude .depend
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#########################################################################
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@ -0,0 +1,112 @@
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/*
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* (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/platform.h>
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/*
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* Handy KS8695 register access functions.
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*/
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#define ks8695_read(a) *((volatile ulong *) (KS8695_IO_BASE + (a)))
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#define ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v)
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int timer_inited;
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ulong timer_ticks;
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int interrupt_init (void)
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{
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/* nothing happens here - we don't setup any IRQs */
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return (0);
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}
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/*
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* Initial timer set constants. Nothing complicated, just set for a 1ms
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* tick.
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*/
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#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_1)
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#define TIMER_COUNT (TIMER_INTERVAL / 2)
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#define TIMER_PULSE TIMER_COUNT
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void reset_timer_masked(void)
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{
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/* Set the hadware timer for 1ms */
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ks8695_write(KS8695_TIMER1, TIMER_COUNT);
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ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
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ks8695_write(KS8695_TIMER_CTRL, 0x2);
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timer_ticks = 0;
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timer_inited++;
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}
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void reset_timer(void)
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{
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reset_timer_masked();
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}
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ulong get_timer_masked(void)
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{
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/* Check for timer wrap */
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if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) {
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/* Clear interrupt condition */
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ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1);
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timer_ticks++;
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}
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return timer_ticks;
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}
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ulong get_timer(ulong base)
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{
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return (get_timer_masked() - base);
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}
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void set_timer(ulong t)
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{
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timer_ticks = t;
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}
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void udelay(ulong usec)
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{
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ulong start = get_timer_masked();
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ulong end;
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if (!timer_inited)
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reset_timer();
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/* Only 1ms resolution :-( */
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end = usec / 1000;
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while (get_timer(start) < end)
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;
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}
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void reset_cpu (ulong ignored)
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{
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ulong tc;
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/* Set timer0 to watchdog, and let it timeout */
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tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2;
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ks8695_write(KS8695_TIMER_CTRL, tc);
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ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff));
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ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1));
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/* Should only wait here till watchdog resets */
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for (;;)
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;
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}
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@ -0,0 +1,205 @@
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/*
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* lowlevel_init.S - basic hardware initialization for the KS8695 CPU
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*
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* Copyright (c) 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
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* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/arch/platform.h>
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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/*
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*************************************************************************
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*
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* Handy dandy macros
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*
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*************************************************************************
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*/
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/* Delay a bit */
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.macro DELAY_FOR cycles, reg0
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ldr \reg0, =\cycles
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subs \reg0, \reg0, #1
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subne pc, pc, #0xc
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.endm
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/*
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*************************************************************************
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*
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* Some local storage.
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*
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*************************************************************************
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*/
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/* Should we boot with an interactive console or not */
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.globl serial_console
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/*
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*************************************************************************
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*
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* Raw hardware initialization code. The important thing is to get
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* SDRAM setup and running. We do some other basic things here too,
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* like getting the PLL set for high speed, and init the LEDs.
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*
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*************************************************************************
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*/
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.globl lowlevel_init
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lowlevel_init:
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#if DEBUG
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/*
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* enable UART for early debug trace
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*/
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ldr r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
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mov r2, #0xd9
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str r2, [r1] /* 115200 baud */
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ldr r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
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mov r2, #0x03
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str r2, [r1] /* 8 data bits, no parity, 1 stop */
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ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
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mov r2, #0x41
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str r2, [r1] /* write 'A' */
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#endif
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#if DEBUG
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ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
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mov r2, #0x42
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str r2, [r1]
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#endif
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/*
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* remap the memory and flash regions. we want to end up with
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* ram from address 0, and flash at 32MB.
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*/
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ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0)
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ldr r2, =0xbfc00040
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str r2, [r1] /* large flash map */
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ldr pc, =(highflash+0x02000000-0x00f00000) /* jump to high flash address */
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highflash:
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ldr r2, =0x8fe00040
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str r2, [r1] /* remap flash range */
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/*
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* remap the second select region to the 4MB immediately after
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* the first region. This way if you have a larger flash (say 8Mb)
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* then you can have it all mapped nicely. Has no effect if you
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* only have a 4Mb or smaller flash.
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*/
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ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1)
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ldr r2, =0x9fe40040
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str r2, [r1] /* remap flash2 region, contiguous */
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ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
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ldr r2, =0x30000005
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str r2, [r1] /* enable both flash selects */
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#ifdef CONFIG_CM41xx
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/*
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* map the second flash chip, using the external IO lines.
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*/
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ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0)
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ldr r2, =0xafe80b6d
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str r2, [r1] /* remap io0 region, contiguous */
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ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1)
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ldr r2, =0xbfec0b6d
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str r2, [r1] /* remap io1 region, contiguous */
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ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
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ldr r2, =0x30050005
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str r2, [r1] /* enable second flash */
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#endif
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/*
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* before relocating, we have to setup RAM timing
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*/
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ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
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#if (PHYS_SDRAM_1_SIZE == 0x02000000)
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ldr r2, =0x7fc0000e /* 32MB */
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#else
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ldr r2, =0x3fc0000e /* 16MB */
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#endif
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str r2, [r1] /* configure sdram bank0 setup */
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ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
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mov r2, #0
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str r2, [r1] /* configure sdram bank1 setup */
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ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
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ldr r2, =0x0000000a
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str r2, [r1] /* set RAS/CAS timing */
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ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
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ldr r2, =0x00030000
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str r2, [r1] /* send NOP command */
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DELAY_FOR 0x100, r0
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ldr r2, =0x00010000
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str r2, [r1] /* send PRECHARGE-ALL */
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DELAY_FOR 0x100, r0
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ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH)
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ldr r2, =0x00000020
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str r2, [r1] /* set for fast refresh */
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DELAY_FOR 0x100, r0
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ldr r2, =0x00000190
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str r2, [r1] /* set normal refresh timing */
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ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
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ldr r2, =0x00020033
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str r2, [r1] /* send mode command */
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DELAY_FOR 0x100, r0
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ldr r2, =0x01f00000
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str r2, [r1] /* enable sdram fifos */
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/*
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* set pll to top speed
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*/
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ldr r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK)
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mov r2, #0
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str r2, [r1] /* set pll clock to 166MHz */
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ldr r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0)
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ldr r2, [r1] /* Get switch ctrl0 register */
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and r2, r2, #0x0fc00000 /* Mask out LED control bits */
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orr r2, r2, #0x01800000 /* Set Link/activity/speed actions */
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str r2, [r1]
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#ifdef CONFIG_CM4008
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ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE)
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ldr r2, =0x0000fe30
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str r2, [r1] /* enable LED's as outputs */
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ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA)
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ldr r2, =0x0000fe20
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str r2, [r1] /* turn on power LED */
|
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#endif
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#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx)
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ldr r2, [r1] /* get current GPIO input data */
|
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tst r2, #0x8 /* check if "erase" depressed */
|
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beq nobutton
|
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mov r2, #0 /* be quiet on boot, no console */
|
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ldr r1, =serial_console
|
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str r2, [r1]
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nobutton:
|
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#endif
|
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|
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add lr, lr, #0x02000000 /* flash is now mapped high */
|
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add ip, ip, #0x02000000 /* this is a hack */
|
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mov pc, lr /* all done, return */
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|
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
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|
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@ -0,0 +1,116 @@
|
|||
/*
|
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* serial.c -- KS8695 serial driver
|
||||
*
|
||||
* (C) Copyright 2004, Greg Ungerer <greg.ungerer@opengear.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
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#include <asm/arch/platform.h>
|
||||
|
||||
#ifndef CONFIG_SERIAL1
|
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#error "Bad: you didn't configure serial ..."
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Define the UART hardware register access structure.
|
||||
*/
|
||||
struct ks8695uart {
|
||||
unsigned int RX; /* 0x00 - Receive data (r) */
|
||||
unsigned int TX; /* 0x04 - Transmit data (w) */
|
||||
unsigned int FCR; /* 0x08 - Fifo Control (r/w) */
|
||||
unsigned int LCR; /* 0x0c - Line Control (r/w) */
|
||||
unsigned int MCR; /* 0x10 - Modem Control (r/w) */
|
||||
unsigned int LSR; /* 0x14 - Line Status (r/w) */
|
||||
unsigned int MSR; /* 0x18 - Modem Status (r/w) */
|
||||
unsigned int BD; /* 0x1c - Baud Rate (r/w) */
|
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unsigned int SR; /* 0x20 - Status (r/w) */
|
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};
|
||||
|
||||
#define KS8695_UART_ADDR ((void *) (KS8695_IO_BASE + KS8695_UART_RX_BUFFER))
|
||||
#define KS8695_UART_CLK 25000000
|
||||
|
||||
|
||||
/*
|
||||
* Under some circumstances we want to be "quiet" and not issue any
|
||||
* serial output - though we want u-boot to otherwise work and behave
|
||||
* the same. By default be noisy.
|
||||
*/
|
||||
int serial_console = 1;
|
||||
|
||||
|
||||
void serial_setbrg(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
|
||||
|
||||
/* Set to global baud rate and 8 data bits, no parity, 1 stop bit*/
|
||||
uartp->BD = KS8695_UART_CLK / gd->baudrate;
|
||||
uartp->LCR = KS8695_UART_LINEC_WLEN8;
|
||||
}
|
||||
|
||||
int serial_init(void)
|
||||
{
|
||||
serial_console = 1;
|
||||
serial_setbrg();
|
||||
return 0;
|
||||
}
|
||||
|
||||
void serial_raw_putc(const char c)
|
||||
{
|
||||
volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
|
||||
int i;
|
||||
|
||||
for (i = 0; (i < 0x100000); i++) {
|
||||
if (uartp->LSR & KS8695_UART_LINES_TXFE)
|
||||
break;
|
||||
}
|
||||
|
||||
uartp->TX = c;
|
||||
}
|
||||
|
||||
void serial_putc(const char c)
|
||||
{
|
||||
if (serial_console) {
|
||||
serial_raw_putc(c);
|
||||
if (c == '\n')
|
||||
serial_raw_putc('\r');
|
||||
}
|
||||
}
|
||||
|
||||
int serial_tstc(void)
|
||||
{
|
||||
volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
|
||||
if (serial_console)
|
||||
return ((uartp->LSR & KS8695_UART_LINES_RXFE) ? 1 : 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void serial_puts(const char *s)
|
||||
{
|
||||
char c;
|
||||
while ((c = *s++) != 0)
|
||||
serial_putc(c);
|
||||
}
|
||||
|
||||
int serial_getc(void)
|
||||
{
|
||||
volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
|
||||
|
||||
while ((uartp->LSR & KS8695_UART_LINES_RXFE) == 0)
|
||||
;
|
||||
return (uartp->RX);
|
||||
}
|
||||
|
|
@ -47,7 +47,8 @@ OBJS = 3c589.o 5701rls.o ali512x.o \
|
|||
status_led.o sym53c8xx.o \
|
||||
ti_pci1410a.o tigon3.o \
|
||||
usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \
|
||||
videomodes.o w83c553f.o
|
||||
videomodes.o w83c553f.o \
|
||||
ks8695eth.o
|
||||
|
||||
all: $(LIB)
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,236 @@
|
|||
/*
|
||||
* ks8695eth.c -- KS8695 ethernet driver
|
||||
*
|
||||
* (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/****************************************************************************/
|
||||
|
||||
#include <common.h>
|
||||
#include <malloc.h>
|
||||
#include <net.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/platform.h>
|
||||
|
||||
/****************************************************************************/
|
||||
|
||||
/*
|
||||
* Hardware register access to the KS8695 LAN ethernet port
|
||||
* (well, it is the 4 port switch really).
|
||||
*/
|
||||
#define ks8695_read(a) *((volatile unsigned long *) (KS8695_IO_BASE + (a)))
|
||||
#define ks8695_write(a,v) *((volatile unsigned long *) (KS8695_IO_BASE + (a))) = (v)
|
||||
|
||||
/****************************************************************************/
|
||||
|
||||
/*
|
||||
* Define the descriptor in-memory data structures.
|
||||
*/
|
||||
struct ks8695_txdesc {
|
||||
uint32_t owner;
|
||||
uint32_t ctrl;
|
||||
uint32_t addr;
|
||||
uint32_t next;
|
||||
};
|
||||
|
||||
struct ks8695_rxdesc {
|
||||
uint32_t status;
|
||||
uint32_t ctrl;
|
||||
uint32_t addr;
|
||||
uint32_t next;
|
||||
};
|
||||
|
||||
/****************************************************************************/
|
||||
|
||||
/*
|
||||
* Allocate local data structures to use for receiving and sending
|
||||
* packets. Just to keep it all nice and simple.
|
||||
*/
|
||||
|
||||
#define TXDESCS 4
|
||||
#define RXDESCS 4
|
||||
#define BUFSIZE 2048
|
||||
|
||||
volatile struct ks8695_txdesc ks8695_tx[TXDESCS] __attribute__((aligned(256)));
|
||||
volatile struct ks8695_rxdesc ks8695_rx[RXDESCS] __attribute__((aligned(256)));
|
||||
volatile uint8_t ks8695_bufs[BUFSIZE*(TXDESCS+RXDESCS)] __attribute__((aligned(2048)));;
|
||||
|
||||
/****************************************************************************/
|
||||
|
||||
/*
|
||||
* Ideally we want to use the MAC address stored in flash.
|
||||
* But we do some sanity checks in case they are not present
|
||||
* first.
|
||||
*/
|
||||
unsigned char eth_mac[] = {
|
||||
0x00, 0x13, 0xc6, 0x00, 0x00, 0x00
|
||||
};
|
||||
|
||||
void ks8695_getmac(void)
|
||||
{
|
||||
unsigned char *fp;
|
||||
int i;
|
||||
|
||||
/* Check if flash MAC is valid */
|
||||
fp = (unsigned char *) 0x0201c000;
|
||||
for (i = 0; (i < 6); i++) {
|
||||
if ((fp[i] != 0) && (fp[i] != 0xff))
|
||||
break;
|
||||
}
|
||||
|
||||
/* If we found a valid looking MAC address then use it */
|
||||
if (i < 6)
|
||||
memcpy(ð_mac[0], fp, 6);
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
|
||||
void eth_reset(bd_t *bd)
|
||||
{
|
||||
int i;
|
||||
|
||||
debug ("%s(%d): eth_reset()\n", __FILE__, __LINE__);
|
||||
|
||||
/* Reset the ethernet engines first */
|
||||
ks8695_write(KS8695_LAN_DMA_TX, 0x80000000);
|
||||
ks8695_write(KS8695_LAN_DMA_RX, 0x80000000);
|
||||
|
||||
ks8695_getmac();
|
||||
|
||||
/* Set MAC address */
|
||||
ks8695_write(KS8695_LAN_MAC_LOW, (eth_mac[5] | (eth_mac[4] << 8) |
|
||||
(eth_mac[3] << 16) | (eth_mac[2] << 24)));
|
||||
ks8695_write(KS8695_LAN_MAC_HIGH, (eth_mac[1] | (eth_mac[0] << 8)));
|
||||
|
||||
/* Turn the 4 port switch on */
|
||||
i = ks8695_read(KS8695_SWITCH_CTRL0);
|
||||
ks8695_write(KS8695_SWITCH_CTRL0, (i | 0x1));
|
||||
/* ks8695_write(KS8695_WAN_CONTROL, 0x3f000066); */
|
||||
|
||||
/* Initialize descriptor rings */
|
||||
for (i = 0; (i < TXDESCS); i++) {
|
||||
ks8695_tx[i].owner = 0;
|
||||
ks8695_tx[i].ctrl = 0;
|
||||
ks8695_tx[i].addr = (uint32_t) &ks8695_bufs[i*BUFSIZE];
|
||||
ks8695_tx[i].next = (uint32_t) &ks8695_tx[i+1];
|
||||
}
|
||||
ks8695_tx[TXDESCS-1].ctrl = 0x02000000;
|
||||
ks8695_tx[TXDESCS-1].next = (uint32_t) &ks8695_tx[0];
|
||||
|
||||
for (i = 0; (i < RXDESCS); i++) {
|
||||
ks8695_rx[i].status = 0x80000000;
|
||||
ks8695_rx[i].ctrl = BUFSIZE - 4;
|
||||
ks8695_rx[i].addr = (uint32_t) &ks8695_bufs[(i+TXDESCS)*BUFSIZE];
|
||||
ks8695_rx[i].next = (uint32_t) &ks8695_rx[i+1];
|
||||
}
|
||||
ks8695_rx[RXDESCS-1].ctrl |= 0x00080000;
|
||||
ks8695_rx[RXDESCS-1].next = (uint32_t) &ks8695_rx[0];
|
||||
|
||||
/* The KS8695 is pretty slow reseting the ethernets... */
|
||||
udelay(2000000);
|
||||
|
||||
/* Enable the ethernet engine */
|
||||
ks8695_write(KS8695_LAN_TX_LIST, (uint32_t) &ks8695_tx[0]);
|
||||
ks8695_write(KS8695_LAN_RX_LIST, (uint32_t) &ks8695_rx[0]);
|
||||
ks8695_write(KS8695_LAN_DMA_TX, 0x3);
|
||||
ks8695_write(KS8695_LAN_DMA_RX, 0x71);
|
||||
ks8695_write(KS8695_LAN_DMA_RX_START, 0x1);
|
||||
|
||||
printf("KS8695 ETHERNET: ");
|
||||
for (i = 0; (i < 5); i++) {
|
||||
bd->bi_enetaddr[i] = eth_mac[i];
|
||||
printf("%02x:", eth_mac[i]);
|
||||
}
|
||||
bd->bi_enetaddr[i] = eth_mac[i];
|
||||
printf("%02x\n", eth_mac[i]);
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
|
||||
int eth_init(bd_t *bd)
|
||||
{
|
||||
debug ("%s(%d): eth_init()\n", __FILE__, __LINE__);
|
||||
|
||||
eth_reset(bd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
|
||||
void eth_halt(void)
|
||||
{
|
||||
debug ("%s(%d): eth_halt()\n", __FILE__, __LINE__);
|
||||
|
||||
/* Reset the ethernet engines */
|
||||
ks8695_write(KS8695_LAN_DMA_TX, 0x80000000);
|
||||
ks8695_write(KS8695_LAN_DMA_RX, 0x80000000);
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
|
||||
int eth_rx(void)
|
||||
{
|
||||
volatile struct ks8695_rxdesc *dp;
|
||||
int i, len = 0;
|
||||
|
||||
debug ("%s(%d): eth_rx()\n", __FILE__, __LINE__);
|
||||
|
||||
for (i = 0; (i < RXDESCS); i++) {
|
||||
dp= &ks8695_rx[i];
|
||||
if ((dp->status & 0x80000000) == 0) {
|
||||
len = (dp->status & 0x7ff) - 4;
|
||||
NetReceive((void *) dp->addr, len);
|
||||
dp->status = 0x80000000;
|
||||
ks8695_write(KS8695_LAN_DMA_RX_START, 0x1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
|
||||
int eth_send(volatile void *packet, int len)
|
||||
{
|
||||
volatile struct ks8695_txdesc *dp;
|
||||
static int next = 0;
|
||||
|
||||
debug ("%s(%d): eth_send(packet=%x,len=%d)\n", __FILE__, __LINE__,
|
||||
packet, len);
|
||||
|
||||
dp = &ks8695_tx[next];
|
||||
memcpy((void *) dp->addr, packet, len);
|
||||
|
||||
if (len < 64) {
|
||||
memset(dp->addr+len, 0, 64-len);
|
||||
len = 64;
|
||||
}
|
||||
|
||||
dp->ctrl = len | 0xe0000000;
|
||||
dp->owner = 0x80000000;
|
||||
|
||||
ks8695_write(KS8695_LAN_DMA_TX, 0x3);
|
||||
ks8695_write(KS8695_LAN_DMA_TX_START, 0x1);
|
||||
|
||||
if (++next >= TXDESCS)
|
||||
next = 0;
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
|
|
@ -0,0 +1,306 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __address_h
|
||||
#define __address_h 1
|
||||
|
||||
#define KS8695_SDRAM_START 0x00000000
|
||||
#define KS8695_SDRAM_SIZE 0x01000000
|
||||
#define KS8695_MEM_SIZE KS8695_SDRAM_SIZE
|
||||
#define KS8695_MEM_START KS8695_SDRAM_START
|
||||
|
||||
#define KS8695_PCMCIA_IO_BASE 0x03800000
|
||||
#define KS8695_PCMCIA_IO_SIZE 0x00040000
|
||||
|
||||
#define KS8695_IO_BASE 0x03FF0000
|
||||
#define KS8695_IO_SIZE 0x00010000
|
||||
|
||||
#define KS8695_SYSTEN_CONFIG 0x00
|
||||
#define KS8695_SYSTEN_BUS_CLOCK 0x04
|
||||
|
||||
#define KS8695_FLASH_START 0x02800000
|
||||
#define KS8695_FLASH_SIZE 0x00400000
|
||||
|
||||
/*i/o control registers offset difinitions*/
|
||||
#define KS8695_IO_CTRL0 0x4000
|
||||
#define KS8695_IO_CTRL1 0x4004
|
||||
#define KS8695_IO_CTRL2 0x4008
|
||||
#define KS8695_IO_CTRL3 0x400C
|
||||
|
||||
/*memory control registers offset difinitions*/
|
||||
#define KS8695_MEM_CTRL0 0x4010
|
||||
#define KS8695_MEM_CTRL1 0x4014
|
||||
#define KS8695_MEM_CTRL2 0x4018
|
||||
#define KS8695_MEM_CTRL3 0x401C
|
||||
#define KS8695_MEM_GENERAL 0x4020
|
||||
#define KS8695_SDRAM_CTRL0 0x4030
|
||||
#define KS8695_SDRAM_CTRL1 0x4034
|
||||
#define KS8695_SDRAM_GENERAL 0x4038
|
||||
#define KS8695_SDRAM_BUFFER 0x403C
|
||||
#define KS8695_SDRAM_REFRESH 0x4040
|
||||
|
||||
/*WAN control registers offset difinitions*/
|
||||
#define KS8695_WAN_DMA_TX 0x6000
|
||||
#define KS8695_WAN_DMA_RX 0x6004
|
||||
#define KS8695_WAN_DMA_TX_START 0x6008
|
||||
#define KS8695_WAN_DMA_RX_START 0x600C
|
||||
#define KS8695_WAN_TX_LIST 0x6010
|
||||
#define KS8695_WAN_RX_LIST 0x6014
|
||||
#define KS8695_WAN_MAC_LOW 0x6018
|
||||
#define KS8695_WAN_MAC_HIGH 0x601C
|
||||
#define KS8695_WAN_MAC_ELOW 0x6080
|
||||
#define KS8695_WAN_MAC_EHIGH 0x6084
|
||||
|
||||
/*LAN control registers offset difinitions*/
|
||||
#define KS8695_LAN_DMA_TX 0x8000
|
||||
#define KS8695_LAN_DMA_RX 0x8004
|
||||
#define KS8695_LAN_DMA_TX_START 0x8008
|
||||
#define KS8695_LAN_DMA_RX_START 0x800C
|
||||
#define KS8695_LAN_TX_LIST 0x8010
|
||||
#define KS8695_LAN_RX_LIST 0x8014
|
||||
#define KS8695_LAN_MAC_LOW 0x8018
|
||||
#define KS8695_LAN_MAC_HIGH 0x801C
|
||||
#define KS8695_LAN_MAC_ELOW 0X8080
|
||||
#define KS8695_LAN_MAC_EHIGH 0X8084
|
||||
|
||||
/*HPNA control registers offset difinitions*/
|
||||
#define KS8695_HPNA_DMA_TX 0xA000
|
||||
#define KS8695_HPNA_DMA_RX 0xA004
|
||||
#define KS8695_HPNA_DMA_TX_START 0xA008
|
||||
#define KS8695_HPNA_DMA_RX_START 0xA00C
|
||||
#define KS8695_HPNA_TX_LIST 0xA010
|
||||
#define KS8695_HPNA_RX_LIST 0xA014
|
||||
#define KS8695_HPNA_MAC_LOW 0xA018
|
||||
#define KS8695_HPNA_MAC_HIGH 0xA01C
|
||||
#define KS8695_HPNA_MAC_ELOW 0xA080
|
||||
#define KS8695_HPNA_MAC_EHIGH 0xA084
|
||||
|
||||
/*UART control registers offset difinitions*/
|
||||
#define KS8695_UART_RX_BUFFER 0xE000
|
||||
#define KS8695_UART_TX_HOLDING 0xE004
|
||||
|
||||
#define KS8695_UART_FIFO_CTRL 0xE008
|
||||
#define KS8695_UART_FIFO_TRIG01 0x00
|
||||
#define KS8695_UART_FIFO_TRIG04 0x80
|
||||
#define KS8695_UART_FIFO_TXRST 0x03
|
||||
#define KS8695_UART_FIFO_RXRST 0x02
|
||||
#define KS8695_UART_FIFO_FEN 0x01
|
||||
|
||||
#define KS8695_UART_LINE_CTRL 0xE00C
|
||||
#define KS8695_UART_LINEC_BRK 0x40
|
||||
#define KS8695_UART_LINEC_EPS 0x10
|
||||
#define KS8695_UART_LINEC_PEN 0x08
|
||||
#define KS8695_UART_LINEC_STP2 0x04
|
||||
#define KS8695_UART_LINEC_WLEN8 0x03
|
||||
#define KS8695_UART_LINEC_WLEN7 0x02
|
||||
#define KS8695_UART_LINEC_WLEN6 0x01
|
||||
#define KS8695_UART_LINEC_WLEN5 0x00
|
||||
|
||||
#define KS8695_UART_MODEM_CTRL 0xE010
|
||||
#define KS8695_UART_MODEMC_RTS 0x02
|
||||
#define KS8695_UART_MODEMC_DTR 0x01
|
||||
|
||||
#define KS8695_UART_LINE_STATUS 0xE014
|
||||
#define KS8695_UART_LINES_TXFE 0x20
|
||||
#define KS8695_UART_LINES_BE 0x10
|
||||
#define KS8695_UART_LINES_FE 0x08
|
||||
#define KS8695_UART_LINES_PE 0x04
|
||||
#define KS8695_UART_LINES_OE 0x02
|
||||
#define KS8695_UART_LINES_RXFE 0x01
|
||||
#define KS8695_UART_LINES_ANY (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE)
|
||||
|
||||
#define KS8695_UART_MODEM_STATUS 0xE018
|
||||
#define KS8695_UART_MODEM_DCD 0x80
|
||||
#define KS8695_UART_MODEM_DSR 0x20
|
||||
#define KS8695_UART_MODEM_CTS 0x10
|
||||
#define KS8695_UART_MODEM_DDCD 0x08
|
||||
#define KS8695_UART_MODEM_DDSR 0x02
|
||||
#define KS8695_UART_MODEM_DCTS 0x01
|
||||
#define UART8695_MODEM_ANY 0xFF
|
||||
|
||||
#define KS8695_UART_DIVISOR 0xE01C
|
||||
#define KS8695_UART_STATUS 0xE020
|
||||
|
||||
/*Interrupt controlller registers offset difinitions*/
|
||||
#define KS8695_INT_CONTL 0xE200
|
||||
#define KS8695_INT_ENABLE 0xE204
|
||||
#define KS8695_INT_ENABLE_MODEM 0x0800
|
||||
#define KS8695_INT_ENABLE_ERR 0x0400
|
||||
#define KS8695_INT_ENABLE_RX 0x0200
|
||||
#define KS8695_INT_ENABLE_TX 0x0100
|
||||
|
||||
#define KS8695_INT_STATUS 0xE208
|
||||
#define KS8695_INT_WAN_PRIORITY 0xE20C
|
||||
#define KS8695_INT_HPNA_PRIORITY 0xE210
|
||||
#define KS8695_INT_LAN_PRIORITY 0xE214
|
||||
#define KS8695_INT_TIMER_PRIORITY 0xE218
|
||||
#define KS8695_INT_UART_PRIORITY 0xE21C
|
||||
#define KS8695_INT_EXT_PRIORITY 0xE220
|
||||
#define KS8695_INT_CHAN_PRIORITY 0xE224
|
||||
#define KS8695_INT_BUSERROR_PRO 0xE228
|
||||
#define KS8695_INT_MASK_STATUS 0xE22C
|
||||
#define KS8695_FIQ_PEND_PRIORITY 0xE230
|
||||
#define KS8695_IRQ_PEND_PRIORITY 0xE234
|
||||
|
||||
/*timer registers offset difinitions*/
|
||||
#define KS8695_TIMER_CTRL 0xE400
|
||||
#define KS8695_TIMER1 0xE404
|
||||
#define KS8695_TIMER0 0xE408
|
||||
#define KS8695_TIMER1_PCOUNT 0xE40C
|
||||
#define KS8695_TIMER0_PCOUNT 0xE410
|
||||
|
||||
/*GPIO registers offset difinitions*/
|
||||
#define KS8695_GPIO_MODE 0xE600
|
||||
#define KS8695_GPIO_CTRL 0xE604
|
||||
#define KS8695_GPIO_DATA 0xE608
|
||||
|
||||
/*SWITCH registers offset difinitions*/
|
||||
#define KS8695_SWITCH_CTRL0 0xE800
|
||||
#define KS8695_SWITCH_CTRL1 0xE804
|
||||
#define KS8695_SWITCH_PORT1 0xE808
|
||||
#define KS8695_SWITCH_PORT2 0xE80C
|
||||
#define KS8695_SWITCH_PORT3 0xE810
|
||||
#define KS8695_SWITCH_PORT4 0xE814
|
||||
#define KS8695_SWITCH_PORT5 0xE818
|
||||
#define KS8695_SWITCH_AUTO0 0xE81C
|
||||
#define KS8695_SWITCH_AUTO1 0xE820
|
||||
#define KS8695_SWITCH_LUE_CTRL 0xE824
|
||||
#define KS8695_SWITCH_LUE_HIGH 0xE828
|
||||
#define KS8695_SWITCH_LUE_LOW 0xE82C
|
||||
#define KS8695_SWITCH_ADVANCED 0xE830
|
||||
|
||||
#define KS8695_SWITCH_LPPM12 0xE874
|
||||
#define KS8695_SWITCH_LPPM34 0xE878
|
||||
|
||||
/*host communication registers difinitions*/
|
||||
#define KS8695_DSCP_HIGH 0xE834
|
||||
#define KS8695_DSCP_LOW 0xE838
|
||||
#define KS8695_SWITCH_MAC_HIGH 0xE83C
|
||||
#define KS8695_SWITCH_MAC_LOW 0xE840
|
||||
|
||||
/*miscellaneours registers difinitions*/
|
||||
#define KS8695_MANAGE_COUNTER 0xE844
|
||||
#define KS8695_MANAGE_DATA 0xE848
|
||||
#define KS8695_LAN12_POWERMAGR 0xE84C
|
||||
#define KS8695_LAN34_POWERMAGR 0xE850
|
||||
|
||||
#define KS8695_DEVICE_ID 0xEA00
|
||||
#define KS8695_REVISION_ID 0xEA04
|
||||
|
||||
#define KS8695_MISC_CONTROL 0xEA08
|
||||
#define KS8695_WAN_CONTROL 0xEA0C
|
||||
#define KS8695_WAN_POWERMAGR 0xEA10
|
||||
#define KS8695_WAN_PHY_CONTROL 0xEA14
|
||||
#define KS8695_WAN_PHY_STATUS 0xEA18
|
||||
|
||||
/* bus clock definitions*/
|
||||
#define KS8695_BUS_CLOCK_125MHZ 0x0
|
||||
#define KS8695_BUS_CLOCK_100MHZ 0x1
|
||||
#define KS8695_BUS_CLOCK_62MHZ 0x2
|
||||
#define KS8695_BUS_CLOCK_50MHZ 0x3
|
||||
#define KS8695_BUS_CLOCK_41MHZ 0x4
|
||||
#define KS8695_BUS_CLOCK_33MHZ 0x5
|
||||
#define KS8695_BUS_CLOCK_31MHZ 0x6
|
||||
#define KS8695_BUS_CLOCK_25MHZ 0x7
|
||||
|
||||
/* -------------------------------------------------------------------------------
|
||||
* definations for IRQ
|
||||
* -------------------------------------------------------------------------------*/
|
||||
|
||||
#define KS8695_INT_EXT_INT0 2
|
||||
#define KS8695_INT_EXT_INT1 3
|
||||
#define KS8695_INT_EXT_INT2 4
|
||||
#define KS8695_INT_EXT_INT3 5
|
||||
#define KS8695_INT_TIMERINT0 6
|
||||
#define KS8695_INT_TIMERINT1 7
|
||||
#define KS8695_INT_UART_TX 8
|
||||
#define KS8695_INT_UART_RX 9
|
||||
#define KS8695_INT_UART_LINE_ERR 10
|
||||
#define KS8695_INT_UART_MODEMS 11
|
||||
#define KS8695_INT_LAN_STOP_RX 12
|
||||
#define KS8695_INT_LAN_STOP_TX 13
|
||||
#define KS8695_INT_LAN_BUF_RX_STATUS 14
|
||||
#define KS8695_INT_LAN_BUF_TX_STATUS 15
|
||||
#define KS8695_INT_LAN_RX_STATUS 16
|
||||
#define KS8695_INT_LAN_TX_STATUS 17
|
||||
#define KS8695_INT_HPAN_STOP_RX 18
|
||||
#define KS8695_INT_HPNA_STOP_TX 19
|
||||
#define KS8695_INT_HPNA_BUF_RX_STATUS 20
|
||||
#define KS8695_INT_HPNA_BUF_TX_STATUS 21
|
||||
#define KS8695_INT_HPNA_RX_STATUS 22
|
||||
#define KS8695_INT_HPNA_TX_STATUS 23
|
||||
#define KS8695_INT_BUS_ERROR 24
|
||||
#define KS8695_INT_WAN_STOP_RX 25
|
||||
#define KS8695_INT_WAN_STOP_TX 26
|
||||
#define KS8695_INT_WAN_BUF_RX_STATUS 27
|
||||
#define KS8695_INT_WAN_BUF_TX_STATUS 28
|
||||
#define KS8695_INT_WAN_RX_STATUS 29
|
||||
#define KS8695_INT_WAN_TX_STATUS 30
|
||||
|
||||
#define KS8695_INT_UART KS8695_INT_UART_TX
|
||||
|
||||
/* -------------------------------------------------------------------------------
|
||||
* Interrupt bit positions
|
||||
*
|
||||
* -------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define KS8695_INTMASK_EXT_INT0 ( 1 << KS8695_INT_EXT_INT0 )
|
||||
#define KS8695_INTMASK_EXT_INT1 ( 1 << KS8695_INT_EXT_INT1 )
|
||||
#define KS8695_INTMASK_EXT_INT2 ( 1 << KS8695_INT_EXT_INT2 )
|
||||
#define KS8695_INTMASK_EXT_INT3 ( 1 << KS8695_INT_EXT_INT3 )
|
||||
#define KS8695_INTMASK_TIMERINT0 ( 1 << KS8695_INT_TIMERINT0 )
|
||||
#define KS8695_INTMASK_TIMERINT1 ( 1 << KS8695_INT_TIMERINT1 )
|
||||
#define KS8695_INTMASK_UART_TX ( 1 << KS8695_INT_UART_TX )
|
||||
#define KS8695_INTMASK_UART_RX ( 1 << KS8695_INT_UART_RX )
|
||||
#define KS8695_INTMASK_UART_LINE_ERR ( 1 << KS8695_INT_UART_LINE_ERR )
|
||||
#define KS8695_INTMASK_UART_MODEMS ( 1 << KS8695_INT_UART_MODEMS )
|
||||
#define KS8695_INTMASK_LAN_STOP_RX ( 1 << KS8695_INT_LAN_STOP_RX )
|
||||
#define KS8695_INTMASK_LAN_STOP_TX ( 1 << KS8695_INT_LAN_STOP_TX )
|
||||
#define KS8695_INTMASK_LAN_BUF_RX_STATUS ( 1 << KS8695_INT_LAN_BUF_RX_STATUS )
|
||||
#define KS8695_INTMASK_LAN_BUF_TX_STATUS ( 1 << KS8695_INT_LAN_BUF_TX_STATUS )
|
||||
#define KS8695_INTMASK_LAN_RX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS )
|
||||
#define KS8695_INTMASK_LAN_TX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS )
|
||||
#define KS8695_INTMASK_HPAN_STOP_RX ( 1 << KS8695_INT_HPAN_STOP_RX )
|
||||
#define KS8695_INTMASK_HPNA_STOP_TX ( 1 << KS8695_INT_HPNA_STOP_TX )
|
||||
#define KS8695_INTMASK_HPNA_BUF_RX_STATUS ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS )
|
||||
#define KS8695_INTMAKS_HPNA_BUF_TX_STATUS ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS
|
||||
#define KS8695_INTMASK_HPNA_RX_STATUS ( 1 << KS8695_INT_HPNA_RX_STATUS )
|
||||
#define KS8695_INTMASK_HPNA_TX_STATUS ( 1 << KS8695_INT_HPNA_TX_STATUS )
|
||||
#define KS8695_INTMASK_BUS_ERROR ( 1 << KS8695_INT_BUS_ERROR )
|
||||
#define KS8695_INTMASK_WAN_STOP_RX ( 1 << KS8695_INT_WAN_STOP_RX )
|
||||
#define KS8695_INTMASK_WAN_STOP_TX ( 1 << KS8695_INT_WAN_STOP_TX )
|
||||
#define KS8695_INTMASK_WAN_BUF_RX_STATUS ( 1 << KS8695_INT_WAN_BUF_RX_STATUS )
|
||||
#define KS8695_INTMASK_WAN_BUF_TX_STATUS ( 1 << KS8695_INT_WAN_BUF_TX_STATUS )
|
||||
#define KS8695_INTMASK_WAN_RX_STATUS ( 1 << KS8695_INT_WAN_RX_STATUS )
|
||||
#define KS8695_INTMASK_WAN_TX_STATUS ( 1 << KS8695_INT_WAN_TX_STATUS )
|
||||
|
||||
#define KS8695_SC_VALID_INT 0xFFFFFFFF
|
||||
#define MAXIRQNUM 31
|
||||
|
||||
/*
|
||||
* Timer definitions
|
||||
*
|
||||
* Use timer 1 & 2
|
||||
* (both run at 25MHz).
|
||||
*
|
||||
*/
|
||||
#define TICKS_PER_uSEC 25
|
||||
#define mSEC_1 1000
|
||||
#define mSEC_10 (mSEC_1 * 10)
|
||||
|
||||
#endif
|
||||
|
||||
/* END */
|
||||
|
|
@ -377,15 +377,30 @@ static void setup_videolfb_tag (gd_t *gd)
|
|||
}
|
||||
#endif /* CONFIG_VFD || CONFIG_LCD */
|
||||
|
||||
#ifdef CONFIG_SERIAL_TAG
|
||||
void setup_serial_tag (struct tag **tmp)
|
||||
{
|
||||
struct tag *params = *tmp;
|
||||
struct tag_serialnr serialnr;
|
||||
void get_board_serial(struct tag_serialnr *serialnr);
|
||||
|
||||
get_board_serial(&serialnr);
|
||||
params->hdr.tag = ATAG_SERIAL;
|
||||
params->hdr.size = tag_size (tag_serialnr);
|
||||
params->u.serialnr.low = serialnr.low;
|
||||
params->u.serialnr.high= serialnr.high;
|
||||
params = tag_next (params);
|
||||
*tmp = params;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_REVISION_TAG
|
||||
void setup_revision_tag(struct tag **in_params)
|
||||
{
|
||||
u32 rev = 0;
|
||||
#ifdef CONFIG_OMAP2420H4
|
||||
u32 get_board_rev(void);
|
||||
|
||||
rev = get_board_rev();
|
||||
#endif
|
||||
params->hdr.tag = ATAG_REVISION;
|
||||
params->hdr.size = tag_size (tag_revision);
|
||||
params->u.revision.rev = rev;
|
||||
|
|
|
|||
Loading…
Reference in New Issue