ARM/Samsung: add generic S3C6410 SoC specific functions
Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -2,5 +2,5 @@ obj-y += s3c-timer.o generic.o
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obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
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obj-lowlevel-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
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obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o clocks-s3c24xx.o mem-s3c24x0.o
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obj-$(CONFIG_ARCH_S3C64xx) += gpio-s3c64xx.o clocks-s3c64xx.o
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obj-$(CONFIG_ARCH_S3C64xx) += gpio-s3c64xx.o clocks-s3c64xx.o mem-s3c64xx.o
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obj-$(CONFIG_S3C_LOWLEVEL_INIT) += $(obj-lowlevel-y)
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@ -0,0 +1,40 @@
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/*
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* Copyright 2012 Juergen Beisert
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef INCLUDE_MACH_DEVICES_S3C64XX_H
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# define INCLUDE_MACH_DEVICES_S3C64XX_H
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#include <driver.h>
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#include <mach/s3c64xx-iomap.h>
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static inline void s3c64xx_add_uart1(void)
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{
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add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE,
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S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
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}
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static inline void s3c64xx_add_uart2(void)
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{
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add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART2_BASE,
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S3C_UART2_SIZE, IORESOURCE_MEM, NULL);
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}
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static inline void s3c64xx_add_uart3(void)
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{
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add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART3_BASE,
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S3C_UART3_SIZE, IORESOURCE_MEM, NULL);
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}
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#endif /* INCLUDE_MACH_DEVICES_S3C64XX_H */
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@ -41,3 +41,20 @@ void s3c24xx_disable_second_sdram_bank(void);
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#ifdef CONFIG_ARCH_S5PCxx
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void s5p_init_pll(void);
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#endif
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#ifdef CONFIG_ARCH_S3C64xx
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unsigned s3c_set_epllclk(unsigned, unsigned, unsigned, unsigned);
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uint32_t s3c_get_epllclk(void);
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unsigned s3c_get_hsmmc_clk(int);
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void s3c_set_hsmmc_clk(int, int, unsigned);
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unsigned s3c6410_get_memory_size(void);
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struct s3c6410_chipselect {
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unsigned adr_setup_t; /* in [ns] */
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unsigned access_setup_t; /* in [ns] */
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unsigned access_t; /* in [ns] */
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unsigned cs_hold_t; /* in [ns] */
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unsigned adr_hold_t; /* in [ns] */
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unsigned char width; /* 8 or 16 */
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};
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int s3c6410_setup_chipselect(int, const struct s3c6410_chipselect*);
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#endif
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@ -0,0 +1,66 @@
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/*
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* Copyright (C) 2012 Juergen Beisert
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <errno.h>
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#include <io.h>
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#include <mach/s3c-iomap.h>
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#include <mach/s3c-generic.h>
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#define S3C_DRAMC_CHIP_0_CFG (S3C_DRAMC + 0x200)
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/* note: this routine honors the first memory bank only */
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unsigned s3c6410_get_memory_size(void)
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{
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unsigned reg = readl(S3C_DRAMC_CHIP_0_CFG) & 0xff;
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return ~(reg << 24) + 1;
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}
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/* configure the timing of one of the available external chip select lines */
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int s3c6410_setup_chipselect(int no, const struct s3c6410_chipselect *c)
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{
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unsigned per_t = 1000000000 / s3c_get_hclk();
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unsigned tacs, tcos, tacc, tcoh, tcah, shift;
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uint32_t reg;
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/* start of cycle to chip select assertion (= address/data setup) */
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tacs = DIV_ROUND_UP(c->adr_setup_t, per_t);
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/* start of CS to read/write assertion (= access setup) */
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tcos = DIV_ROUND_UP(c->access_setup_t, per_t);
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/* length of read/write assertion (= access lenght) */
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tacc = DIV_ROUND_UP(c->access_t, per_t) - 1;
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/* CS hold after access is finished */
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tcoh = DIV_ROUND_UP(c->cs_hold_t, per_t);
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/* adress/data hold after CS is deasserted */
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tcah = DIV_ROUND_UP(c->adr_hold_t, per_t);
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shift = no * 4;
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reg = readl(S3C_SROM_BW) & ~(0xf << shift);
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if (c->width == 16)
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reg |= 0x1 << shift;
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writel(reg, S3C_SROM_BW);
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#ifdef DEBUG
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if (tacs > 15 || tcos > 15 || tacc > 31 || tcoh > 15 || tcah > 15) {
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pr_err("At least one of the timings are invalid\n");
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return -EINVAL;
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}
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pr_info("Will write 0x%08X\n", tacs << 28 | tcos << 24 | tacc << 16 |
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tcoh << 12 | tcah << 8);
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#endif
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writel(tacs << 28 | tcos << 24 | tacc << 16 | tcoh << 12 | tcah << 8,
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S3C_SROM_BC0 + shift);
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return 0;
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}
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