tegra: fix MESLECT clock enable
Don't disable clk to unrelated devices in the process. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -31,3 +31,5 @@
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#define CRC_RST_DEV_V_MSELECT (1 << 3)
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#define CRC_RST_DEV_V_CLR 0x434
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#define CRC_CLK_OUT_ENB_V_SET 0x440
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@ -177,7 +177,7 @@ static void start_cpu0_clocks(void)
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CRC_CLK_SOURCE_MSEL_SRC_SHIFT),
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TEGRA_CLK_RESET_BASE + CRC_CLK_SOURCE_MSEL);
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writel(CRC_CLK_OUT_ENB_V_MSELECT,
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TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_V);
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TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_V_SET);
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tegra_ll_delay_usec(3);
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writel(CRC_RST_DEV_V_MSELECT,
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TEGRA_CLK_RESET_BASE + CRC_RST_DEV_V_CLR);
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