ARM: Add ELTEC HiPerCam board support
This adds support for the i.MX6 based Eltec HiPerCam board. This board comes with different i.MX6 flavours and different memory sizes. Currently supported is the i.MX6dl version with 256MB DDR3 RAM. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
5967f594af
commit
3da922bb1b
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@ -37,6 +37,7 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += eukrea_cpuimx25/
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obj-$(CONFIG_MACH_EUKREA_CPUIMX27) += eukrea_cpuimx27/
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obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += eukrea_cpuimx35/
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obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += eukrea_cpuimx51/
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obj-$(CONFIG_MACH_ELTEC_HIPERCAM) += eltec-hipercam/
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obj-$(CONFIG_MACH_FREESCALE_MX25_3STACK) += freescale-mx25-3ds/
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obj-$(CONFIG_MACH_FREESCALE_MX35_3STACK) += freescale-mx35-3ds/
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obj-$(CONFIG_MACH_FREESCALE_MX51_PDK) += freescale-mx51-babbage/
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@ -0,0 +1,2 @@
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lwl-y += lowlevel.o
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obj-y += board.o
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@ -0,0 +1,31 @@
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/*
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* Copyright (C) 2015 Sascha Hauer <s.hauer@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <bbu.h>
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#include <mach/bbu.h>
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static int hipercam_init(void)
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{
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if (!of_machine_is_compatible("eltec,hipercam-rev01"))
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return 0;
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imx6_bbu_internal_spi_i2c_register_handler("nor", "/dev/m25p0.barebox",
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BBU_HANDLER_FLAG_DEFAULT);
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return 0;
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}
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device_initcall(hipercam_init);
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@ -0,0 +1,105 @@
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soc imx6
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loadaddr 0x10000000
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wm 32 0x020e04bc 0x00000030
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wm 32 0x020e04c0 0x00000030
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wm 32 0x020e04c4 0x00000030
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wm 32 0x020e04c8 0x00000030
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wm 32 0x020e04cc 0x00000030
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wm 32 0x020e04d0 0x00000030
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wm 32 0x020e04d4 0x00000030
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wm 32 0x020e04d8 0x00000030
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wm 32 0x020e0764 0x00000030
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wm 32 0x020e0770 0x00000030
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wm 32 0x020e0778 0x00000030
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wm 32 0x020e077c 0x00000030
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wm 32 0x020e0780 0x00000030
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wm 32 0x020e0784 0x00000030
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wm 32 0x020e078c 0x00000030
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wm 32 0x020e0748 0x00000030
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wm 32 0x020e074c 0x00000030
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wm 32 0x020e076c 0x00000030
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wm 32 0x020e0470 0x00020030
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wm 32 0x020e0474 0x00020030
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wm 32 0x020e0478 0x00020030
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wm 32 0x020e047c 0x00020030
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wm 32 0x020e0480 0x00020030
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wm 32 0x020e0484 0x00020030
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wm 32 0x020e0488 0x00020030
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wm 32 0x020e048c 0x00020030
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wm 32 0x020e0464 0x00020030
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wm 32 0x020e0490 0x00020030
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wm 32 0x020e04ac 0x00020030
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wm 32 0x020e04b0 0x00020030
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wm 32 0x020e0494 0x00020030
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wm 32 0x020e04a4 0x00003000
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wm 32 0x020e04a8 0x00003000
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wm 32 0x020e04b4 0x00003030
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wm 32 0x020e04b8 0x00003030
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wm 32 0x020e0750 0x00020000
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wm 32 0x020e0760 0x00020000
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wm 32 0x020e0754 0x00000000
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wm 32 0x020e04a0 0x00000000
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wm 32 0x020e0774 0x000c0000
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wm 32 0x021b081c 0x33333333
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wm 32 0x021b0820 0x33333333
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wm 32 0x021b0824 0x33333333
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wm 32 0x021b0828 0x33333333
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wm 32 0x021b481c 0x33333333
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wm 32 0x021b4820 0x33333333
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wm 32 0x021b4824 0x33333333
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wm 32 0x021b4828 0x33333333
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wm 32 0x021b0018 0x00081740
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wm 32 0x021b001c 0x00008000
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wm 32 0x021b0004 0x0002002d
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wm 32 0x021b000c 0x8c435323
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wm 32 0x021b0010 0xb66e8d63
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wm 32 0x021b0014 0x01ff00db
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wm 32 0x021b002c 0x000026d2
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wm 32 0x021b0030 0x00431023
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wm 32 0x021b0008 0x00333030
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wm 32 0x021b0004 0x0002556d
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wm 32 0x021b0040 0x00000027
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wm 32 0x021b0000 0xc4190000
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wm 32 0x021b001c 0x04008032
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wm 32 0x021b001c 0x0400803a
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wm 32 0x021b001c 0x00008033
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wm 32 0x021b001c 0x0000803b
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wm 32 0x021b001c 0x00048031
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wm 32 0x021b001c 0x00048039
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wm 32 0x021b001c 0x13208030
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wm 32 0x021b001c 0x13208038
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wm 32 0x021b001c 0x04008040
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wm 32 0x021b001c 0x04008048
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wm 32 0x021b0800 0xa1390003
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wm 32 0x021b4800 0xa1390003
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wm 32 0x021b0020 0x00005800
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wm 32 0x021b0818 0x00022227
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wm 32 0x021b4818 0x00022227
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wm 32 0x021b083c 0x42350231
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wm 32 0x021b483c 0x42350231
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wm 32 0x021b0840 0x021a0218
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wm 32 0x021b4840 0x021a0218
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wm 32 0x021b0848 0x4b4b4e49
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wm 32 0x021b4848 0x4b4b4e49
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wm 32 0x021b0850 0x3f3f3035
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wm 32 0x021b4850 0x3f3f3035
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wm 32 0x021b080c 0x0040003c
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wm 32 0x021b0810 0x0032003e
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wm 32 0x021b480c 0x0040003c
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wm 32 0x021b4810 0x0032003e
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wm 32 0x021b08b8 0x00000800
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wm 32 0x021b48b8 0x00000800
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wm 32 0x021b001c 0x00000000
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wm 32 0x021b0404 0x00011006
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wm 32 0x020c4068 0x00c03f3f
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wm 32 0x020c406c 0x0030fc03
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wm 32 0x020c4070 0x0fffc000
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wm 32 0x020c4074 0x3ff00000
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wm 32 0x020c4078 0x00fff300
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wm 32 0x020c407c 0x0f0000c3
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wm 32 0x020c4080 0x000003ff
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wm 32 0x020e0010 0xf00000cf
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wm 32 0x020e0018 0x007f007f
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wm 32 0x020e001c 0x007f007f
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wm 32 0x020c4060 0x000000fb
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@ -0,0 +1,56 @@
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/*
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* Copyright (C) 2015 Sascha Hauer <s.hauer@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <linux/sizes.h>
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#include <io.h>
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#include <debug_ll.h>
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#include <asm/sections.h>
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#include <asm/mmu.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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#include <mach/generic.h>
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static void setup_uart(void)
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{
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void __iomem *uart_base = (void *)0x02020000;
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writel(0x1, 0x020e0330);
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writel(0x00000000, uart_base + 0x80);
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writel(0x00004027, uart_base + 0x84);
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writel(0x00000704, uart_base + 0x88);
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writel(0x00000a81, uart_base + 0x90);
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writel(0x0000002b, uart_base + 0x9c);
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writel(0x00013880, uart_base + 0xb0);
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writel(0x0000047f, uart_base + 0xa4);
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writel(0x0000c34f, uart_base + 0xa8);
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writel(0x00000001, uart_base + 0x80);
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putc_ll('>');
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}
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extern char __dtb_imx6dl_eltec_hipercam_start[];
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ENTRY_FUNCTION(start_imx6dl_eltec_hipercam, r0, r1, r2)
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{
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void *fdt;
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imx6_cpu_lowlevel_init();
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arm_setup_stack(0x00940000 - 8);
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setup_uart();
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fdt = __dtb_imx6dl_eltec_hipercam_start - get_runtime_offset();
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barebox_arm_entry(0x10000000, SZ_256M, fdt);
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}
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@ -12,6 +12,7 @@ CONFIG_MACH_DFI_FS700_M60=y
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CONFIG_MACH_GUF_SANTARO=y
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CONFIG_MACH_REALQ7=y
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CONFIG_MACH_GK802=y
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CONFIG_MACH_ELTEC_HIPERCAM=y
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CONFIG_MACH_TQMA6X=y
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CONFIG_MACH_TX6X=y
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CONFIG_MACH_SABRELITE=y
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@ -12,6 +12,7 @@ pbl-dtb-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o am
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pbl-dtb-$(CONFIG_MACH_DFI_FS700_M60) += imx6q-dfi-fs700-m60-6q.dtb.o imx6dl-dfi-fs700-m60-6s.dtb.o
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pbl-dtb-$(CONFIG_MACH_DUCKBILL) += imx28-duckbill.dtb.o
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pbl-dtb-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += imx51-genesi-efika-sb.dtb.o
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pbl-dtb-$(CONFIG_MACH_ELTEC_HIPERCAM) += imx6dl-eltec-hipercam.dtb.o
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pbl-dtb-$(CONFIG_MACH_EMBEST_RIOTBOARD) += imx6s-riotboard.dtb.o
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pbl-dtb-$(CONFIG_MACH_EMBEDSKY_E9) += imx6q-embedsky-e9.dtb.o
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pbl-dtb-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o
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@ -0,0 +1,324 @@
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/dts-v1/;
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#include "imx6dl.dtsi"
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/ {
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model = "ELTEC HiPerCam";
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compatible = "eltec,hipercam-rev01", "fsl,imx6dl";
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memory {
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reg = <0x10000000 0x10000000>;
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};
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chosen {
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stdout-path = &uart1;
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environment@0 {
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compatible = "barebox,environment";
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device-path = &norflash0, "partname:bareboxenv";
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};
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};
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};
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&ecspi1 {
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status = "okay";
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fsl,spi-num-chipselects = <2>;
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pinctrl-names = "default";
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cs-gpios = <&gpio2 30 0 &gpio3 19 0>;
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pinctrl-0 = <&pinctrl_ecspi1>;
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norflash0: s25fl129p1@0 {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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compatible = "st,s25fl129p1";
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spi-max-frequency = <20000000>;
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reg = <0x0>;
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partition@0 {
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label = "barebox";
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reg = <0x0 0xc0000>;
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};
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partition@1 {
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label = "bareboxenv";
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reg = <0xc0000 0x8000>;
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};
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partition@2 {
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label = "persistent";
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reg = <0x100000 0xf00000>;
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};
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};
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norflash1: s25fl129p1@1 {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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compatible = "st,s25fl129p1";
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spi-max-frequency = <20000000>;
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reg = <0x1>;
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partition@0 {
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label = "Linux";
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reg = <0x0 0x1000000>;
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};
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};
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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};
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&pcie {
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status = "okay";
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reset-gpio = <&gpio7 12 0x0>;
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};
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&usdhc3 {
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bus-width = <0x4>;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc3>;
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cd-gpios = <&gpio2 2 0>;
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wp-gpios = <&gpio2 1 0>;
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no-1-8-v;
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};
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&i2c2 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <0x20>;
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eeprom@0x52 {
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compatible = "amtel,24c04";
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reg = <0x52>;
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pagesize = <0x10>;
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};
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pfuze100@08 {
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compatible = "fsl,pfuze100";
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reg = <0x8>;
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regulators {
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sw1ab {
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regulator-min-microvolt = <0x493e0>;
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regulator-max-microvolt = <0x1c9c38>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <0x186a>;
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};
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sw1c {
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regulator-min-microvolt = <0x493e0>;
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regulator-max-microvolt = <0x1c9c38>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <0x186a>;
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};
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sw2 {
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regulator-min-microvolt = <0xc3500>;
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regulator-max-microvolt = <0x325aa0>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw3a {
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regulator-min-microvolt = <0x61a80>;
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regulator-max-microvolt = <0x1e22d8>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw3b {
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regulator-min-microvolt = <0x61a80>;
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regulator-max-microvolt = <0x1e22d8>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw4 {
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regulator-min-microvolt = <0xc3500>;
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regulator-max-microvolt = <0x325aa0>;
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};
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swbst {
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regulator-min-microvolt = <0x4c4b40>;
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regulator-max-microvolt = <0x4e9530>;
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};
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vsnvs {
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regulator-min-microvolt = <0xf4240>;
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regulator-max-microvolt = <0x2dc6c0>;
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regulator-boot-on;
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regulator-always-on;
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};
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vrefddr {
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regulator-boot-on;
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regulator-always-on;
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};
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vgen1 {
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regulator-min-microvolt = <0xc3500>;
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regulator-max-microvolt = <0x17a6b0>;
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};
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vgen2 {
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regulator-min-microvolt = <0xc3500>;
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regulator-max-microvolt = <0x17a6b0>;
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};
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vgen3 {
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regulator-min-microvolt = <0x1b7740>;
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regulator-max-microvolt = <0x325aa0>;
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};
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vgen4 {
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regulator-min-microvolt = <0x1b7740>;
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regulator-max-microvolt = <0x325aa0>;
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regulator-always-on;
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};
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vgen5 {
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regulator-min-microvolt = <0x1b7740>;
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regulator-max-microvolt = <0x325aa0>;
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regulator-always-on;
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};
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vgen6 {
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regulator-min-microvolt = <0x1b7740>;
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regulator-max-microvolt = <0x325aa0>;
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regulator-always-on;
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};
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};
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};
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};
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&i2c1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <0x1d>;
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||||
|
||||
mt9p031@48 {
|
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compatible = "aptina,mt9p031";
|
||||
reg = <0x48>;
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_cam>;
|
||||
csi_id = <0x0>;
|
||||
clocks = <&clks 201>;
|
||||
clock-names = "csi_mclk";
|
||||
rst-gpios = <&gpio5 22 0>;
|
||||
data-enable-gpios = <&gpio5 20 0x0>;
|
||||
mclk = <12000000>;
|
||||
mclk_source = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx6dl-eltec-hipercam {
|
||||
pinctrl_ecspi1: ecspi1 {
|
||||
fsl,pins = <MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
|
||||
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
|
||||
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
|
||||
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1
|
||||
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1 {
|
||||
fsl,pins = <MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
|
||||
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2 {
|
||||
fsl,pins = <MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3 {
|
||||
fsl,pins = <MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1 {
|
||||
fsl,pins = <MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1 {
|
||||
fsl,pins = <MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3 {
|
||||
fsl,pins = <MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hog: hog {
|
||||
fsl,pins = <MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
|
||||
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
|
||||
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
|
||||
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
|
||||
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
|
||||
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
|
||||
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000
|
||||
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
|
||||
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
|
||||
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
|
||||
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000
|
||||
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000
|
||||
MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
|
||||
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
|
||||
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
|
||||
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
|
||||
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
|
||||
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
|
||||
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
|
||||
MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000
|
||||
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
|
||||
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
|
||||
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
|
||||
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
|
||||
MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x80000000
|
||||
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000
|
||||
MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000
|
||||
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_cam: cam {
|
||||
fsl,pins = <MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
|
||||
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x80000000
|
||||
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
|
||||
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
|
||||
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -279,6 +279,10 @@ config MACH_GK802
|
|||
bool "Zealz GK802 Mini PC"
|
||||
select ARCH_IMX6
|
||||
|
||||
config MACH_ELTEC_HIPERCAM
|
||||
bool "ELTEC HiPerCam"
|
||||
select ARCH_IMX6
|
||||
|
||||
config MACH_TQMA6X
|
||||
bool "TQ tqma6x on mba6x"
|
||||
select ARCH_IMX6
|
||||
|
|
|
|||
|
|
@ -234,3 +234,8 @@ pblx-$(CONFIG_MACH_GW_VENTANA) += start_imx6q_gw54xx_1gx64
|
|||
CFG_start_imx6q_gw54xx_1gx64.pblx.imximg = $(board)/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg
|
||||
FILE_barebox-gateworks-imx6q-ventana-1gx64.img = start_imx6q_gw54xx_1gx64.pblx.imximg
|
||||
image-$(CONFIG_MACH_GW_VENTANA) += barebox-gateworks-imx6q-ventana-1gx64.img
|
||||
|
||||
pblx-$(CONFIG_MACH_ELTEC_HIPERCAM) += start_imx6dl_eltec_hipercam
|
||||
CFG_start_imx6dl_eltec_hipercam.pblx.imximg = $(board)/eltec-hipercam/flash-header-eltec-hipercam.imxcfg
|
||||
FILE_barebox-eltec-hipercam.img = start_imx6dl_eltec_hipercam.pblx.imximg
|
||||
image-$(CONFIG_MACH_ELTEC_HIPERCAM) += barebox-eltec-hipercam.img
|
||||
|
|
|
|||
Loading…
Reference in New Issue