MACH SAMSUNG/S3C: Re-work the GPIO handling for S3C24xx CPUs
a) use the more CPU specific S3C* macro names b) move the register description out of the way, as more recent CPUs using a different layout and more features Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Juergen Beisert
Sascha Hauer
parent
59994faae6
commit
3ee217a69c
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@ -36,6 +36,7 @@
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#include <mach/s3c24xx-nand.h>
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#include <mach/s3c-generic.h>
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#include <mach/s3c-busctl.h>
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#include <mach/s3c24xx-gpio.h>
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// {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
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static struct s3c24x0_nand_platform_data nand_info = {
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@ -53,29 +54,29 @@ static int a9m2410_mem_init(void)
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size = s3c24xx_get_memory_size();
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/* ---------- configure the GPIOs ------------- */
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writel(0x007FFFFF, GPACON);
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writel(0x00000000, GPCCON);
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writel(0x00000000, GPCUP);
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writel(0x00000000, GPDCON);
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writel(0x00000000, GPDUP);
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writel(0xAAAAAAAA, GPECON);
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writel(0x0000E03F, GPEUP);
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writel(0x00000000, GPBCON); /* all inputs */
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writel(0x00000007, GPBUP); /* pullup disabled for GPB0..3 */
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writel(0x00009000, GPFCON); /* GPF7 CLK_INT#, GPF6 Debug-LED */
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writel(0x000000FF, GPFUP);
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writel(readl(GPGDAT) | 0x0010, GPGDAT); /* switch off LCD backlight */
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writel(0xFF00A938, GPGCON); /* switch off USB device */
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writel(0x0000F000, GPGUP);
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writel(readl(GPHDAT) | 0x100, GPHDAT); /* switch BOOTINT/GPIO_ON# to high */
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writel(0x000007FF, GPHUP);
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writel(0x0029FAAA, GPHCON);
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writel(0x007FFFFF, S3C_GPACON);
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writel(0x00000000, S3C_GPCCON);
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writel(0x00000000, S3C_GPCUP);
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writel(0x00000000, S3C_GPDCON);
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writel(0x00000000, S3C_GPDUP);
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writel(0xAAAAAAAA, S3C_GPECON);
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writel(0x0000E03F, S3C_GPEUP);
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writel(0x00000000, S3C_GPBCON); /* all inputs */
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writel(0x00000007, S3C_GPBUP); /* pullup disabled for GPB0..3 */
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writel(0x00009000, S3C_GPFCON); /* GPF7 CLK_INT#, GPF6 Debug-LED */
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writel(0x000000FF, S3C_GPFUP);
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writel(readl(S3C_GPGDAT) | 0x0010, S3C_GPGDAT); /* switch off LCD backlight */
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writel(0xFF00A938, S3C_GPGCON); /* switch off USB device */
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writel(0x0000F000, S3C_GPGUP);
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writel(readl(S3C_GPHDAT) | 0x100, S3C_GPHDAT); /* switch BOOTINT/GPIO_ON# to high */
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writel(0x000007FF, S3C_GPHUP);
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writel(0x0029FAAA, S3C_GPHCON);
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/*
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* USB port1 normal, USB port0 normal, USB1 pads for device
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* PCLK output on CLKOUT0, UPLL CLK output on CLKOUT1,
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* 2nd SDRAM bank off (only bank 1 is used)
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*/
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writel(0x40140, MISCCR);
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writel(0x40140, S3C_MISCCR);
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arm_add_mem_device("ram0", S3C_SDRAM_BASE, size);
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@ -103,9 +104,9 @@ static int a9m2410_devices_init(void)
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writel(reg, S3C_BWSCON);
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/* release the reset signal to the network and UART device */
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reg = readl(MISCCR);
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reg = readl(S3C_MISCCR);
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reg |= 0x10000;
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writel(reg, MISCCR);
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writel(reg, S3C_MISCCR);
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/* ----------- the devices the boot loader should work with -------- */
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add_generic_device("s3c24x0_nand", -1, NULL, S3C24X0_NAND_BASE, 0,
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@ -30,6 +30,7 @@
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#include <io.h>
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#include <mach/s3c-iomap.h>
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#include <mach/s3c-busctl.h>
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#include <mach/s3c24xx-gpio.h>
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/**
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* Initialize the CPU to be able to work with the a9m2410dev evaluation board
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@ -39,38 +40,38 @@ int a9m2410dev_devices_init(void)
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unsigned int reg;
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/* ---------- configure the GPIOs ------------- */
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writel(0x007FFFFF, GPACON);
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writel(0x00000000, GPCCON);
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writel(0x00000000, GPCUP);
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writel(0x00000000, GPDCON);
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writel(0x00000000, GPDUP);
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writel(0xAAAAAAAA, GPECON);
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writel(0x0000E03F, GPEUP);
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writel(0x00000000, GPBCON); /* all inputs */
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writel(0x00000007, GPBUP); /* pullup disabled for GPB0..3 */
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writel(0x00009000, GPFCON); /* GPF7 CLK_INT#, GPF6 Debug-LED */
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writel(0x000000FF, GPFUP);
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writel(readl(GPGDAT) | 0x1010, GPGDAT); /* switch off IDLE_SW#, switch off LCD backlight */
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writel(0x0100A93A, GPGCON); /* switch on USB device */
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writel(0x0000F000, GPGUP);
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writel(0x0029FAAA, GPHCON);
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writel(0x007FFFFF, S3C_GPACON);
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writel(0x00000000, S3C_GPCCON);
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writel(0x00000000, S3C_GPCUP);
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writel(0x00000000, S3C_GPDCON);
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writel(0x00000000, S3C_GPDUP);
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writel(0xAAAAAAAA, S3C_GPECON);
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writel(0x0000E03F, S3C_GPEUP);
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writel(0x00000000, S3C_GPBCON); /* all inputs */
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writel(0x00000007, S3C_GPBUP); /* pullup disabled for GPB0..3 */
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writel(0x00009000, S3C_GPFCON); /* GPF7 CLK_INT#, GPF6 Debug-LED */
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writel(0x000000FF, S3C_GPFUP);
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writel(readl(S3C_GPGDAT) | 0x1010, S3C_GPGDAT); /* switch off IDLE_SW#, switch off LCD backlight */
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writel(0x0100A93A, S3C_GPGCON); /* switch on USB device */
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writel(0x0000F000, S3C_GPGUP);
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writel(0x0029FAAA, S3C_GPHCON);
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writel((1 << 12) | (0 << 11), GPJDAT);
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writel(0x0016aaaa, GPJCON);
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writel(~((0<<12)| (1<<11)), GPJUP);
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writel((1 << 12) | (0 << 11), S3C_GPJDAT);
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writel(0x0016aaaa, S3C_GPJCON);
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writel(~((0<<12)| (1<<11)), S3C_GPJUP);
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writel((0 << 12) | (0 << 11), GPJDAT);
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writel(0x0016aaaa, GPJCON);
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writel(0x00001fff, GPJUP);
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writel((0 << 12) | (0 << 11), S3C_GPJDAT);
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writel(0x0016aaaa, S3C_GPJCON);
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writel(0x00001fff, S3C_GPJUP);
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writel(0x00000000, DSC0);
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writel(0x00000000, DSC1);
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writel(0x00000000, S3C_DSC0);
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writel(0x00000000, S3C_DSC1);
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/*
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* USB port1 normal, USB port0 normal, USB1 pads for device
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* PCLK output on CLKOUT0, UPLL CLK output on CLKOUT1,
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*/
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writel((readl(MISCCR) & ~0xFFFF) | 0x0140, MISCCR);
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writel((readl(S3C_MISCCR) & ~0xFFFF) | 0x0140, S3C_MISCCR);
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/* ----------- configure the access to the outer space ---------- */
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reg = readl(S3C_BWSCON);
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@ -88,9 +89,9 @@ int a9m2410dev_devices_init(void)
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writel(reg, S3C_BWSCON);
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/* release the reset signal to the network and UART device */
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reg = readl(MISCCR);
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reg = readl(S3C_MISCCR);
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reg |= 0x10000;
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writel(reg, MISCCR);
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writel(reg, S3C_MISCCR);
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return 0;
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}
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@ -36,6 +36,7 @@
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#include <mach/s3c24xx-nand.h>
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#include <mach/s3c-generic.h>
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#include <mach/s3c-busctl.h>
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#include <mach/s3c24xx-gpio.h>
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#include "baseboards.h"
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@ -123,9 +124,9 @@ static int a9m2440_devices_init(void)
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#endif
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/* release the reset signal to external devices */
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reg = readl(MISCCR);
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reg = readl(S3C_MISCCR);
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reg |= 0x10000;
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writel(reg, MISCCR);
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writel(reg, S3C_MISCCR);
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/* ----------- the devices the boot loader should work with -------- */
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add_generic_device("s3c24x0_nand", -1, NULL, S3C24X0_NAND_BASE, 0,
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@ -4,6 +4,7 @@
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#include <config.h>
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#include <mach/s3c-iomap.h>
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#include <mach/s3c24xx-gpio.h>
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.section ".text_bare_init.board_init_lowlevel","ax"
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@ -33,7 +34,7 @@ sdram_init:
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* configured yet, these pins show external settings, to detect
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* the SDRAM size.
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*/
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ldr r1, =GPBDAT
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ldr r1, =S3C_GPBDAT
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ldr r4, [r1]
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and r4, r4, #0x3
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@ -44,6 +44,7 @@
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#include <mach/s3c-mci.h>
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#include <mach/s3c24xx-fb.h>
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#include <mach/s3c-busctl.h>
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#include <mach/s3c24xx-gpio.h>
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static struct s3c24x0_nand_platform_data nand_info = {
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.nand_timing = CALC_NFCONF_TIMING(MINI2440_TACLS, MINI2440_TWRPH0,
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@ -292,9 +293,9 @@ static int mini2440_devices_init(void)
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writel(reg, S3C_BWSCON);
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/* release the reset signal to external devices */
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reg = readl(MISCCR);
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reg = readl(S3C_MISCCR);
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reg |= 0x10000;
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writel(reg, MISCCR);
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writel(reg, S3C_MISCCR);
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add_generic_device("s3c24x0_nand", -1, NULL, S3C24X0_NAND_BASE, 0,
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IORESOURCE_MEM, &nand_info);
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@ -31,6 +31,7 @@
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#include <mach/s3c-iomap.h>
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#include <mach/s3c-generic.h>
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#include <mach/s3c-busctl.h>
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#include <mach/s3c24xx-gpio.h>
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/**
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* Calculate the amount of connected and available memory
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@ -81,7 +82,7 @@ uint32_t s3c24xx_get_memory_size(void)
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void s3c24xx_disable_second_sdram_bank(void)
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{
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writel(readl(S3C_BANKCON7) & ~(0x3 << 15), S3C_BANKCON7);
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writel(readl(MISCCR) | (1 << 18), MISCCR); /* disable its clock */
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writel(readl(S3C_MISCCR) | (1 << 18), S3C_MISCCR); /* disable its clock */
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}
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#define S3C_WTCON (S3C_WATCHDOG_BASE)
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@ -20,6 +20,7 @@
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#include <io.h>
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#include <mach/s3c-iomap.h>
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#include <mach/gpio.h>
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#include <mach/s3c24xx-gpio.h>
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static const unsigned char group_offset[] =
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{
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@ -45,10 +46,10 @@ void gpio_set_value(unsigned gpio, int value)
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offset = group_offset[group];
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reg = readl(GPADAT + offset);
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reg = readl(S3C_GPADAT + offset);
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reg &= ~(1 << bit);
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reg |= (!!value) << bit;
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writel(reg, GPADAT + offset);
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writel(reg, S3C_GPADAT + offset);
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}
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int gpio_direction_input(unsigned gpio)
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@ -60,9 +61,9 @@ int gpio_direction_input(unsigned gpio)
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offset = group_offset[group];
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reg = readl(GPACON + offset);
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reg = readl(S3C_GPACON + offset);
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reg &= ~(0x3 << (bit << 1));
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writel(reg, GPACON + offset);
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writel(reg, S3C_GPACON + offset);
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return 0;
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}
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@ -81,14 +82,14 @@ int gpio_direction_output(unsigned gpio, int value)
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gpio_set_value(gpio,value);
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/* direction */
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if (group == 0) { /* GPA is special */
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reg = readl(GPACON);
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reg = readl(S3C_GPACON);
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reg &= ~(1 << bit);
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writel(reg, GPACON);
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writel(reg, S3C_GPACON);
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} else {
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reg = readl(GPACON + offset);
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reg = readl(S3C_GPACON + offset);
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reg &= ~(0x3 << (bit << 1));
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reg |= 0x1 << (bit << 1);
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writel(reg, GPACON + offset);
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writel(reg, S3C_GPACON + offset);
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}
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return 0;
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@ -107,7 +108,7 @@ int gpio_get_value(unsigned gpio)
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offset = group_offset[group];
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/* value */
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reg = readl(GPADAT + offset);
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reg = readl(S3C_GPADAT + offset);
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return !!(reg & (1 << bit));
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}
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@ -132,9 +133,9 @@ void s3c_gpio_mode(unsigned gpio_mode)
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gpio_direction_output(bit, GET_GPIOVAL(gpio_mode));
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break;
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default:
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reg = readl(GPACON);
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reg = readl(S3C_GPACON);
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reg |= 1 << bit;
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writel(reg, GPACON);
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writel(reg, S3C_GPACON);
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break;
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}
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return;
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@ -143,12 +144,12 @@ void s3c_gpio_mode(unsigned gpio_mode)
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offset = group_offset[group];
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if (PU_PRESENT(gpio_mode)) {
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reg = readl(GPACON + offset + 8);
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reg = readl(S3C_GPACON + offset + 8);
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if (GET_PU(gpio_mode))
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reg |= (1 << bit); /* set means _disabled_ */
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else
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reg &= ~(1 << bit);
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writel(reg, GPACON + offset + 8);
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writel(reg, S3C_GPACON + offset + 8);
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}
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switch (func) {
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@ -160,10 +161,10 @@ void s3c_gpio_mode(unsigned gpio_mode)
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break;
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case 2: /* function one */
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case 3: /* function two */
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reg = readl(GPACON + offset);
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reg = readl(S3C_GPACON + offset);
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reg &= ~(0x3 << (bit << 1));
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reg |= func << (bit << 1);
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writel(reg, GPACON + offset);
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writel(reg, S3C_GPACON + offset);
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break;
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}
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}
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@ -32,7 +32,7 @@
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#define S3C_WATCHDOG_BASE 0x53000000
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#define S3C2410_I2C_BASE 0x54000000
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#define S3C2410_I2S_BASE 0x55000000
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#define S3C24X0_GPIO_BASE 0x56000000
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#define S3C_GPIO_BASE 0x56000000
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#define S3C2410_RTC_BASE 0x57000000
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#define S3C2410_ADC_BASE 0x58000000
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#define S3C2410_SPI_BASE 0x59000000
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@ -67,63 +67,3 @@
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#define S3C_UART2_SIZE 0x4000
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#define S3C_UART3_BASE (S3C_UART_BASE + 0x8000)
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#define S3C_UART3_SIZE 0x4000
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/* GPIO registers (direct access) */
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#define GPACON (S3C24X0_GPIO_BASE)
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#define GPADAT (S3C24X0_GPIO_BASE + 0x04)
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#define GPBCON (S3C24X0_GPIO_BASE + 0x10)
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#define GPBDAT (S3C24X0_GPIO_BASE + 0x14)
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#define GPBUP (S3C24X0_GPIO_BASE + 0x18)
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#define GPCCON (S3C24X0_GPIO_BASE + 0x20)
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#define GPCDAT (S3C24X0_GPIO_BASE + 0x24)
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#define GPCUP (S3C24X0_GPIO_BASE + 0x28)
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#define GPDCON (S3C24X0_GPIO_BASE + 0x30)
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#define GPDDAT (S3C24X0_GPIO_BASE + 0x34)
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#define GPDUP (S3C24X0_GPIO_BASE + 0x38)
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#define GPECON (S3C24X0_GPIO_BASE + 0x40)
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#define GPEDAT (S3C24X0_GPIO_BASE + 0x44)
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#define GPEUP (S3C24X0_GPIO_BASE + 0x48)
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#define GPFCON (S3C24X0_GPIO_BASE + 0x50)
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#define GPFDAT (S3C24X0_GPIO_BASE + 0x54)
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#define GPFUP (S3C24X0_GPIO_BASE + 0x58)
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#define GPGCON (S3C24X0_GPIO_BASE + 0x60)
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#define GPGDAT (S3C24X0_GPIO_BASE + 0x64)
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#define GPGUP (S3C24X0_GPIO_BASE + 0x68)
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#define GPHCON (S3C24X0_GPIO_BASE + 0x70)
|
||||
#define GPHDAT (S3C24X0_GPIO_BASE + 0x74)
|
||||
#define GPHUP (S3C24X0_GPIO_BASE + 0x78)
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2440
|
||||
# define GPJCON (S3C24X0_GPIO_BASE + 0xd0)
|
||||
# define GPJDAT (S3C24X0_GPIO_BASE + 0xd4)
|
||||
# define GPJUP (S3C24X0_GPIO_BASE + 0xd8)
|
||||
#endif
|
||||
|
||||
#define MISCCR (S3C24X0_GPIO_BASE + 0x80)
|
||||
#define DCLKCON (S3C24X0_GPIO_BASE + 0x84)
|
||||
#define EXTINT0 (S3C24X0_GPIO_BASE + 0x88)
|
||||
#define EXTINT1 (S3C24X0_GPIO_BASE + 0x8c)
|
||||
#define EXTINT2 (S3C24X0_GPIO_BASE + 0x90)
|
||||
#define EINTFLT0 (S3C24X0_GPIO_BASE + 0x94)
|
||||
#define EINTFLT1 (S3C24X0_GPIO_BASE + 0x98)
|
||||
#define EINTFLT2 (S3C24X0_GPIO_BASE + 0x9c)
|
||||
#define EINTFLT3 (S3C24X0_GPIO_BASE + 0xa0)
|
||||
#define EINTMASK (S3C24X0_GPIO_BASE + 0xa4)
|
||||
#define EINTPEND (S3C24X0_GPIO_BASE + 0xa8)
|
||||
#define GSTATUS0 (S3C24X0_GPIO_BASE + 0xac)
|
||||
#define GSTATUS1 (S3C24X0_GPIO_BASE + 0xb0)
|
||||
#define GSTATUS2 (S3C24X0_GPIO_BASE + 0xb4)
|
||||
#define GSTATUS3 (S3C24X0_GPIO_BASE + 0xb8)
|
||||
#define GSTATUS4 (S3C24X0_GPIO_BASE + 0xbc)
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2440
|
||||
# define DSC0 (S3C24X0_GPIO_BASE + 0xc4)
|
||||
# define DSC1 (S3C24X0_GPIO_BASE + 0xc8)
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Juergen Beisert, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_S3C24XX_GPIO_H
|
||||
# define __MACH_S3C24XX_GPIO_H
|
||||
|
||||
#define S3C_GPACON (S3C_GPIO_BASE)
|
||||
#define S3C_GPADAT (S3C_GPIO_BASE + 0x04)
|
||||
|
||||
#define S3C_GPBCON (S3C_GPIO_BASE + 0x10)
|
||||
#define S3C_GPBDAT (S3C_GPIO_BASE + 0x14)
|
||||
#define S3C_GPBUP (S3C_GPIO_BASE + 0x18)
|
||||
|
||||
#define S3C_GPCCON (S3C_GPIO_BASE + 0x20)
|
||||
#define S3C_GPCDAT (S3C_GPIO_BASE + 0x24)
|
||||
#define S3C_GPCUP (S3C_GPIO_BASE + 0x28)
|
||||
|
||||
#define S3C_GPDCON (S3C_GPIO_BASE + 0x30)
|
||||
#define S3C_GPDDAT (S3C_GPIO_BASE + 0x34)
|
||||
#define S3C_GPDUP (S3C_GPIO_BASE + 0x38)
|
||||
|
||||
#define S3C_GPECON (S3C_GPIO_BASE + 0x40)
|
||||
#define S3C_GPEDAT (S3C_GPIO_BASE + 0x44)
|
||||
#define S3C_GPEUP (S3C_GPIO_BASE + 0x48)
|
||||
|
||||
#define S3C_GPFCON (S3C_GPIO_BASE + 0x50)
|
||||
#define S3C_GPFDAT (S3C_GPIO_BASE + 0x54)
|
||||
#define S3C_GPFUP (S3C_GPIO_BASE + 0x58)
|
||||
|
||||
#define S3C_GPGCON (S3C_GPIO_BASE + 0x60)
|
||||
#define S3C_GPGDAT (S3C_GPIO_BASE + 0x64)
|
||||
#define S3C_GPGUP (S3C_GPIO_BASE + 0x68)
|
||||
|
||||
#define S3C_GPHCON (S3C_GPIO_BASE + 0x70)
|
||||
#define S3C_GPHDAT (S3C_GPIO_BASE + 0x74)
|
||||
#define S3C_GPHUP (S3C_GPIO_BASE + 0x78)
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2440
|
||||
# define S3C_GPJCON (S3C_GPIO_BASE + 0xd0)
|
||||
# define S3C_GPJDAT (S3C_GPIO_BASE + 0xd4)
|
||||
# define S3C_GPJUP (S3C_GPIO_BASE + 0xd8)
|
||||
#endif
|
||||
|
||||
#define S3C_MISCCR (S3C_GPIO_BASE + 0x80)
|
||||
#define S3C_DCLKCON (S3C_GPIO_BASE + 0x84)
|
||||
#define S3C_EXTINT0 (S3C_GPIO_BASE + 0x88)
|
||||
#define S3C_EXTINT1 (S3C_GPIO_BASE + 0x8c)
|
||||
#define S3C_EXTINT2 (S3C_GPIO_BASE + 0x90)
|
||||
#define S3C_EINTFLT0 (S3C_GPIO_BASE + 0x94)
|
||||
#define S3C_EINTFLT1 (S3C_GPIO_BASE + 0x98)
|
||||
#define S3C_EINTFLT2 (S3C_GPIO_BASE + 0x9c)
|
||||
#define S3C_EINTFLT3 (S3C_GPIO_BASE + 0xa0)
|
||||
#define S3C_EINTMASK (S3C_GPIO_BASE + 0xa4)
|
||||
#define S3C_EINTPEND (S3C_GPIO_BASE + 0xa8)
|
||||
#define S3C_GSTATUS0 (S3C_GPIO_BASE + 0xac)
|
||||
#define S3C_GSTATUS1 (S3C_GPIO_BASE + 0xb0)
|
||||
#define S3C_GSTATUS2 (S3C_GPIO_BASE + 0xb4)
|
||||
#define S3C_GSTATUS3 (S3C_GPIO_BASE + 0xb8)
|
||||
#define S3C_GSTATUS4 (S3C_GPIO_BASE + 0xbc)
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2440
|
||||
# define S3C_DSC0 (S3C_GPIO_BASE + 0xc4)
|
||||
# define S3C_DSC1 (S3C_GPIO_BASE + 0xc8)
|
||||
#endif
|
||||
|
||||
#endif /* __MACH_S3C24XX_GPIO_H */
|
||||
Loading…
Reference in New Issue