Merge branch 'for-next/smc911x'
This commit is contained in:
Sascha Hauer
commit
40830caf4e
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@ -4,6 +4,11 @@
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#include <asm/cpu/cdefBF561.h>
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#include <partition.h>
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#include <fs.h>
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#include <smc911x.h>
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struct smc911x_plat smcplat = {
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.shift = 1,
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};
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static int ipe337_devices_init(void) {
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add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0x20000000, 32 * 1024 * 1024, 0);
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@ -17,7 +22,7 @@ static int ipe337_devices_init(void) {
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*pFIO0_FLAG_S = (1<<12);
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add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, 0x24000000, 4096,
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IORESOURCE_MEM, NULL);
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IORESOURCE_MEM, &smcplat);
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devfs_add_partition("nor0", 0x00000, 0x20000, DEVFS_PARTITION_FIXED, "self0");
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devfs_add_partition("nor0", 0x20000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
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@ -36,12 +36,6 @@ config DRIVER_NET_SMC911X
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This option enables support for the SMSC LAN9[12]1[567]
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ethernet chip.
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config DRIVER_NET_SMC911X_ADDRESS_SHIFT
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int
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depends on DRIVER_NET_SMC911X
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default 1 if MACH_IPE337
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default 0
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config DRIVER_NET_SMC91111
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bool "smc91111 ethernet driver"
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select MIIDEV
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@ -37,368 +37,98 @@
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#include <errno.h>
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#include <clock.h>
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#include <io.h>
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#include <smc911x.h>
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#define AS CONFIG_DRIVER_NET_SMC911X_ADDRESS_SHIFT
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/* Below are the register offsets and bit definitions
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* of the Lan911x memory space
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*/
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#define RX_DATA_FIFO (0x00 << AS)
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#define TX_DATA_FIFO (0x20 << AS)
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#define TX_CMD_A_INT_ON_COMP 0x80000000
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#define TX_CMD_A_INT_BUF_END_ALGN 0x03000000
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#define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000
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#define TX_CMD_A_INT_16_BYTE_ALGN 0x01000000
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#define TX_CMD_A_INT_32_BYTE_ALGN 0x02000000
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#define TX_CMD_A_INT_DATA_OFFSET 0x001F0000
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#define TX_CMD_A_INT_FIRST_SEG 0x00002000
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#define TX_CMD_A_INT_LAST_SEG 0x00001000
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#define TX_CMD_A_BUF_SIZE 0x000007FF
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#define TX_CMD_B_PKT_TAG 0xFFFF0000
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#define TX_CMD_B_ADD_CRC_DISABLE 0x00002000
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#define TX_CMD_B_DISABLE_PADDING 0x00001000
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#define TX_CMD_B_PKT_BYTE_LENGTH 0x000007FF
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#define RX_STATUS_FIFO (0x40 << AS)
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#define RX_STS_PKT_LEN 0x3FFF0000
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#define RX_STS_ES 0x00008000
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#define RX_STS_BCST 0x00002000
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#define RX_STS_LEN_ERR 0x00001000
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#define RX_STS_RUNT_ERR 0x00000800
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#define RX_STS_MCAST 0x00000400
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#define RX_STS_TOO_LONG 0x00000080
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#define RX_STS_COLL 0x00000040
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#define RX_STS_ETH_TYPE 0x00000020
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#define RX_STS_WDOG_TMT 0x00000010
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#define RX_STS_MII_ERR 0x00000008
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#define RX_STS_DRIBBLING 0x00000004
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#define RX_STS_CRC_ERR 0x00000002
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#define RX_STATUS_FIFO_PEEK (0x44 << AS)
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#define TX_STATUS_FIFO (0x48 << AS)
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#define TX_STS_TAG 0xFFFF0000
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#define TX_STS_ES 0x00008000
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#define TX_STS_LOC 0x00000800
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#define TX_STS_NO_CARR 0x00000400
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#define TX_STS_LATE_COLL 0x00000200
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#define TX_STS_MANY_COLL 0x00000100
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#define TX_STS_COLL_CNT 0x00000078
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#define TX_STS_MANY_DEFER 0x00000004
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#define TX_STS_UNDERRUN 0x00000002
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#define TX_STS_DEFERRED 0x00000001
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#define TX_STATUS_FIFO_PEEK (0x4C << AS)
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#define ID_REV (0x50 << AS)
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#define ID_REV_CHIP_ID 0xFFFF0000 /* RO */
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#define ID_REV_REV_ID 0x0000FFFF /* RO */
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#define INT_CFG (0x54 << AS)
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#define INT_CFG_INT_DEAS 0xFF000000 /* R/W */
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#define INT_CFG_INT_DEAS_CLR 0x00004000
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#define INT_CFG_INT_DEAS_STS 0x00002000
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#define INT_CFG_IRQ_INT 0x00001000 /* RO */
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#define INT_CFG_IRQ_EN 0x00000100 /* R/W */
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#define INT_CFG_IRQ_POL 0x00000010 /* R/W Not Affected by SW Reset */
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#define INT_CFG_IRQ_TYPE 0x00000001 /* R/W Not Affected by SW Reset */
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#define INT_STS (0x58 << AS)
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#define INT_STS_SW_INT 0x80000000 /* R/WC */
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#define INT_STS_TXSTOP_INT 0x02000000 /* R/WC */
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#define INT_STS_RXSTOP_INT 0x01000000 /* R/WC */
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#define INT_STS_RXDFH_INT 0x00800000 /* R/WC */
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#define INT_STS_RXDF_INT 0x00400000 /* R/WC */
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#define INT_STS_TX_IOC 0x00200000 /* R/WC */
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#define INT_STS_RXD_INT 0x00100000 /* R/WC */
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#define INT_STS_GPT_INT 0x00080000 /* R/WC */
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#define INT_STS_PHY_INT 0x00040000 /* RO */
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#define INT_STS_PME_INT 0x00020000 /* R/WC */
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#define INT_STS_TXSO 0x00010000 /* R/WC */
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#define INT_STS_RWT 0x00008000 /* R/WC */
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#define INT_STS_RXE 0x00004000 /* R/WC */
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#define INT_STS_TXE 0x00002000 /* R/WC */
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//#define INT_STS_ERX 0x00001000 /* R/WC */
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#define INT_STS_TDFU 0x00000800 /* R/WC */
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#define INT_STS_TDFO 0x00000400 /* R/WC */
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#define INT_STS_TDFA 0x00000200 /* R/WC */
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#define INT_STS_TSFF 0x00000100 /* R/WC */
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#define INT_STS_TSFL 0x00000080 /* R/WC */
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//#define INT_STS_RXDF 0x00000040 /* R/WC */
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#define INT_STS_RDFO 0x00000040 /* R/WC */
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#define INT_STS_RDFL 0x00000020 /* R/WC */
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#define INT_STS_RSFF 0x00000010 /* R/WC */
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#define INT_STS_RSFL 0x00000008 /* R/WC */
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#define INT_STS_GPIO2_INT 0x00000004 /* R/WC */
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#define INT_STS_GPIO1_INT 0x00000002 /* R/WC */
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#define INT_STS_GPIO0_INT 0x00000001 /* R/WC */
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#define INT_EN (0x5C << AS)
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#define INT_EN_SW_INT_EN 0x80000000 /* R/W */
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#define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */
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#define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */
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#define INT_EN_RXDFH_INT_EN 0x00800000 /* R/W */
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//#define INT_EN_RXDF_INT_EN 0x00400000 /* R/W */
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#define INT_EN_TIOC_INT_EN 0x00200000 /* R/W */
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#define INT_EN_RXD_INT_EN 0x00100000 /* R/W */
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#define INT_EN_GPT_INT_EN 0x00080000 /* R/W */
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#define INT_EN_PHY_INT_EN 0x00040000 /* R/W */
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#define INT_EN_PME_INT_EN 0x00020000 /* R/W */
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#define INT_EN_TXSO_EN 0x00010000 /* R/W */
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#define INT_EN_RWT_EN 0x00008000 /* R/W */
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#define INT_EN_RXE_EN 0x00004000 /* R/W */
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#define INT_EN_TXE_EN 0x00002000 /* R/W */
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//#define INT_EN_ERX_EN 0x00001000 /* R/W */
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#define INT_EN_TDFU_EN 0x00000800 /* R/W */
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#define INT_EN_TDFO_EN 0x00000400 /* R/W */
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#define INT_EN_TDFA_EN 0x00000200 /* R/W */
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#define INT_EN_TSFF_EN 0x00000100 /* R/W */
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#define INT_EN_TSFL_EN 0x00000080 /* R/W */
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//#define INT_EN_RXDF_EN 0x00000040 /* R/W */
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#define INT_EN_RDFO_EN 0x00000040 /* R/W */
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#define INT_EN_RDFL_EN 0x00000020 /* R/W */
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#define INT_EN_RSFF_EN 0x00000010 /* R/W */
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#define INT_EN_RSFL_EN 0x00000008 /* R/W */
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#define INT_EN_GPIO2_INT 0x00000004 /* R/W */
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#define INT_EN_GPIO1_INT 0x00000002 /* R/W */
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#define INT_EN_GPIO0_INT 0x00000001 /* R/W */
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#define BYTE_TEST (0x64 << AS)
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#define FIFO_INT (0x68 << AS)
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#define FIFO_INT_TX_AVAIL_LEVEL 0xFF000000 /* R/W */
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#define FIFO_INT_TX_STS_LEVEL 0x00FF0000 /* R/W */
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#define FIFO_INT_RX_AVAIL_LEVEL 0x0000FF00 /* R/W */
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#define FIFO_INT_RX_STS_LEVEL 0x000000FF /* R/W */
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#define RX_CFG (0x6C << AS)
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#define RX_CFG_RX_END_ALGN 0xC0000000 /* R/W */
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#define RX_CFG_RX_END_ALGN4 0x00000000 /* R/W */
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#define RX_CFG_RX_END_ALGN16 0x40000000 /* R/W */
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#define RX_CFG_RX_END_ALGN32 0x80000000 /* R/W */
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#define RX_CFG_RX_DMA_CNT 0x0FFF0000 /* R/W */
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#define RX_CFG_RX_DUMP 0x00008000 /* R/W */
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#define RX_CFG_RXDOFF 0x00001F00 /* R/W */
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//#define RX_CFG_RXBAD 0x00000001 /* R/W */
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#define TX_CFG (0x70 << AS)
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//#define TX_CFG_TX_DMA_LVL 0xE0000000 /* R/W */
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//#define TX_CFG_TX_DMA_CNT 0x0FFF0000 /* R/W Self Clearing */
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#define TX_CFG_TXS_DUMP 0x00008000 /* Self Clearing */
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#define TX_CFG_TXD_DUMP 0x00004000 /* Self Clearing */
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#define TX_CFG_TXSAO 0x00000004 /* R/W */
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#define TX_CFG_TX_ON 0x00000002 /* R/W */
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#define TX_CFG_STOP_TX 0x00000001 /* Self Clearing */
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#define HW_CFG (0x74 << AS)
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#define HW_CFG_TTM 0x00200000 /* R/W */
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#define HW_CFG_SF 0x00100000 /* R/W */
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#define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */
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#define HW_CFG_TR 0x00003000 /* R/W */
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#define HW_CFG_PHY_CLK_SEL 0x00000060 /* R/W */
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#define HW_CFG_PHY_CLK_SEL_INT_PHY 0x00000000 /* R/W */
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#define HW_CFG_PHY_CLK_SEL_EXT_PHY 0x00000020 /* R/W */
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#define HW_CFG_PHY_CLK_SEL_CLK_DIS 0x00000040 /* R/W */
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#define HW_CFG_SMI_SEL 0x00000010 /* R/W */
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#define HW_CFG_EXT_PHY_DET 0x00000008 /* RO */
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#define HW_CFG_EXT_PHY_EN 0x00000004 /* R/W */
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#define HW_CFG_32_16_BIT_MODE 0x00000004 /* RO */
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#define HW_CFG_SRST_TO 0x00000002 /* RO */
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#define HW_CFG_SRST 0x00000001 /* Self Clearing */
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#define RX_DP_CTRL (0x78 << AS)
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#define RX_DP_CTRL_RX_FFWD 0x80000000 /* R/W */
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#define RX_DP_CTRL_FFWD_BUSY 0x80000000 /* RO */
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#define RX_FIFO_INF (0x7C << AS)
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#define RX_FIFO_INF_RXSUSED 0x00FF0000 /* RO */
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#define RX_FIFO_INF_RXDUSED 0x0000FFFF /* RO */
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#define TX_FIFO_INF (0x80 << AS)
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#define TX_FIFO_INF_TSUSED 0x00FF0000 /* RO */
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#define TX_FIFO_INF_TDFREE 0x0000FFFF /* RO */
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#define PMT_CTRL (0x84 << AS)
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#define PMT_CTRL_PM_MODE 0x00003000 /* Self Clearing */
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#define PMT_CTRL_PHY_RST 0x00000400 /* Self Clearing */
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#define PMT_CTRL_WOL_EN 0x00000200 /* R/W */
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#define PMT_CTRL_ED_EN 0x00000100 /* R/W */
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#define PMT_CTRL_PME_TYPE 0x00000040 /* R/W Not Affected by SW Reset */
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#define PMT_CTRL_WUPS 0x00000030 /* R/WC */
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#define PMT_CTRL_WUPS_NOWAKE 0x00000000 /* R/WC */
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#define PMT_CTRL_WUPS_ED 0x00000010 /* R/WC */
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#define PMT_CTRL_WUPS_WOL 0x00000020 /* R/WC */
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#define PMT_CTRL_WUPS_MULTI 0x00000030 /* R/WC */
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#define PMT_CTRL_PME_IND 0x00000008 /* R/W */
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#define PMT_CTRL_PME_POL 0x00000004 /* R/W */
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#define PMT_CTRL_PME_EN 0x00000002 /* R/W Not Affected by SW Reset */
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#define PMT_CTRL_READY 0x00000001 /* RO */
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#define GPIO_CFG (0x88 << AS)
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#define GPIO_CFG_LED3_EN 0x40000000 /* R/W */
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#define GPIO_CFG_LED2_EN 0x20000000 /* R/W */
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#define GPIO_CFG_LED1_EN 0x10000000 /* R/W */
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#define GPIO_CFG_GPIO2_INT_POL 0x04000000 /* R/W */
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#define GPIO_CFG_GPIO1_INT_POL 0x02000000 /* R/W */
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#define GPIO_CFG_GPIO0_INT_POL 0x01000000 /* R/W */
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#define GPIO_CFG_EEPR_EN 0x00700000 /* R/W */
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#define GPIO_CFG_GPIOBUF2 0x00040000 /* R/W */
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#define GPIO_CFG_GPIOBUF1 0x00020000 /* R/W */
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#define GPIO_CFG_GPIOBUF0 0x00010000 /* R/W */
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#define GPIO_CFG_GPIODIR2 0x00000400 /* R/W */
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#define GPIO_CFG_GPIODIR1 0x00000200 /* R/W */
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#define GPIO_CFG_GPIODIR0 0x00000100 /* R/W */
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#define GPIO_CFG_GPIOD4 0x00000010 /* R/W */
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#define GPIO_CFG_GPIOD3 0x00000008 /* R/W */
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#define GPIO_CFG_GPIOD2 0x00000004 /* R/W */
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#define GPIO_CFG_GPIOD1 0x00000002 /* R/W */
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#define GPIO_CFG_GPIOD0 0x00000001 /* R/W */
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#define GPT_CFG (0x8C << AS)
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#define GPT_CFG_TIMER_EN 0x20000000 /* R/W */
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#define GPT_CFG_GPT_LOAD 0x0000FFFF /* R/W */
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#define GPT_CNT (0x90 << AS)
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#define GPT_CNT_GPT_CNT 0x0000FFFF /* RO */
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#define ENDIAN (0x98 << AS)
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#define FREE_RUN (0x9C << AS)
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#define RX_DROP (0xA0 << AS)
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#define MAC_CSR_CMD (0xA4 << AS)
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#define MAC_CSR_CMD_CSR_BUSY 0x80000000 /* Self Clearing */
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#define MAC_CSR_CMD_R_NOT_W 0x40000000 /* R/W */
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#define MAC_CSR_CMD_CSR_ADDR 0x000000FF /* R/W */
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#define MAC_CSR_DATA (0xA8 << AS)
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#define AFC_CFG (0xAC << AS)
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#define AFC_CFG_AFC_HI 0x00FF0000 /* R/W */
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#define AFC_CFG_AFC_LO 0x0000FF00 /* R/W */
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#define AFC_CFG_BACK_DUR 0x000000F0 /* R/W */
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#define AFC_CFG_FCMULT 0x00000008 /* R/W */
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#define AFC_CFG_FCBRD 0x00000004 /* R/W */
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#define AFC_CFG_FCADD 0x00000002 /* R/W */
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#define AFC_CFG_FCANY 0x00000001 /* R/W */
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#define E2P_CMD (0xB0 << AS)
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#define E2P_CMD_EPC_BUSY 0x80000000 /* Self Clearing */
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#define E2P_CMD_EPC_CMD 0x70000000 /* R/W */
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#define E2P_CMD_EPC_CMD_READ 0x00000000 /* R/W */
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#define E2P_CMD_EPC_CMD_EWDS 0x10000000 /* R/W */
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#define E2P_CMD_EPC_CMD_EWEN 0x20000000 /* R/W */
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#define E2P_CMD_EPC_CMD_WRITE 0x30000000 /* R/W */
|
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#define E2P_CMD_EPC_CMD_WRAL 0x40000000 /* R/W */
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||||
#define E2P_CMD_EPC_CMD_ERASE 0x50000000 /* R/W */
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#define E2P_CMD_EPC_CMD_ERAL 0x60000000 /* R/W */
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#define E2P_CMD_EPC_CMD_RELOAD 0x70000000 /* R/W */
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#define E2P_CMD_EPC_TIMEOUT 0x00000200 /* RO */
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#define E2P_CMD_MAC_ADDR_LOADED 0x00000100 /* RO */
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#define E2P_CMD_EPC_ADDR 0x000000FF /* R/W */
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||||
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#define E2P_DATA (0xB4 << AS)
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#define E2P_DATA_EEPROM_DATA 0x000000FF /* R/W */
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/* end of LAN register offsets and bit definitions */
|
||||
|
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/* MAC Control and Status registers */
|
||||
#define MAC_CR 0x01 /* R/W */
|
||||
|
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/* MAC_CR - MAC Control Register */
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#define MAC_CR_RXALL 0x80000000
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// TODO: delete this bit? It is not described in the data sheet.
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#define MAC_CR_HBDIS 0x10000000
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||||
#define MAC_CR_RCVOWN 0x00800000
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||||
#define MAC_CR_LOOPBK 0x00200000
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||||
#define MAC_CR_FDPX 0x00100000
|
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#define MAC_CR_MCPAS 0x00080000
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||||
#define MAC_CR_PRMS 0x00040000
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||||
#define MAC_CR_INVFILT 0x00020000
|
||||
#define MAC_CR_PASSBAD 0x00010000
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#define MAC_CR_HFILT 0x00008000
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||||
#define MAC_CR_HPFILT 0x00002000
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#define MAC_CR_LCOLL 0x00001000
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||||
#define MAC_CR_BCAST 0x00000800
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||||
#define MAC_CR_DISRTY 0x00000400
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||||
#define MAC_CR_PADSTR 0x00000100
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||||
#define MAC_CR_BOLMT_MASK 0x000000C0
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||||
#define MAC_CR_DFCHK 0x00000020
|
||||
#define MAC_CR_TXEN 0x00000008
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||||
#define MAC_CR_RXEN 0x00000004
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||||
|
||||
#define ADDRH 0x02 /* R/W mask 0x0000FFFFUL */
|
||||
#define ADDRL 0x03 /* R/W mask 0xFFFFFFFFUL */
|
||||
#define HASHH 0x04 /* R/W */
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||||
#define HASHL 0x05 /* R/W */
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||||
|
||||
#define MII_ACC 0x06 /* R/W */
|
||||
#define MII_ACC_PHY_ADDR 0x0000F800
|
||||
#define MII_ACC_MIIRINDA 0x000007C0
|
||||
#define MII_ACC_MII_WRITE 0x00000002
|
||||
#define MII_ACC_MII_BUSY 0x00000001
|
||||
|
||||
#define MII_DATA 0x07 /* R/W mask 0x0000FFFFUL */
|
||||
|
||||
#ifdef FLOW
|
||||
#undef FLOW /* clashed with include/asm/cpu/defBF561.h:1654 */
|
||||
#endif
|
||||
|
||||
#define FLOW 0x08 /* R/W */
|
||||
#define FLOW_FCPT 0xFFFF0000
|
||||
#define FLOW_FCPASS 0x00000004
|
||||
#define FLOW_FCEN 0x00000002
|
||||
#define FLOW_FCBSY 0x00000001
|
||||
|
||||
#define VLAN1 0x09 /* R/W mask 0x0000FFFFUL */
|
||||
#define VLAN1_VTI1 0x0000ffff
|
||||
|
||||
#define VLAN2 0x0A /* R/W mask 0x0000FFFFUL */
|
||||
#define VLAN2_VTI2 0x0000ffff
|
||||
|
||||
#define WUFF 0x0B /* WO */
|
||||
|
||||
#define WUCSR 0x0C /* R/W */
|
||||
#define WUCSR_GUE 0x00000200
|
||||
#define WUCSR_WUFR 0x00000040
|
||||
#define WUCSR_MPR 0x00000020
|
||||
#define WUCSR_WAKE_EN 0x00000004
|
||||
#define WUCSR_MPEN 0x00000002
|
||||
|
||||
/* Chip ID values */
|
||||
#define CHIP_9115 0x115
|
||||
#define CHIP_9116 0x116
|
||||
#define CHIP_9117 0x117
|
||||
#define CHIP_9118 0x118
|
||||
#define CHIP_9215 0x115a
|
||||
#define CHIP_9216 0x116a
|
||||
#define CHIP_9217 0x117a
|
||||
#define CHIP_9218 0x118a
|
||||
#define CHIP_9221 0x9221
|
||||
#include "smc911x.h"
|
||||
|
||||
struct smc911x_priv {
|
||||
struct eth_device edev;
|
||||
struct mii_device miidev;
|
||||
void __iomem *base;
|
||||
};
|
||||
|
||||
struct chip_id {
|
||||
u16 id;
|
||||
char *name;
|
||||
};
|
||||
int shift;
|
||||
int generation;
|
||||
|
||||
static const struct chip_id chip_ids[] = {
|
||||
{ CHIP_9115, "LAN9115" },
|
||||
{ CHIP_9116, "LAN9116" },
|
||||
{ CHIP_9117, "LAN9117" },
|
||||
{ CHIP_9118, "LAN9118" },
|
||||
{ CHIP_9215, "LAN9215" },
|
||||
{ CHIP_9216, "LAN9216" },
|
||||
{ CHIP_9217, "LAN9217" },
|
||||
{ CHIP_9218, "LAN9218" },
|
||||
{ CHIP_9221, "LAN9221" },
|
||||
{ 0, NULL },
|
||||
u32 (*reg_read)(struct smc911x_priv *priv, u32 reg);
|
||||
void (*reg_write)(struct smc911x_priv *priv, u32 reg, u32 val);
|
||||
};
|
||||
|
||||
#define DRIVERNAME "smc911x"
|
||||
|
||||
#define __smc_shift(priv, reg) ((reg) << ((priv)->shift))
|
||||
|
||||
static inline u32 smc911x_reg_read(struct smc911x_priv *priv, u32 reg)
|
||||
{
|
||||
return priv->reg_read(priv, reg);
|
||||
}
|
||||
|
||||
static inline u32 __smc911x_reg_readw(struct smc911x_priv *priv, u32 reg)
|
||||
{
|
||||
return ((readw(priv->base + reg) & 0xFFFF) |
|
||||
((readw(priv->base + reg + 2) & 0xFFFF) << 16));
|
||||
}
|
||||
|
||||
static inline u32 __smc911x_reg_readl(struct smc911x_priv *priv, u32 reg)
|
||||
{
|
||||
return readl(priv->base + reg);
|
||||
}
|
||||
|
||||
static inline u32
|
||||
__smc911x_reg_readw_shift(struct smc911x_priv *priv, u32 reg)
|
||||
{
|
||||
return (readw(priv->base +
|
||||
__smc_shift(priv, reg)) & 0xFFFF) |
|
||||
((readw(priv->base +
|
||||
__smc_shift(priv, reg + 2)) & 0xFFFF) << 16);
|
||||
|
||||
}
|
||||
|
||||
static inline u32
|
||||
__smc911x_reg_readl_shift(struct smc911x_priv *priv, u32 reg)
|
||||
{
|
||||
return readl(priv->base + __smc_shift(priv, reg));
|
||||
}
|
||||
|
||||
static inline void smc911x_reg_write(struct smc911x_priv *priv, u32 reg,
|
||||
u32 val)
|
||||
{
|
||||
priv->reg_write(priv, reg, val);
|
||||
}
|
||||
|
||||
static inline void __smc911x_reg_writew(struct smc911x_priv *priv, u32 reg,
|
||||
u32 val)
|
||||
{
|
||||
writew(val & 0xFFFF, priv->base + reg);
|
||||
writew((val >> 16) & 0xFFFF, priv->base + reg + 2);
|
||||
}
|
||||
|
||||
static inline void __smc911x_reg_writel(struct smc911x_priv *priv, u32 reg,
|
||||
u32 val)
|
||||
{
|
||||
writel(val, priv->base + reg);
|
||||
}
|
||||
|
||||
static inline void
|
||||
__smc911x_reg_writew_shift(struct smc911x_priv *priv, u32 reg, u32 val)
|
||||
{
|
||||
writew(val & 0xFFFF,
|
||||
priv->base + __smc_shift(priv, reg));
|
||||
writew((val >> 16) & 0xFFFF,
|
||||
priv->base + __smc_shift(priv, reg + 2));
|
||||
}
|
||||
|
||||
static inline void
|
||||
__smc911x_reg_writel_shift(struct smc911x_priv *priv, u32 reg, u32 val)
|
||||
{
|
||||
writel(val, priv->base + __smc_shift(priv, reg));
|
||||
}
|
||||
|
||||
static int smc911x_mac_wait_busy(struct smc911x_priv *priv)
|
||||
{
|
||||
uint64_t start = get_time_ns();
|
||||
|
||||
while (!is_timeout(start, MSECOND)) {
|
||||
if (!(readl(priv->base + MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY))
|
||||
if (!(smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY))
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -413,12 +143,12 @@ static u32 smc911x_get_mac_csr(struct eth_device *edev, u8 reg)
|
|||
|
||||
smc911x_mac_wait_busy(priv);
|
||||
|
||||
writel(MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg,
|
||||
priv->base + MAC_CSR_CMD);
|
||||
smc911x_reg_write(priv, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY |
|
||||
MAC_CSR_CMD_R_NOT_W | reg);
|
||||
|
||||
smc911x_mac_wait_busy(priv);
|
||||
|
||||
val = readl(priv->base + MAC_CSR_DATA);
|
||||
val = smc911x_reg_read(priv, MAC_CSR_DATA);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
|
@ -429,8 +159,8 @@ static void smc911x_set_mac_csr(struct eth_device *edev, u8 reg, u32 data)
|
|||
|
||||
smc911x_mac_wait_busy(priv);
|
||||
|
||||
writel(data, priv->base + MAC_CSR_DATA);
|
||||
writel(MAC_CSR_CMD_CSR_BUSY | reg, priv->base + MAC_CSR_CMD);
|
||||
smc911x_reg_write(priv, MAC_CSR_DATA, data);
|
||||
smc911x_reg_write(priv, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
|
||||
|
||||
smc911x_mac_wait_busy(priv);
|
||||
}
|
||||
|
|
@ -504,10 +234,10 @@ static int smc911x_phy_reset(struct eth_device *edev)
|
|||
struct smc911x_priv *priv = edev->priv;
|
||||
u32 reg;
|
||||
|
||||
reg = readl(priv->base + PMT_CTRL);
|
||||
reg = smc911x_reg_read(priv, PMT_CTRL);
|
||||
reg &= 0xfcf;
|
||||
reg |= PMT_CTRL_PHY_RST;
|
||||
writel(reg, priv->base + PMT_CTRL);
|
||||
smc911x_reg_write(priv, PMT_CTRL, reg);
|
||||
|
||||
mdelay(100);
|
||||
|
||||
|
|
@ -520,13 +250,13 @@ static void smc911x_reset(struct eth_device *edev)
|
|||
uint64_t start;
|
||||
|
||||
/* Take out of PM setting first */
|
||||
if (readl(priv->base + PMT_CTRL) & PMT_CTRL_READY) {
|
||||
if (smc911x_reg_read(priv, PMT_CTRL) & PMT_CTRL_READY) {
|
||||
/* Write to the bytetest will take out of powerdown */
|
||||
writel(0, priv->base + BYTE_TEST);
|
||||
smc911x_reg_write(priv, BYTE_TEST, 0);
|
||||
|
||||
start = get_time_ns();
|
||||
while(1) {
|
||||
if ((readl(priv->base + PMT_CTRL) & PMT_CTRL_READY))
|
||||
if ((smc911x_reg_read(priv, PMT_CTRL) & PMT_CTRL_READY))
|
||||
break;
|
||||
if (is_timeout(start, 100 * USECOND)) {
|
||||
dev_err(&edev->dev,
|
||||
|
|
@ -537,13 +267,13 @@ static void smc911x_reset(struct eth_device *edev)
|
|||
}
|
||||
|
||||
/* Disable interrupts */
|
||||
writel(0, priv->base + INT_EN);
|
||||
smc911x_reg_write(priv, INT_EN, 0);
|
||||
|
||||
writel(HW_CFG_SRST, priv->base + HW_CFG);
|
||||
smc911x_reg_write(priv, HW_CFG, HW_CFG_SRST);
|
||||
|
||||
start = get_time_ns();
|
||||
while(1) {
|
||||
if (!(readl(priv->base + E2P_CMD) & E2P_CMD_EPC_BUSY))
|
||||
if (!(smc911x_reg_read(priv, E2P_CMD) & E2P_CMD_EPC_BUSY))
|
||||
break;
|
||||
if (is_timeout(start, 10 * MSECOND)) {
|
||||
dev_err(&edev->dev, "reset timeout\n");
|
||||
|
|
@ -554,10 +284,10 @@ static void smc911x_reset(struct eth_device *edev)
|
|||
/* Reset the FIFO level and flow control settings */
|
||||
smc911x_set_mac_csr(edev, FLOW, FLOW_FCPT | FLOW_FCEN);
|
||||
|
||||
writel(0x0050287F, priv->base + AFC_CFG);
|
||||
smc911x_reg_write(priv, AFC_CFG, 0x0050287F);
|
||||
|
||||
/* Set to LED outputs */
|
||||
writel(0x70070000, priv->base + GPIO_CFG);
|
||||
smc911x_reg_write(priv, GPIO_CFG, 0x70070000);
|
||||
}
|
||||
|
||||
static void smc911x_enable(struct eth_device *edev)
|
||||
|
|
@ -565,14 +295,14 @@ static void smc911x_enable(struct eth_device *edev)
|
|||
struct smc911x_priv *priv = edev->priv;
|
||||
|
||||
/* Enable TX */
|
||||
writel(8 << 16 | HW_CFG_SF, priv->base + HW_CFG);
|
||||
smc911x_reg_write(priv, HW_CFG, 8 << 16 | HW_CFG_SF);
|
||||
|
||||
writel(GPT_CFG_TIMER_EN | 10000, priv->base + GPT_CFG);
|
||||
smc911x_reg_write(priv, GPT_CFG, GPT_CFG_TIMER_EN | 10000);
|
||||
|
||||
writel(TX_CFG_TX_ON, priv->base + TX_CFG);
|
||||
smc911x_reg_write(priv, TX_CFG, TX_CFG_TX_ON);
|
||||
|
||||
/* no padding to start of packets */
|
||||
writel(RX_CFG_RX_DUMP, priv->base + RX_CFG);
|
||||
smc911x_reg_write(priv, RX_CFG, RX_CFG_RX_DUMP);
|
||||
}
|
||||
|
||||
static int smc911x_eth_open(struct eth_device *edev)
|
||||
|
|
@ -595,19 +325,19 @@ static int smc911x_eth_send(struct eth_device *edev, void *packet, int length)
|
|||
u32 status;
|
||||
uint64_t start;
|
||||
|
||||
writel(TX_CMD_A_INT_FIRST_SEG | TX_CMD_A_INT_LAST_SEG | length,
|
||||
priv->base + TX_DATA_FIFO);
|
||||
writel(length, priv->base + TX_DATA_FIFO);
|
||||
smc911x_reg_write(priv, TX_DATA_FIFO,
|
||||
TX_CMD_A_INT_FIRST_SEG | TX_CMD_A_INT_LAST_SEG | length);
|
||||
smc911x_reg_write(priv, TX_DATA_FIFO, length);
|
||||
|
||||
tmplen = (length + 3) / 4;
|
||||
|
||||
while(tmplen--)
|
||||
writel(*data++, priv->base + TX_DATA_FIFO);
|
||||
smc911x_reg_write(priv, TX_DATA_FIFO, *data++);
|
||||
|
||||
/* wait for transmission */
|
||||
start = get_time_ns();
|
||||
while (1) {
|
||||
if ((readl(priv->base + TX_FIFO_INF) &
|
||||
if ((smc911x_reg_read(priv, TX_FIFO_INF) &
|
||||
TX_FIFO_INF_TSUSED) >> 16)
|
||||
break;
|
||||
if (is_timeout(start, 100 * MSECOND)) {
|
||||
|
|
@ -619,7 +349,7 @@ static int smc911x_eth_send(struct eth_device *edev, void *packet, int length)
|
|||
/* get status. Ignore 'no carrier' error, it has no meaning for
|
||||
* full duplex operation
|
||||
*/
|
||||
status = readl(priv->base + TX_STATUS_FIFO) & (TX_STS_LOC |
|
||||
status = smc911x_reg_read(priv, TX_STATUS_FIFO) & (TX_STS_LOC |
|
||||
TX_STS_LATE_COLL | TX_STS_MANY_COLL | TX_STS_MANY_DEFER |
|
||||
TX_STS_UNDERRUN);
|
||||
|
||||
|
|
@ -641,7 +371,7 @@ static void smc911x_eth_halt(struct eth_device *edev)
|
|||
struct smc911x_priv *priv = (struct smc911x_priv *)edev->priv;
|
||||
|
||||
/* Disable TX */
|
||||
writel(TX_CFG_STOP_TX, priv->base + TX_CFG);
|
||||
smc911x_reg_write(priv, TX_CFG, TX_CFG_STOP_TX);
|
||||
|
||||
// smc911x_reset(edev);
|
||||
}
|
||||
|
|
@ -653,15 +383,15 @@ static int smc911x_eth_rx(struct eth_device *edev)
|
|||
u32 pktlen, tmplen;
|
||||
u32 status;
|
||||
|
||||
if((readl(priv->base + RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) {
|
||||
status = readl(priv->base + RX_STATUS_FIFO);
|
||||
if((smc911x_reg_read(priv, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) {
|
||||
status = smc911x_reg_read(priv, RX_STATUS_FIFO);
|
||||
pktlen = (status & RX_STS_PKT_LEN) >> 16;
|
||||
|
||||
writel(0, priv->base + RX_CFG);
|
||||
smc911x_reg_write(priv, RX_CFG, 0);
|
||||
|
||||
tmplen = (pktlen + 2 + 3) / 4;
|
||||
while(tmplen--)
|
||||
*data++ = readl(priv->base + RX_DATA_FIFO);
|
||||
*data++ = smc911x_reg_read(priv, RX_DATA_FIFO);
|
||||
|
||||
if(status & RX_STS_ES)
|
||||
dev_err(&edev->dev, "dropped bad packet. Status: 0x%08x\n",
|
||||
|
|
@ -690,30 +420,110 @@ static int smc911x_probe(struct device_d *dev)
|
|||
struct eth_device *edev;
|
||||
struct smc911x_priv *priv;
|
||||
uint32_t val;
|
||||
int i;
|
||||
void __iomem *base;
|
||||
|
||||
base = dev_request_mem_region(dev, 0);
|
||||
|
||||
val = readl(base + BYTE_TEST);
|
||||
if(val != 0x87654321) {
|
||||
dev_err(dev, "no smc911x found on 0x%p (byte_test=0x%08x)\n",
|
||||
base, val);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
val = readl(base + ID_REV) >> 16;
|
||||
for(i = 0; chip_ids[i].id != 0; i++) {
|
||||
if (chip_ids[i].id == val) break;
|
||||
}
|
||||
if (!chip_ids[i].id) {
|
||||
dev_err(dev, "Unknown chip ID %04x\n", val);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
dev_info(dev, "detected %s controller\n", chip_ids[i].name);
|
||||
int is_32bit, ret;
|
||||
struct smc911x_plat *pdata = dev->platform_data;
|
||||
|
||||
priv = xzalloc(sizeof(*priv));
|
||||
is_32bit = dev->resource[0].flags & IORESOURCE_MEM_TYPE_MASK;
|
||||
if (!is_32bit)
|
||||
is_32bit = 1;
|
||||
else
|
||||
is_32bit = is_32bit == IORESOURCE_MEM_32BIT;
|
||||
priv->base = dev_request_mem_region(dev, 0);
|
||||
|
||||
if (pdata && pdata->shift)
|
||||
priv->shift = pdata->shift;
|
||||
|
||||
if (is_32bit) {
|
||||
if (pdata->shift) {
|
||||
priv->reg_read = __smc911x_reg_readl_shift;
|
||||
priv->reg_write = __smc911x_reg_writel_shift;
|
||||
} else {
|
||||
priv->reg_read = __smc911x_reg_readl;
|
||||
priv->reg_write = __smc911x_reg_writel;
|
||||
}
|
||||
} else {
|
||||
if (pdata->shift) {
|
||||
priv->reg_read = __smc911x_reg_readw_shift;
|
||||
priv->reg_write = __smc911x_reg_writew_shift;
|
||||
} else {
|
||||
priv->reg_read = __smc911x_reg_readw;
|
||||
priv->reg_write = __smc911x_reg_writew;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* poll the READY bit in PMT_CTRL. Any other access to the device is
|
||||
* forbidden while this bit isn't set. Try for 100ms
|
||||
*/
|
||||
ret = wait_on_timeout(100 * MSECOND, smc911x_reg_read(priv, PMT_CTRL) & PMT_CTRL_READY);
|
||||
if (!ret) {
|
||||
dev_err(dev, "Device not READY in 100ms aborting\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
val = smc911x_reg_read(priv, BYTE_TEST);
|
||||
if (val == 0x43218765) {
|
||||
dev_dbg(dev, "BYTE_TEST looks swapped, "
|
||||
"applying WORD_SWAP");
|
||||
smc911x_reg_write(priv, WORD_SWAP, 0xffffffff);
|
||||
|
||||
/* 1 dummy read of BYTE_TEST is needed after a write to
|
||||
* WORD_SWAP before its contents are valid */
|
||||
val = smc911x_reg_read(priv, BYTE_TEST);
|
||||
|
||||
val = smc911x_reg_read(priv, BYTE_TEST);
|
||||
}
|
||||
|
||||
if (val != 0x87654321) {
|
||||
dev_err(dev, "no smc911x found on 0x%p (byte_test=0x%08x)\n",
|
||||
priv->base, val);
|
||||
if (((val >> 16) & 0xFFFF) == (val & 0xFFFF)) {
|
||||
/*
|
||||
* This may mean the chip is set
|
||||
* for 32 bit while the bus is reading 16 bit
|
||||
*/
|
||||
dev_err(dev, "top 16 bits equal to bottom 16 bits\n");
|
||||
}
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
val = smc911x_reg_read(priv, ID_REV);
|
||||
switch (val & 0xFFFF0000) {
|
||||
case 0x01180000:
|
||||
case 0x01170000:
|
||||
case 0x01160000:
|
||||
case 0x01150000:
|
||||
case 0x218A0000:
|
||||
/* LAN911[5678] family */
|
||||
priv->generation = val & 0x0000FFFF;
|
||||
break;
|
||||
|
||||
case 0x118A0000:
|
||||
case 0x117A0000:
|
||||
case 0x116A0000:
|
||||
case 0x115A0000:
|
||||
/* LAN921[5678] family */
|
||||
priv->generation = 3;
|
||||
break;
|
||||
|
||||
case 0x92100000:
|
||||
case 0x92110000:
|
||||
case 0x92200000:
|
||||
case 0x92210000:
|
||||
/* LAN9210/LAN9211/LAN9220/LAN9221 */
|
||||
priv->generation = 4;
|
||||
break;
|
||||
|
||||
default:
|
||||
dev_err(dev, "LAN911x not identified, idrev: 0x%08X\n",
|
||||
val);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
dev_info(dev, "LAN911x identified, idrev: 0x%08X, generation: %d\n",
|
||||
val, priv->generation);
|
||||
|
||||
edev = &priv->edev;
|
||||
edev->priv = priv;
|
||||
|
||||
|
|
@ -732,7 +542,6 @@ static int smc911x_probe(struct device_d *dev)
|
|||
priv->miidev.flags = 0;
|
||||
priv->miidev.edev = edev;
|
||||
priv->miidev.parent = dev;
|
||||
priv->base = base;
|
||||
|
||||
smc911x_reset(edev);
|
||||
smc911x_phy_reset(edev);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,342 @@
|
|||
/*
|
||||
* SMSC LAN9[12]1[567] Network driver
|
||||
*
|
||||
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* Below are the register offsets and bit definitions
|
||||
* of the Lan911x memory space
|
||||
*/
|
||||
|
||||
#define WORD_SWAP 0x98
|
||||
|
||||
#define RX_DATA_FIFO 0x00
|
||||
|
||||
#define TX_DATA_FIFO 0x20
|
||||
#define TX_CMD_A_INT_ON_COMP 0x80000000
|
||||
#define TX_CMD_A_INT_BUF_END_ALGN 0x03000000
|
||||
#define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000
|
||||
#define TX_CMD_A_INT_16_BYTE_ALGN 0x01000000
|
||||
#define TX_CMD_A_INT_32_BYTE_ALGN 0x02000000
|
||||
#define TX_CMD_A_INT_DATA_OFFSET 0x001F0000
|
||||
#define TX_CMD_A_INT_FIRST_SEG 0x00002000
|
||||
#define TX_CMD_A_INT_LAST_SEG 0x00001000
|
||||
#define TX_CMD_A_BUF_SIZE 0x000007FF
|
||||
#define TX_CMD_B_PKT_TAG 0xFFFF0000
|
||||
#define TX_CMD_B_ADD_CRC_DISABLE 0x00002000
|
||||
#define TX_CMD_B_DISABLE_PADDING 0x00001000
|
||||
#define TX_CMD_B_PKT_BYTE_LENGTH 0x000007FF
|
||||
|
||||
#define RX_STATUS_FIFO 0x40
|
||||
#define RX_STS_PKT_LEN 0x3FFF0000
|
||||
#define RX_STS_ES 0x00008000
|
||||
#define RX_STS_BCST 0x00002000
|
||||
#define RX_STS_LEN_ERR 0x00001000
|
||||
#define RX_STS_RUNT_ERR 0x00000800
|
||||
#define RX_STS_MCAST 0x00000400
|
||||
#define RX_STS_TOO_LONG 0x00000080
|
||||
#define RX_STS_COLL 0x00000040
|
||||
#define RX_STS_ETH_TYPE 0x00000020
|
||||
#define RX_STS_WDOG_TMT 0x00000010
|
||||
#define RX_STS_MII_ERR 0x00000008
|
||||
#define RX_STS_DRIBBLING 0x00000004
|
||||
#define RX_STS_CRC_ERR 0x00000002
|
||||
#define RX_STATUS_FIFO_PEEK 0x44
|
||||
#define TX_STATUS_FIFO 0x48
|
||||
#define TX_STS_TAG 0xFFFF0000
|
||||
#define TX_STS_ES 0x00008000
|
||||
#define TX_STS_LOC 0x00000800
|
||||
#define TX_STS_NO_CARR 0x00000400
|
||||
#define TX_STS_LATE_COLL 0x00000200
|
||||
#define TX_STS_MANY_COLL 0x00000100
|
||||
#define TX_STS_COLL_CNT 0x00000078
|
||||
#define TX_STS_MANY_DEFER 0x00000004
|
||||
#define TX_STS_UNDERRUN 0x00000002
|
||||
#define TX_STS_DEFERRED 0x00000001
|
||||
#define TX_STATUS_FIFO_PEEK 0x4C
|
||||
#define ID_REV 0x50
|
||||
#define ID_REV_CHIP_ID 0xFFFF0000 /* RO */
|
||||
#define ID_REV_REV_ID 0x0000FFFF /* RO */
|
||||
|
||||
#define INT_CFG 0x54
|
||||
#define INT_CFG_INT_DEAS 0xFF000000 /* R/W */
|
||||
#define INT_CFG_INT_DEAS_CLR 0x00004000
|
||||
#define INT_CFG_INT_DEAS_STS 0x00002000
|
||||
#define INT_CFG_IRQ_INT 0x00001000 /* RO */
|
||||
#define INT_CFG_IRQ_EN 0x00000100 /* R/W */
|
||||
#define INT_CFG_IRQ_POL 0x00000010 /* R/W Not Affected by SW Reset */
|
||||
#define INT_CFG_IRQ_TYPE 0x00000001 /* R/W Not Affected by SW Reset */
|
||||
|
||||
#define INT_STS 0x58
|
||||
#define INT_STS_SW_INT 0x80000000 /* R/WC */
|
||||
#define INT_STS_TXSTOP_INT 0x02000000 /* R/WC */
|
||||
#define INT_STS_RXSTOP_INT 0x01000000 /* R/WC */
|
||||
#define INT_STS_RXDFH_INT 0x00800000 /* R/WC */
|
||||
#define INT_STS_RXDF_INT 0x00400000 /* R/WC */
|
||||
#define INT_STS_TX_IOC 0x00200000 /* R/WC */
|
||||
#define INT_STS_RXD_INT 0x00100000 /* R/WC */
|
||||
#define INT_STS_GPT_INT 0x00080000 /* R/WC */
|
||||
#define INT_STS_PHY_INT 0x00040000 /* RO */
|
||||
#define INT_STS_PME_INT 0x00020000 /* R/WC */
|
||||
#define INT_STS_TXSO 0x00010000 /* R/WC */
|
||||
#define INT_STS_RWT 0x00008000 /* R/WC */
|
||||
#define INT_STS_RXE 0x00004000 /* R/WC */
|
||||
#define INT_STS_TXE 0x00002000 /* R/WC */
|
||||
//#define INT_STS_ERX 0x00001000 /* R/WC */
|
||||
#define INT_STS_TDFU 0x00000800 /* R/WC */
|
||||
#define INT_STS_TDFO 0x00000400 /* R/WC */
|
||||
#define INT_STS_TDFA 0x00000200 /* R/WC */
|
||||
#define INT_STS_TSFF 0x00000100 /* R/WC */
|
||||
#define INT_STS_TSFL 0x00000080 /* R/WC */
|
||||
//#define INT_STS_RXDF 0x00000040 /* R/WC */
|
||||
#define INT_STS_RDFO 0x00000040 /* R/WC */
|
||||
#define INT_STS_RDFL 0x00000020 /* R/WC */
|
||||
#define INT_STS_RSFF 0x00000010 /* R/WC */
|
||||
#define INT_STS_RSFL 0x00000008 /* R/WC */
|
||||
#define INT_STS_GPIO2_INT 0x00000004 /* R/WC */
|
||||
#define INT_STS_GPIO1_INT 0x00000002 /* R/WC */
|
||||
#define INT_STS_GPIO0_INT 0x00000001 /* R/WC */
|
||||
#define INT_EN 0x5C
|
||||
#define INT_EN_SW_INT_EN 0x80000000 /* R/W */
|
||||
#define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */
|
||||
#define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */
|
||||
#define INT_EN_RXDFH_INT_EN 0x00800000 /* R/W */
|
||||
//#define INT_EN_RXDF_INT_EN 0x00400000 /* R/W */
|
||||
#define INT_EN_TIOC_INT_EN 0x00200000 /* R/W */
|
||||
#define INT_EN_RXD_INT_EN 0x00100000 /* R/W */
|
||||
#define INT_EN_GPT_INT_EN 0x00080000 /* R/W */
|
||||
#define INT_EN_PHY_INT_EN 0x00040000 /* R/W */
|
||||
#define INT_EN_PME_INT_EN 0x00020000 /* R/W */
|
||||
#define INT_EN_TXSO_EN 0x00010000 /* R/W */
|
||||
#define INT_EN_RWT_EN 0x00008000 /* R/W */
|
||||
#define INT_EN_RXE_EN 0x00004000 /* R/W */
|
||||
#define INT_EN_TXE_EN 0x00002000 /* R/W */
|
||||
//#define INT_EN_ERX_EN 0x00001000 /* R/W */
|
||||
#define INT_EN_TDFU_EN 0x00000800 /* R/W */
|
||||
#define INT_EN_TDFO_EN 0x00000400 /* R/W */
|
||||
#define INT_EN_TDFA_EN 0x00000200 /* R/W */
|
||||
#define INT_EN_TSFF_EN 0x00000100 /* R/W */
|
||||
#define INT_EN_TSFL_EN 0x00000080 /* R/W */
|
||||
//#define INT_EN_RXDF_EN 0x00000040 /* R/W */
|
||||
#define INT_EN_RDFO_EN 0x00000040 /* R/W */
|
||||
#define INT_EN_RDFL_EN 0x00000020 /* R/W */
|
||||
#define INT_EN_RSFF_EN 0x00000010 /* R/W */
|
||||
#define INT_EN_RSFL_EN 0x00000008 /* R/W */
|
||||
#define INT_EN_GPIO2_INT 0x00000004 /* R/W */
|
||||
#define INT_EN_GPIO1_INT 0x00000002 /* R/W */
|
||||
#define INT_EN_GPIO0_INT 0x00000001 /* R/W */
|
||||
|
||||
#define BYTE_TEST 0x64
|
||||
#define FIFO_INT 0x68
|
||||
#define FIFO_INT_TX_AVAIL_LEVEL 0xFF000000 /* R/W */
|
||||
#define FIFO_INT_TX_STS_LEVEL 0x00FF0000 /* R/W */
|
||||
#define FIFO_INT_RX_AVAIL_LEVEL 0x0000FF00 /* R/W */
|
||||
#define FIFO_INT_RX_STS_LEVEL 0x000000FF /* R/W */
|
||||
|
||||
#define RX_CFG 0x6C
|
||||
#define RX_CFG_RX_END_ALGN 0xC0000000 /* R/W */
|
||||
#define RX_CFG_RX_END_ALGN4 0x00000000 /* R/W */
|
||||
#define RX_CFG_RX_END_ALGN16 0x40000000 /* R/W */
|
||||
#define RX_CFG_RX_END_ALGN32 0x80000000 /* R/W */
|
||||
#define RX_CFG_RX_DMA_CNT 0x0FFF0000 /* R/W */
|
||||
#define RX_CFG_RX_DUMP 0x00008000 /* R/W */
|
||||
#define RX_CFG_RXDOFF 0x00001F00 /* R/W */
|
||||
//#define RX_CFG_RXBAD 0x00000001 /* R/W */
|
||||
|
||||
#define TX_CFG 0x70
|
||||
//#define TX_CFG_TX_DMA_LVL 0xE0000000 /* R/W */
|
||||
//#define TX_CFG_TX_DMA_CNT 0x0FFF0000 /* R/W Self Clearing */
|
||||
#define TX_CFG_TXS_DUMP 0x00008000 /* Self Clearing */
|
||||
#define TX_CFG_TXD_DUMP 0x00004000 /* Self Clearing */
|
||||
#define TX_CFG_TXSAO 0x00000004 /* R/W */
|
||||
#define TX_CFG_TX_ON 0x00000002 /* R/W */
|
||||
#define TX_CFG_STOP_TX 0x00000001 /* Self Clearing */
|
||||
|
||||
#define HW_CFG 0x74
|
||||
#define HW_CFG_TTM 0x00200000 /* R/W */
|
||||
#define HW_CFG_SF 0x00100000 /* R/W */
|
||||
#define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */
|
||||
#define HW_CFG_TR 0x00003000 /* R/W */
|
||||
#define HW_CFG_PHY_CLK_SEL 0x00000060 /* R/W */
|
||||
#define HW_CFG_PHY_CLK_SEL_INT_PHY 0x00000000 /* R/W */
|
||||
#define HW_CFG_PHY_CLK_SEL_EXT_PHY 0x00000020 /* R/W */
|
||||
#define HW_CFG_PHY_CLK_SEL_CLK_DIS 0x00000040 /* R/W */
|
||||
#define HW_CFG_SMI_SEL 0x00000010 /* R/W */
|
||||
#define HW_CFG_EXT_PHY_DET 0x00000008 /* RO */
|
||||
#define HW_CFG_EXT_PHY_EN 0x00000004 /* R/W */
|
||||
#define HW_CFG_32_16_BIT_MODE 0x00000004 /* RO */
|
||||
#define HW_CFG_SRST_TO 0x00000002 /* RO */
|
||||
#define HW_CFG_SRST 0x00000001 /* Self Clearing */
|
||||
|
||||
#define RX_DP_CTRL 0x78
|
||||
#define RX_DP_CTRL_RX_FFWD 0x80000000 /* R/W */
|
||||
#define RX_DP_CTRL_FFWD_BUSY 0x80000000 /* RO */
|
||||
|
||||
#define RX_FIFO_INF 0x7C
|
||||
#define RX_FIFO_INF_RXSUSED 0x00FF0000 /* RO */
|
||||
#define RX_FIFO_INF_RXDUSED 0x0000FFFF /* RO */
|
||||
|
||||
#define TX_FIFO_INF 0x80
|
||||
#define TX_FIFO_INF_TSUSED 0x00FF0000 /* RO */
|
||||
#define TX_FIFO_INF_TDFREE 0x0000FFFF /* RO */
|
||||
|
||||
#define PMT_CTRL 0x84
|
||||
#define PMT_CTRL_PM_MODE 0x00003000 /* Self Clearing */
|
||||
#define PMT_CTRL_PHY_RST 0x00000400 /* Self Clearing */
|
||||
#define PMT_CTRL_WOL_EN 0x00000200 /* R/W */
|
||||
#define PMT_CTRL_ED_EN 0x00000100 /* R/W */
|
||||
#define PMT_CTRL_PME_TYPE 0x00000040 /* R/W Not Affected by SW Reset */
|
||||
#define PMT_CTRL_WUPS 0x00000030 /* R/WC */
|
||||
#define PMT_CTRL_WUPS_NOWAKE 0x00000000 /* R/WC */
|
||||
#define PMT_CTRL_WUPS_ED 0x00000010 /* R/WC */
|
||||
#define PMT_CTRL_WUPS_WOL 0x00000020 /* R/WC */
|
||||
#define PMT_CTRL_WUPS_MULTI 0x00000030 /* R/WC */
|
||||
#define PMT_CTRL_PME_IND 0x00000008 /* R/W */
|
||||
#define PMT_CTRL_PME_POL 0x00000004 /* R/W */
|
||||
#define PMT_CTRL_PME_EN 0x00000002 /* R/W Not Affected by SW Reset */
|
||||
#define PMT_CTRL_READY 0x00000001 /* RO */
|
||||
|
||||
#define GPIO_CFG 0x88
|
||||
#define GPIO_CFG_LED3_EN 0x40000000 /* R/W */
|
||||
#define GPIO_CFG_LED2_EN 0x20000000 /* R/W */
|
||||
#define GPIO_CFG_LED1_EN 0x10000000 /* R/W */
|
||||
#define GPIO_CFG_GPIO2_INT_POL 0x04000000 /* R/W */
|
||||
#define GPIO_CFG_GPIO1_INT_POL 0x02000000 /* R/W */
|
||||
#define GPIO_CFG_GPIO0_INT_POL 0x01000000 /* R/W */
|
||||
#define GPIO_CFG_EEPR_EN 0x00700000 /* R/W */
|
||||
#define GPIO_CFG_GPIOBUF2 0x00040000 /* R/W */
|
||||
#define GPIO_CFG_GPIOBUF1 0x00020000 /* R/W */
|
||||
#define GPIO_CFG_GPIOBUF0 0x00010000 /* R/W */
|
||||
#define GPIO_CFG_GPIODIR2 0x00000400 /* R/W */
|
||||
#define GPIO_CFG_GPIODIR1 0x00000200 /* R/W */
|
||||
#define GPIO_CFG_GPIODIR0 0x00000100 /* R/W */
|
||||
#define GPIO_CFG_GPIOD4 0x00000010 /* R/W */
|
||||
#define GPIO_CFG_GPIOD3 0x00000008 /* R/W */
|
||||
#define GPIO_CFG_GPIOD2 0x00000004 /* R/W */
|
||||
#define GPIO_CFG_GPIOD1 0x00000002 /* R/W */
|
||||
#define GPIO_CFG_GPIOD0 0x00000001 /* R/W */
|
||||
|
||||
#define GPT_CFG 0x8C
|
||||
#define GPT_CFG_TIMER_EN 0x20000000 /* R/W */
|
||||
#define GPT_CFG_GPT_LOAD 0x0000FFFF /* R/W */
|
||||
|
||||
#define GPT_CNT 0x90
|
||||
#define GPT_CNT_GPT_CNT 0x0000FFFF /* RO */
|
||||
|
||||
#define ENDIAN 0x98
|
||||
#define FREE_RUN 0x9C
|
||||
#define RX_DROP 0xA0
|
||||
#define MAC_CSR_CMD 0xA4
|
||||
#define MAC_CSR_CMD_CSR_BUSY 0x80000000 /* Self Clearing */
|
||||
#define MAC_CSR_CMD_R_NOT_W 0x40000000 /* R/W */
|
||||
#define MAC_CSR_CMD_CSR_ADDR 0x000000FF /* R/W */
|
||||
|
||||
#define MAC_CSR_DATA 0xA8
|
||||
#define AFC_CFG 0xAC
|
||||
#define AFC_CFG_AFC_HI 0x00FF0000 /* R/W */
|
||||
#define AFC_CFG_AFC_LO 0x0000FF00 /* R/W */
|
||||
#define AFC_CFG_BACK_DUR 0x000000F0 /* R/W */
|
||||
#define AFC_CFG_FCMULT 0x00000008 /* R/W */
|
||||
#define AFC_CFG_FCBRD 0x00000004 /* R/W */
|
||||
#define AFC_CFG_FCADD 0x00000002 /* R/W */
|
||||
#define AFC_CFG_FCANY 0x00000001 /* R/W */
|
||||
|
||||
#define E2P_CMD 0xB0
|
||||
#define E2P_CMD_EPC_BUSY 0x80000000 /* Self Clearing */
|
||||
#define E2P_CMD_EPC_CMD 0x70000000 /* R/W */
|
||||
#define E2P_CMD_EPC_CMD_READ 0x00000000 /* R/W */
|
||||
#define E2P_CMD_EPC_CMD_EWDS 0x10000000 /* R/W */
|
||||
#define E2P_CMD_EPC_CMD_EWEN 0x20000000 /* R/W */
|
||||
#define E2P_CMD_EPC_CMD_WRITE 0x30000000 /* R/W */
|
||||
#define E2P_CMD_EPC_CMD_WRAL 0x40000000 /* R/W */
|
||||
#define E2P_CMD_EPC_CMD_ERASE 0x50000000 /* R/W */
|
||||
#define E2P_CMD_EPC_CMD_ERAL 0x60000000 /* R/W */
|
||||
#define E2P_CMD_EPC_CMD_RELOAD 0x70000000 /* R/W */
|
||||
#define E2P_CMD_EPC_TIMEOUT 0x00000200 /* RO */
|
||||
#define E2P_CMD_MAC_ADDR_LOADED 0x00000100 /* RO */
|
||||
#define E2P_CMD_EPC_ADDR 0x000000FF /* R/W */
|
||||
|
||||
#define E2P_DATA 0xB4
|
||||
#define E2P_DATA_EEPROM_DATA 0x000000FF /* R/W */
|
||||
/* end of LAN register offsets and bit definitions */
|
||||
|
||||
/* MAC Control and Status registers */
|
||||
#define MAC_CR 0x01 /* R/W */
|
||||
|
||||
/* MAC_CR - MAC Control Register */
|
||||
#define MAC_CR_RXALL 0x80000000
|
||||
// TODO: delete this bit? It is not described in the data sheet.
|
||||
#define MAC_CR_HBDIS 0x10000000
|
||||
#define MAC_CR_RCVOWN 0x00800000
|
||||
#define MAC_CR_LOOPBK 0x00200000
|
||||
#define MAC_CR_FDPX 0x00100000
|
||||
#define MAC_CR_MCPAS 0x00080000
|
||||
#define MAC_CR_PRMS 0x00040000
|
||||
#define MAC_CR_INVFILT 0x00020000
|
||||
#define MAC_CR_PASSBAD 0x00010000
|
||||
#define MAC_CR_HFILT 0x00008000
|
||||
#define MAC_CR_HPFILT 0x00002000
|
||||
#define MAC_CR_LCOLL 0x00001000
|
||||
#define MAC_CR_BCAST 0x00000800
|
||||
#define MAC_CR_DISRTY 0x00000400
|
||||
#define MAC_CR_PADSTR 0x00000100
|
||||
#define MAC_CR_BOLMT_MASK 0x000000C0
|
||||
#define MAC_CR_DFCHK 0x00000020
|
||||
#define MAC_CR_TXEN 0x00000008
|
||||
#define MAC_CR_RXEN 0x00000004
|
||||
|
||||
#define ADDRH 0x02 /* R/W mask 0x0000FFFFUL */
|
||||
#define ADDRL 0x03 /* R/W mask 0xFFFFFFFFUL */
|
||||
#define HASHH 0x04 /* R/W */
|
||||
#define HASHL 0x05 /* R/W */
|
||||
|
||||
#define MII_ACC 0x06 /* R/W */
|
||||
#define MII_ACC_PHY_ADDR 0x0000F800
|
||||
#define MII_ACC_MIIRINDA 0x000007C0
|
||||
#define MII_ACC_MII_WRITE 0x00000002
|
||||
#define MII_ACC_MII_BUSY 0x00000001
|
||||
|
||||
#define MII_DATA 0x07 /* R/W mask 0x0000FFFFUL */
|
||||
|
||||
#ifdef FLOW
|
||||
#undef FLOW /* clashed with include/asm/cpu/defBF561.h:1654 */
|
||||
#endif
|
||||
|
||||
#define FLOW 0x08 /* R/W */
|
||||
#define FLOW_FCPT 0xFFFF0000
|
||||
#define FLOW_FCPASS 0x00000004
|
||||
#define FLOW_FCEN 0x00000002
|
||||
#define FLOW_FCBSY 0x00000001
|
||||
|
||||
#define VLAN1 0x09 /* R/W mask 0x0000FFFFUL */
|
||||
#define VLAN1_VTI1 0x0000ffff
|
||||
|
||||
#define VLAN2 0x0A /* R/W mask 0x0000FFFFUL */
|
||||
#define VLAN2_VTI2 0x0000ffff
|
||||
|
||||
#define WUFF 0x0B /* WO */
|
||||
|
||||
#define WUCSR 0x0C /* R/W */
|
||||
#define WUCSR_GUE 0x00000200
|
||||
#define WUCSR_WUFR 0x00000040
|
||||
#define WUCSR_MPR 0x00000020
|
||||
#define WUCSR_WAKE_EN 0x00000004
|
||||
#define WUCSR_MPEN 0x00000002
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* (C) Copyright 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Under GPLv2
|
||||
*/
|
||||
|
||||
#ifndef __SMC911X_PLATFORM_H_
|
||||
#define __SMC911X_PLATFORM_H_
|
||||
|
||||
/**
|
||||
* @brief Platform dependent feature:
|
||||
* Pass pointer to this structure as part of device_d -> platform_data
|
||||
*/
|
||||
struct smc911x_plat {
|
||||
int shift;
|
||||
};
|
||||
|
||||
#endif /* __SMC911X_PLATFORM_H_ */
|
||||
Loading…
Reference in New Issue