Add board/cpu specific NAND chip select function to 440 NDFC
Based on idea and implementation from Jeff Mann Patch by Stefan Roese, 20 Oct 2006
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Stefan Roese
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73652699dd
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43a2b0e76a
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@ -7,6 +7,10 @@ Changes since U-Boot 1.1.4:
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* Add (preliminary) support for V38B board
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* Add board/cpu specific NAND chip select function to 440 NDFC
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Based on idea and implementation from Jeff Mann
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Patch by Stefan Roese, 20 Oct 2006
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* PPC405EP: Add support for board configuration of CPC0_PCI register
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This is needed to be able to configure PerWE*/PCI_INT* pin as PerWE*
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Patch by Tolunay Orkun, 07 Apr 2006
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@ -178,6 +178,14 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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printf("Device %d: %s", dev, nand_info[dev].name);
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puts("... is now current device\n");
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nand_curr_device = dev;
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#ifdef CFG_NAND_SELECT_DEVICE
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/*
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* Select the chip in the board/cpu specific driver
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*/
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board_nand_select_device(nand_info[dev].priv, dev);
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#endif
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return 0;
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}
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@ -66,7 +66,7 @@ static void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
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static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte)
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{
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struct nand_chip *this = mtdinfo->priv;
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ulong base = (ulong) this->IO_ADDR_W;
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ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
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if (hwctl & 0x1)
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out8(base + NDFC_CMD, byte);
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@ -79,7 +79,7 @@ static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte)
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static u_char ndfc_read_byte(struct mtd_info *mtdinfo)
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{
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struct nand_chip *this = mtdinfo->priv;
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ulong base = (ulong) this->IO_ADDR_W;
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ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
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return (in8(base + NDFC_DATA));
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}
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@ -87,7 +87,7 @@ static u_char ndfc_read_byte(struct mtd_info *mtdinfo)
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static int ndfc_dev_ready(struct mtd_info *mtdinfo)
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{
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struct nand_chip *this = mtdinfo->priv;
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ulong base = (ulong) this->IO_ADDR_W;
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ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
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while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY))
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;
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@ -111,30 +111,30 @@ static int ndfc_dev_ready(struct mtd_info *mtdinfo)
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static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
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{
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struct nand_chip *this = mtdinfo->priv;
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ulong base = (ulong) this->IO_ADDR_W;
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ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
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uint32_t *p = (uint32_t *) buf;
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for(;len > 0; len -= 4)
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for (;len > 0; len -= 4)
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*p++ = in32(base + NDFC_DATA);
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}
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static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
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{
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struct nand_chip *this = mtdinfo->priv;
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ulong base = (ulong) this->IO_ADDR_W;
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ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
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uint32_t *p = (uint32_t *) buf;
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for(; len > 0; len -= 4)
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for (; len > 0; len -= 4)
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out32(base + NDFC_DATA, *p++);
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}
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static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
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{
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struct nand_chip *this = mtdinfo->priv;
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ulong base = (ulong) this->IO_ADDR_W;
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ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
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uint32_t *p = (uint32_t *) buf;
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for(; len > 0; len -= 4)
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for (; len > 0; len -= 4)
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if (*p++ != in32(base + NDFC_DATA))
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return -1;
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@ -142,8 +142,20 @@ static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len
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}
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#endif /* #ifndef CONFIG_NAND_SPL */
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void board_nand_select_device(struct nand_chip *nand, int chip)
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{
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ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
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/* Set NandFlash Core Configuration Register */
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/* 1col x 2 rows */
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out32(base + NDFC_CCR, 0x00000000 | (chip << 24));
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}
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void board_nand_init(struct nand_chip *nand)
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{
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int chip = (ulong)nand->IO_ADDR_W & 0x00000003;
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ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
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nand->eccmode = NAND_ECC_SOFT;
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nand->hwcontrol = ndfc_hwcontrol;
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@ -166,10 +178,11 @@ void board_nand_init(struct nand_chip *nand)
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mtebc(pb0ap, CFG_EBC_PB0AP);
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#endif
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/* Set NandFlash Core Configuration Register */
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/* Chip select 3, 1col x 2 rows */
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out32(CFG_NAND_BASE + NDFC_CCR, 0x00000000 | (CFG_NAND_CS << 24));
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out32(CFG_NAND_BASE + NDFC_BCFG0 + (CFG_NAND_CS << 2), 0x80002222);
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/*
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* Select required NAND chip in NDFC
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*/
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board_nand_select_device(nand, chip);
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out32(base + NDFC_BCFG0 + (chip << 2), 0x80002222);
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}
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#endif
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@ -66,8 +66,15 @@ void nand_init(void)
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size += nand_info[i].size;
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if (nand_curr_device == -1)
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nand_curr_device = i;
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}
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}
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printf("%lu MiB\n", size / (1024 * 1024));
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#ifdef CFG_NAND_SELECT_DEVICE
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/*
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* Select the chip in the board/cpu specific driver
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*/
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board_nand_select_device(nand_info[nand_curr_device].priv, nand_curr_device);
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#endif
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}
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#endif
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@ -134,13 +134,6 @@
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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#endif
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/*-----------------------------------------------------------------------
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* NAND FLASH
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*----------------------------------------------------------------------*/
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#define CFG_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CFG_NAND_BASE CFG_NAND_ADDR
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/*
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* IPL (Initial Program Loader, integrated inside CPU)
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* Will load first 4k from NAND (SPL) into cache and execute it from there.
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@ -405,6 +398,14 @@
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#define CFG_EBC_PB2AP 0x24814580
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#define CFG_EBC_PB2CR (CFG_CPLD | 0x38000)
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/*-----------------------------------------------------------------------
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* NAND FLASH
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*----------------------------------------------------------------------*/
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#define CFG_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
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#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*----------------------------------------------------------------------*/
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@ -117,4 +117,8 @@ int nand_lock( nand_info_t *meminfo, int tight );
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int nand_unlock( nand_info_t *meminfo, ulong start, ulong length );
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int nand_get_lock_status(nand_info_t *meminfo, ulong offset);
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#ifdef CFG_NAND_SELECT_DEVICE
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void board_nand_select_device(struct nand_chip *nand, int chip);
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#endif
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#endif
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