ARM: i.MX25: Add missing GPT clock lookups
Only one GPT will be used, but with devicetree support we can't predict which one it is, so we need the clock lookup for all GPTs to ensure that the timer gets its clock. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -140,6 +140,9 @@ static int imx25_ccm_probe(struct device_d *dev)
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clkdev_add_physbase(clks[per15], MX25_UART4_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per15], MX25_UART5_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per5], MX25_GPT1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per5], MX25_GPT2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per5], MX25_GPT3_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per5], MX25_GPT4_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[ipg], MX25_FEC_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[ipg], MX25_I2C1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[ipg], MX25_I2C2_BASE_ADDR, NULL);
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@ -35,6 +35,9 @@
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#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
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#define MX25_CCM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
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#define MX25_GPT4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x84000)
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#define MX25_GPT3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x88000)
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#define MX25_GPT2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x8c000)
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#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
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#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000)
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#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000)
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