dts: update to v4.1-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
6345d37ae5
commit
461f8cfc7e
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@ -0,0 +1,20 @@
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* ARC Performance Counters
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The ARC700 can be configured with a pipeline performance monitor for counting
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CPU and cache events like cache misses and hits. Like conventional PCT there
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are 100+ hardware conditions dynamically mapped to upto 32 counters
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Note that:
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* The ARC 700 PCT does not support interrupts; although HW events may be
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counted, the HW events themselves cannot serve as a trigger for a sample.
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Required properties:
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- compatible : should contain
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"snps,arc700-pct"
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Example:
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pmu {
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compatible = "snps,arc700-pct";
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};
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@ -1,24 +0,0 @@
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* ARC Performance Monitor Unit
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The ARC 700 can be configured with a pipeline performance monitor for counting
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CPU and cache events like cache misses and hits.
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Note that:
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* ARC 700 refers to a family of ARC processor cores;
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- There is only one type of PMU available for the whole family;
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- The PMU may support different sets of events; supported events are probed
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at boot time, as required by the reference manual.
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* The ARC 700 PMU does not support interrupts; although HW events may be
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counted, the HW events themselves cannot serve as a trigger for a sample.
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Required properties:
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- compatible : should contain
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"snps,arc700-pmu"
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Example:
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pmu {
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compatible = "snps,arc700-pmu";
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};
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@ -0,0 +1,88 @@
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Annapurna Labs Alpine Platform Device Tree Bindings
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---------------------------------------------------------------
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Boards in the Alpine family shall have the following properties:
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* Required root node properties:
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compatible: must contain "al,alpine"
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* Example:
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/ {
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model = "Annapurna Labs Alpine Dev Board";
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compatible = "al,alpine";
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...
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}
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* CPU node:
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The Alpine platform includes cortex-a15 cores.
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enable-method: must be "al,alpine-smp" to allow smp [1]
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Example:
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "al,alpine-smp";
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cpu@0 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <1>;
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};
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cpu@2 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <3>;
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};
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};
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* Alpine CPU resume registers
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The CPU resume register are used to define required resume address after
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reset.
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Properties:
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- compatible : Should contain "al,alpine-cpu-resume".
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- reg : Offset and length of the register set for the device
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Example:
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cpu_resume {
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compatible = "al,alpine-cpu-resume";
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reg = <0xfbff5ed0 0x30>;
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};
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* Alpine System-Fabric Service Registers
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The System-Fabric Service Registers allow various operation on CPU and
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system fabric, like powering CPUs off.
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Properties:
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- compatible : Should contain "al,alpine-sysfabric-service" and "syscon".
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- reg : Offset and length of the register set for the device
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Example:
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nb_service {
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compatible = "al,alpine-sysfabric-service", "syscon";
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reg = <0xfb070000 0x10000>;
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};
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[1] arm/cpu-enable-method/al,alpine-smp
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@ -0,0 +1,14 @@
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Altera's SoCFPGA platform device tree bindings
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---------------------------------------------
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Boards with Cyclone 5 SoC:
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Required root node properties:
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compatible = "altr,socfpga-cyclone5", "altr,socfpga";
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Boards with Arria 5 SoC:
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Required root node properties:
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compatible = "altr,socfpga-arria5", "altr,socfpga";
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Boards with Arria 10 SoC:
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Required root node properties:
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compatible = "altr,socfpga-arria10", "altr,socfpga";
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@ -8,3 +8,7 @@ Boards with the Amlogic Meson6 SoC shall have the following properties:
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Boards with the Amlogic Meson8 SoC shall have the following properties:
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Required root node property:
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compatible: "amlogic,meson8";
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Board compatible values:
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- "geniatech,atv1200"
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- "minix,neo-x8"
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@ -17,7 +17,10 @@ to deliver its interrupts via SPIs.
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- interrupts : Interrupt list for secure, non-secure, virtual and
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hypervisor timers, in that order.
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- clock-frequency : The frequency of the main counter, in Hz. Optional.
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- clock-frequency : The frequency of the main counter, in Hz. Should be present
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only where necessary to work around broken firmware which does not configure
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CNTFRQ on all CPUs to a uniform correct value. Use of this property is
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strongly discouraged; fix your firmware unless absolutely impossible.
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- always-on : a boolean property. If present, the timer is powered through an
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always-on power domain, therefore it never loses context.
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@ -46,7 +49,8 @@ Example:
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- compatible : Should at least contain "arm,armv7-timer-mem".
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- clock-frequency : The frequency of the main counter, in Hz. Optional.
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- clock-frequency : The frequency of the main counter, in Hz. Should be present
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only when firmware has not configured the MMIO CNTFRQ registers.
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- reg : The control frame base address.
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@ -0,0 +1,20 @@
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Marvell Armada 39x Platforms Device Tree Bindings
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-------------------------------------------------
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Boards with a SoC of the Marvell Armada 39x family shall have the
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following property:
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Required root node property:
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- compatible: must contain "marvell,armada390"
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In addition, boards using the Marvell Armada 398 SoC shall have the
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following property before the previous one:
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Required root node property:
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compatible: must contain "marvell,armada398"
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Example:
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compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390";
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@ -46,10 +46,12 @@ PIT Timer required properties:
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shared across all System Controller members.
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System Timer (ST) required properties:
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- compatible: Should be "atmel,at91rm9200-st"
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- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd"
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- reg: Should contain registers location and length
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- interrupts: Should contain interrupt for the ST which is the IRQ line
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shared across all System Controller members.
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Its subnodes can be:
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- watchdog: compatible should be "atmel,at91rm9200-wdt"
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TC/TCLIB Timer required properties:
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- compatible: Should be "atmel,<chip>-tcb".
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@ -94,8 +94,11 @@ specific to ARM.
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- compatible
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Usage: required
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Value type: <string>
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Definition: must be "arm,cci-400-pmu"
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Definition: Must contain one of:
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"arm,cci-400-pmu,r0"
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"arm,cci-400-pmu,r1"
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"arm,cci-400-pmu" - DEPRECATED, permitted only where OS has
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secure acces to CCI registers
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- reg:
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Usage: required
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Value type: Integer cells. A register entry, expressed
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@ -61,7 +61,6 @@ Example:
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0 0x20010000 0 0x1000>;
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coresight-default-sink;
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clocks = <&oscclk6a>;
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clock-names = "apb_pclk";
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port {
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@ -0,0 +1,52 @@
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========================================================
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Secondary CPU enable-method "al,alpine-smp" binding
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========================================================
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This document describes the "al,alpine-smp" method for
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enabling secondary CPUs. To apply to all CPUs, a single
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"al,alpine-smp" enable method should be defined in the
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"cpus" node.
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Enable method name: "al,alpine-smp"
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Compatible machines: "al,alpine"
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Compatible CPUs: "arm,cortex-a15"
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Related properties: (none)
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Note:
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This enable method requires valid nodes compatible with
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"al,alpine-cpu-resume" and "al,alpine-nb-service"[1].
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Example:
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "al,alpine-smp";
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cpu@0 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <1>;
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};
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cpu@2 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <3>;
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};
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};
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--
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[1] arm/al,alpine.txt
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@ -192,6 +192,7 @@ nodes to be present and contain the properties described below.
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"brcm,brahma-b15"
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"marvell,armada-375-smp"
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"marvell,armada-380-smp"
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"marvell,armada-390-smp"
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"marvell,armada-xp-smp"
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"qcom,gcc-msm8660"
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"qcom,kpss-acc-v1"
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@ -22,6 +22,9 @@ Optional Properties:
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- pclkN, clkN: Pairs of parent of input clock and input clock to the
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devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
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are supported currently.
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- asbN: Clocks required by asynchronous bridges (ASB) present in
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the power domain. These clock should be enabled during power
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domain on/off operations.
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- power-domains: phandle pointing to the parent power domain, for more details
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see Documentation/devicetree/bindings/power/power_domain.txt
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@ -0,0 +1,14 @@
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Freescale Vybrid Miscellaneous System Control - CPU Configuration
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The MSCM IP contains multiple sub modules, this binding describes the first
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block of registers which contains CPU configuration information.
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Required properties:
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- compatible: "fsl,vf610-mscm-cpucfg", "syscon"
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- reg: the register range of the MSCM CPU configuration registers
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Example:
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mscm_cpucfg: cpucfg@40001000 {
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compatible = "fsl,vf610-mscm-cpucfg", "syscon";
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reg = <0x40001000 0x800>;
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}
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@ -0,0 +1,33 @@
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Freescale Vybrid Miscellaneous System Control - Interrupt Router
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The MSCM IP contains multiple sub modules, this binding describes the second
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block of registers which control the interrupt router. The interrupt router
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allows to configure the recipient of each peripheral interrupt. Furthermore
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it controls the directed processor interrupts. The module is available in all
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Vybrid SoC's but is only really useful in dual core configurations (VF6xx
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which comes with a Cortex-A5/Cortex-M4 combination).
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Required properties:
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- compatible: "fsl,vf610-mscm-ir"
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- reg: the register range of the MSCM Interrupt Router
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- fsl,cpucfg: The handle to the MSCM CPU configuration node, required
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to get the current CPU ID
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- interrupt-controller: Identifies the node as an interrupt controller
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- #interrupt-cells: Two cells, interrupt number and cells.
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The hardware interrupt number according to interrupt
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assignment of the interrupt router is required.
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Flags get passed only when using GIC as parent. Flags
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encoding as documented by the GIC bindings.
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- interrupt-parent: Should be the phandle for the interrupt controller of
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the CPU the device tree is intended to be used on. This
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is either the node of the GIC or NVIC controller.
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Example:
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mscm_ir: interrupt-controller@40001800 {
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compatible = "fsl,vf610-mscm-ir";
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reg = <0x40001800 0x400>;
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fsl,cpucfg = <&mscm_cpucfg>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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}
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@ -1,5 +0,0 @@
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Geniatech platforms device tree bindings
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-------------------------------------------
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Geniatech ATV1200
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- compatible = "geniatech,atv1200"
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@ -18,6 +18,8 @@ Main node required properties:
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"arm,arm11mp-gic"
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"brcm,brahma-b15-gic"
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"arm,arm1176jzf-devchip-gic"
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"qcom,msm-8660-qgic"
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"qcom,msm-qgic2"
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The type shall be a <u32> and the value shall be 3.
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@ -56,11 +58,6 @@ Optional
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regions, used when the GIC doesn't have banked registers. The offset is
|
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cpu-offset * cpu-nr.
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- arm,routable-irqs : Total number of gic irq inputs which are not directly
|
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connected from the peripherals, but are routed dynamically
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by a crossbar/multiplexer preceding the GIC. The GIC irq
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input line is assigned dynamically when the corresponding
|
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peripheral's crossbar line is mapped.
|
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Example:
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intc: interrupt-controller@fff11000 {
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@ -68,7 +65,6 @@ Example:
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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arm,routable-irqs = <160>;
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reg = <0xfff11000 0x1000>,
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<0xfff10100 0x100>;
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||||
};
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|
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@ -42,6 +42,7 @@ board. Currently known boards are:
|
|||
"lacie,cloudbox"
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"lacie,inetspace_v2"
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"lacie,laplug"
|
||||
"lacie,nas2big"
|
||||
"lacie,netspace_lite_v2"
|
||||
"lacie,netspace_max_v2"
|
||||
"lacie,netspace_mini_v2"
|
||||
|
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@ -0,0 +1,84 @@
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QCOM Idle States for cpuidle driver
|
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||||
ARM provides idle-state node to define the cpuidle states, as defined in [1].
|
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cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
|
||||
states. Idle states have different enter/exit latency and residency values.
|
||||
The idle states supported by the QCOM SoC are defined as -
|
||||
|
||||
* Standby
|
||||
* Retention
|
||||
* Standalone Power Collapse (Standalone PC or SPC)
|
||||
* Power Collapse (PC)
|
||||
|
||||
Standby: Standby does a little more in addition to architectural clock gating.
|
||||
When the WFI instruction is executed the ARM core would gate its internal
|
||||
clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
|
||||
trigger to execute the SPM state machine. The SPM state machine waits for the
|
||||
interrupt to trigger the core back in to active. This triggers the cache
|
||||
hierarchy to enter standby states, when all cpus are idle. An interrupt brings
|
||||
the SPM state machine out of its wait, the next step is to ensure that the
|
||||
cache hierarchy is also out of standby, and then the cpu is allowed to resume
|
||||
execution. This state is defined as a generic ARM WFI state by the ARM cpuidle
|
||||
driver and is not defined in the DT. The SPM state machine should be
|
||||
configured to execute this state by default and after executing every other
|
||||
state below.
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||||
|
||||
Retention: Retention is a low power state where the core is clock gated and
|
||||
the memory and the registers associated with the core are retained. The
|
||||
voltage may be reduced to the minimum value needed to keep the processor
|
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registers active. The SPM should be configured to execute the retention
|
||||
sequence and would wait for interrupt, before restoring the cpu to execution
|
||||
state. Retention may have a slightly higher latency than Standby.
|
||||
|
||||
Standalone PC: A cpu can power down and warmboot if there is a sufficient time
|
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between the time it enters idle and the next known wake up. SPC mode is used
|
||||
to indicate a core entering a power down state without consulting any other
|
||||
cpu or the system resources. This helps save power only on that core. The SPM
|
||||
sequence for this idle state is programmed to power down the supply to the
|
||||
core, wait for the interrupt, restore power to the core, and ensure the
|
||||
system state including cache hierarchy is ready before allowing core to
|
||||
resume. Applying power and resetting the core causes the core to warmboot
|
||||
back into Elevation Level (EL) which trampolines the control back to the
|
||||
kernel. Entering a power down state for the cpu, needs to be done by trapping
|
||||
into a EL. Failing to do so, would result in a crash enforced by the warm boot
|
||||
code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
|
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be flushed in s/w, before powering down the core.
|
||||
|
||||
Power Collapse: This state is similar to the SPC mode, but distinguishes
|
||||
itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
|
||||
modes. In a hierarchical power domain SoC, this means L2 and other caches can
|
||||
be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
|
||||
voltages reduced, provided all cpus enter this state. Since the span of low
|
||||
power modes possible at this state is vast, the exit latency and the residency
|
||||
of this low power mode would be considered high even though at a cpu level,
|
||||
this essentially is cpu power down. The SPM in this state also may handshake
|
||||
with the Resource power manager (RPM) processor in the SoC to indicate a
|
||||
complete application processor subsystem shut down.
|
||||
|
||||
The idle-state for QCOM SoCs are distinguished by the compatible property of
|
||||
the idle-states device node.
|
||||
|
||||
The devicetree representation of the idle state should be -
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Must be one of -
|
||||
"qcom,idle-state-ret",
|
||||
"qcom,idle-state-spc",
|
||||
"qcom,idle-state-pc",
|
||||
and "arm,idle-state".
|
||||
|
||||
Other required and optional properties are specified in [1].
|
||||
|
||||
Example:
|
||||
|
||||
idle-states {
|
||||
CPU_SPC: spc {
|
||||
compatible = "qcom,idle-state-spc", "arm,idle-state";
|
||||
entry-latency-us = <150>;
|
||||
exit-latency-us = <200>;
|
||||
min-residency-us = <2000>;
|
||||
};
|
||||
};
|
||||
|
||||
[1]. Documentation/devicetree/bindings/arm/idle-states.txt
|
||||
|
|
@ -2,22 +2,31 @@ SPM AVS Wrapper 2 (SAW2)
|
|||
|
||||
The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
|
||||
Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
|
||||
micro-controller that transitions a piece of hardware (like a processor or
|
||||
power-controller that transitions a piece of hardware (like a processor or
|
||||
subsystem) into and out of low power modes via a direct connection to
|
||||
the PMIC. It can also be wired up to interact with other processors in the
|
||||
system, notifying them when a low power state is entered or exited.
|
||||
|
||||
Multiple revisions of the SAW hardware are supported using these Device Nodes.
|
||||
SAW2 revisions differ in the register offset and configuration data. Also, the
|
||||
same revision of the SAW in different SoCs may have different configuration
|
||||
data due the the differences in hardware capabilities. Hence the SoC name, the
|
||||
version of the SAW hardware in that SoC and the distinction between cpu (big
|
||||
or Little) or cache, may be needed to uniquely identify the SAW register
|
||||
configuration and initialization data. The compatible string is used to
|
||||
indicate this parameter.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: shall contain "qcom,saw2". A more specific value should be
|
||||
one of:
|
||||
"qcom,saw2-v1"
|
||||
"qcom,saw2-v1.1"
|
||||
"qcom,saw2-v2"
|
||||
"qcom,saw2-v2.1"
|
||||
Definition: Must have
|
||||
"qcom,saw2"
|
||||
A more specific value could be one of:
|
||||
"qcom,apq8064-saw2-v1.1-cpu"
|
||||
"qcom,msm8974-saw2-v2.1-cpu"
|
||||
"qcom,apq8084-saw2-v2.1-cpu"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
|
|
@ -26,10 +35,23 @@ PROPERTIES
|
|||
the register region. An optional second element specifies
|
||||
the base address and size of the alias register region.
|
||||
|
||||
- regulator:
|
||||
Usage: optional
|
||||
Value type: boolean
|
||||
Definition: Indicates that this SPM device acts as a regulator device
|
||||
device for the core (CPU or Cache) the SPM is attached
|
||||
to.
|
||||
|
||||
Example:
|
||||
Example 1:
|
||||
|
||||
regulator@2099000 {
|
||||
power-controller@2099000 {
|
||||
compatible = "qcom,saw2";
|
||||
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
|
||||
regulator;
|
||||
};
|
||||
|
||||
Example 2:
|
||||
saw0: power-controller@f9089000 {
|
||||
compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
|
||||
reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,11 +9,17 @@ Properties:
|
|||
"qcom,scss-timer" - scorpion subsystem
|
||||
|
||||
- interrupts : Interrupts for the debug timer, the first general purpose
|
||||
timer, and optionally a second general purpose timer in that
|
||||
order.
|
||||
timer, and optionally a second general purpose timer, and
|
||||
optionally as well, 2 watchdog interrupts, in that order.
|
||||
|
||||
- reg : Specifies the base address of the timer registers.
|
||||
|
||||
- clocks: Reference to the parent clocks, one per output clock. The parents
|
||||
must appear in the same order as the clock names.
|
||||
|
||||
- clock-names: The name of the clocks as free-form strings. They should be in
|
||||
the same order as the clocks.
|
||||
|
||||
- clock-frequency : The frequency of the debug timer and the general purpose
|
||||
timer(s) in Hz in that order.
|
||||
|
||||
|
|
@ -29,9 +35,13 @@ Example:
|
|||
compatible = "qcom,scss-timer", "qcom,msm-timer";
|
||||
interrupts = <1 1 0x301>,
|
||||
<1 2 0x301>,
|
||||
<1 3 0x301>;
|
||||
<1 3 0x301>,
|
||||
<1 4 0x301>,
|
||||
<1 5 0x301>;
|
||||
reg = <0x0200a000 0x100>;
|
||||
clock-frequency = <19200000>,
|
||||
<32768>;
|
||||
clocks = <&sleep_clk>;
|
||||
clock-names = "sleep";
|
||||
cpu-offset = <0x40000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,7 +9,9 @@ inputs.
|
|||
Required properties:
|
||||
- compatible : Should be "ti,irq-crossbar"
|
||||
- reg: Base address and the size of the crossbar registers.
|
||||
- ti,max-irqs: Total number of irqs available at the interrupt controller.
|
||||
- interrupt-controller: indicates that this block is an interrupt controller.
|
||||
- interrupt-parent: the interrupt controller this block is connected to.
|
||||
- ti,max-irqs: Total number of irqs available at the parent interrupt controller.
|
||||
- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
|
||||
- ti,reg-size: Size of a individual register in bytes. Every individual
|
||||
register is assumed to be of same size. Valid sizes are 1, 2, 4.
|
||||
|
|
@ -27,13 +29,13 @@ Optional properties:
|
|||
when the interrupt controller irq is unused (when not provided, default is 0)
|
||||
|
||||
Examples:
|
||||
crossbar_mpu: @4a020000 {
|
||||
crossbar_mpu: crossbar@4a002a48 {
|
||||
compatible = "ti,irq-crossbar";
|
||||
reg = <0x4a002a48 0x130>;
|
||||
ti,max-irqs = <160>;
|
||||
ti,max-crossbar-sources = <400>;
|
||||
ti,reg-size = <2>;
|
||||
ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
|
||||
ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
|
||||
ti,irqs-skip = <10 133 139 140>;
|
||||
};
|
||||
|
||||
|
|
@ -44,10 +46,6 @@ Documentation/devicetree/bindings/arm/gic.txt for further details.
|
|||
|
||||
An interrupt consumer on an SoC using crossbar will use:
|
||||
interrupts = <GIC_SPI request_number interrupt_level>
|
||||
When the request number is between 0 to that described by
|
||||
"ti,max-crossbar-sources", it is assumed to be a crossbar mapping. If the
|
||||
request_number is greater than "ti,max-crossbar-sources", then it is mapped as a
|
||||
quirky hardware mapping direct to GIC.
|
||||
|
||||
Example:
|
||||
device_x@0x4a023000 {
|
||||
|
|
@ -55,9 +53,3 @@ Example:
|
|||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
...
|
||||
};
|
||||
|
||||
device_y@0x4a033000 {
|
||||
/* Direct mapped GIC SPI 1 used */
|
||||
interrupts = <GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH>;
|
||||
...
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,79 @@
|
|||
OMAP Control Module bindings
|
||||
|
||||
Control Module contains miscellaneous features under it based on SoC type.
|
||||
Pincontrol is one common feature, and it has a specialized support
|
||||
described in [1]. Typically some clock nodes are also under control module.
|
||||
Syscon is used to share register level access to drivers external to
|
||||
control module driver itself.
|
||||
|
||||
See [2] for documentation about clock/clockdomain nodes.
|
||||
|
||||
[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
|
||||
[2] Documentation/devicetree/bindings/clock/ti/*
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be one of:
|
||||
"ti,am3-scm"
|
||||
"ti,am4-scm"
|
||||
"ti,dm814-scrm"
|
||||
"ti,dm816-scrm"
|
||||
"ti,omap2-scm"
|
||||
"ti,omap3-scm"
|
||||
"ti,omap4-scm-core"
|
||||
"ti,omap4-scm-padconf-core"
|
||||
"ti,omap5-scm-core"
|
||||
"ti,omap5-scm-padconf-core"
|
||||
"ti,dra7-scm-core"
|
||||
- reg: Contains Control Module register address range
|
||||
(base address and length)
|
||||
|
||||
Optional properties:
|
||||
- clocks: clocks for this module
|
||||
- clockdomains: clockdomains for this module
|
||||
|
||||
Examples:
|
||||
|
||||
scm: scm@2000 {
|
||||
compatible = "ti,omap3-scm", "simple-bus";
|
||||
reg = <0x2000 0x2000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x2000 0x2000>;
|
||||
|
||||
omap3_pmx_core: pinmux@30 {
|
||||
compatible = "ti,omap3-padconf",
|
||||
"pinctrl-single";
|
||||
reg = <0x30 0x230>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
pinctrl-single,register-width = <16>;
|
||||
pinctrl-single,function-mask = <0xff1f>;
|
||||
};
|
||||
|
||||
scm_conf: scm_conf@270 {
|
||||
compatible = "syscon";
|
||||
reg = <0x270 0x330>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
scm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
scm_clockdomains: clockdomains {
|
||||
};
|
||||
}
|
||||
|
||||
&scm_clocks {
|
||||
mcbsp5_mux_fck: mcbsp5_mux_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-mux-clock";
|
||||
clocks = <&core_96m_fck>, <&mcbsp_clks>;
|
||||
ti,bit-shift = <4>;
|
||||
reg = <0x02d8>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
L4 interconnect bindings
|
||||
|
||||
These bindings describe the OMAP SoCs L4 interconnect bus.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus
|
||||
Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus
|
||||
Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus
|
||||
Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus
|
||||
Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus
|
||||
Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus
|
||||
Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus
|
||||
Should be "ti,dra7-l4-cfg" for DRA7 family l4 cfg bus
|
||||
Should be "ti,dra7-l4-wkup" for DRA7 family l4 wkup bus
|
||||
Should be "ti,am3-l4-wkup" for AM33xx family l4 wkup bus
|
||||
Should be "ti,am4-l4-wkup" for AM43xx family l4 wkup bus
|
||||
- ranges : contains the IO map range for the bus
|
||||
|
||||
Examples:
|
||||
|
||||
l4: l4@48000000 {
|
||||
compatible "ti,omap2-l4", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x48000000 0x100000>;
|
||||
};
|
||||
|
|
@ -10,14 +10,10 @@ documentation about the individual clock/clockdomain nodes.
|
|||
Required properties:
|
||||
- compatible: Must be one of:
|
||||
"ti,am3-prcm"
|
||||
"ti,am3-scrm"
|
||||
"ti,am4-prcm"
|
||||
"ti,am4-scrm"
|
||||
"ti,omap2-prcm"
|
||||
"ti,omap2-scrm"
|
||||
"ti,omap3-prm"
|
||||
"ti,omap3-cm"
|
||||
"ti,omap3-scrm"
|
||||
"ti,omap4-cm1"
|
||||
"ti,omap4-prm"
|
||||
"ti,omap4-cm2"
|
||||
|
|
@ -29,6 +25,8 @@ Required properties:
|
|||
"ti,dra7-prm"
|
||||
"ti,dra7-cm-core-aon"
|
||||
"ti,dra7-cm-core"
|
||||
"ti,dm814-prcm"
|
||||
"ti,dm816-prcm"
|
||||
- reg: Contains PRCM module register address range
|
||||
(base address and length)
|
||||
- clocks: clocks for this module
|
||||
|
|
|
|||
|
|
@ -18,12 +18,21 @@ Required properties:
|
|||
"arm,arm11mpcore-pmu"
|
||||
"arm,arm1176-pmu"
|
||||
"arm,arm1136-pmu"
|
||||
"qcom,scorpion-pmu"
|
||||
"qcom,scorpion-mp-pmu"
|
||||
"qcom,krait-pmu"
|
||||
- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
|
||||
interrupt (PPI) then 1 interrupt should be specified.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- interrupt-affinity : Valid only when using SPIs, specifies a list of phandles
|
||||
to CPU nodes corresponding directly to the affinity of
|
||||
the SPIs listed in the interrupts property.
|
||||
|
||||
This property should be present when there is more than
|
||||
a single SPI.
|
||||
|
||||
- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
|
||||
events.
|
||||
|
||||
|
|
|
|||
|
|
@ -22,3 +22,7 @@ Rockchip platforms device tree bindings
|
|||
- compatible = "firefly,firefly-rk3288", "rockchip,rk3288";
|
||||
or
|
||||
- compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288";
|
||||
|
||||
- ChipSPARK PopMetal-RK3288 board:
|
||||
Required root node properties:
|
||||
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
|
||||
|
|
|
|||
|
|
@ -29,10 +29,27 @@ Properties:
|
|||
- clocks : list of phandles and specifiers to all input clocks listed in
|
||||
clock-names property.
|
||||
|
||||
Optional properties:
|
||||
|
||||
Some PMUs are capable of behaving as an interrupt controller (mostly
|
||||
to wake up a suspended PMU). In which case, they can have the
|
||||
following properties:
|
||||
|
||||
- interrupt-controller: indicate that said PMU is an interrupt controller
|
||||
|
||||
- #interrupt-cells: must be identical to the that of the parent interrupt
|
||||
controller.
|
||||
|
||||
- interrupt-parent: a phandle indicating which interrupt controller
|
||||
this PMU signals interrupts to.
|
||||
|
||||
Example :
|
||||
pmu_system_controller: system-controller@10040000 {
|
||||
compatible = "samsung,exynos5250-pmu", "syscon";
|
||||
reg = <0x10040000 0x5000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
|
||||
"clkout4", "clkout8", "clkout9";
|
||||
|
|
|
|||
|
|
@ -7,8 +7,6 @@ SoCs:
|
|||
compatible = "renesas,emev2"
|
||||
- RZ/A1H (R7S72100)
|
||||
compatible = "renesas,r7s72100"
|
||||
- SH-Mobile AP4 (R8A73720/SH7372)
|
||||
compatible = "renesas,sh7372"
|
||||
- SH-Mobile AG5 (R8A73A00/SH73A0)
|
||||
compatible = "renesas,sh73a0"
|
||||
- R-Mobile APE6 (R8A73A40)
|
||||
|
|
@ -37,8 +35,6 @@ Boards:
|
|||
compatible = "renesas,alt", "renesas,r8a7794"
|
||||
- APE6-EVM
|
||||
compatible = "renesas,ape6evm", "renesas,r8a73a4"
|
||||
- APE6-EVM - Reference Device Tree Implementation
|
||||
compatible = "renesas,ape6evm-reference", "renesas,r8a73a4"
|
||||
- Atmark Techno Armadillo-800 EVA
|
||||
compatible = "renesas,armadillo800eva"
|
||||
- BOCK-W
|
||||
|
|
@ -57,12 +53,8 @@ Boards:
|
|||
compatible = "renesas,kzm9d", "renesas,emev2"
|
||||
- Kyoto Microcomputer Co. KZM-A9-GT
|
||||
compatible = "renesas,kzm9g", "renesas,sh73a0"
|
||||
- Kyoto Microcomputer Co. KZM-A9-GT - Reference Device Tree Implementation
|
||||
compatible = "renesas,kzm9g-reference", "renesas,sh73a0"
|
||||
- Lager (RTP0RC7790SEB00010S)
|
||||
compatible = "renesas,lager", "renesas,r8a7790"
|
||||
- Mackerel (R0P7372LC0016RL, AP4 EVM 2nd)
|
||||
compatible = "renesas,mackerel"
|
||||
- Marzen
|
||||
compatible = "renesas,marzen", "renesas,r8a7779"
|
||||
|
||||
|
|
|
|||
|
|
@ -5,9 +5,12 @@ Required properties:
|
|||
Tegra30, must contain "nvidia,tegra30-ahb". Otherwise, must contain
|
||||
'"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124,
|
||||
tegra132, or tegra210.
|
||||
- reg : Should contain 1 register ranges(address and length)
|
||||
- reg : Should contain 1 register ranges(address and length). For
|
||||
Tegra20, Tegra30, and Tegra114 chips, the value must be <0x6000c004
|
||||
0x10c>. For Tegra124, Tegra132 and Tegra210 chips, the value should
|
||||
be be <0x6000c000 0x150>.
|
||||
|
||||
Example:
|
||||
Example (for a Tegra20 chip):
|
||||
ahb: ahb@6000c004 {
|
||||
compatible = "nvidia,tegra20-ahb";
|
||||
reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,32 @@
|
|||
NVIDIA Tegra Activity Monitor
|
||||
|
||||
The activity monitor block collects statistics about the behaviour of other
|
||||
components in the system. This information can be used to derive the rate at
|
||||
which the external memory needs to be clocked in order to serve all requests
|
||||
from the monitored clients.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "nvidia,tegra<chip>-actmon"
|
||||
- reg: offset and length of the register set for the device
|
||||
- interrupts: standard interrupt property
|
||||
- clocks: Must contain a phandle and clock specifier pair for each entry in
|
||||
clock-names. See ../../clock/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- actmon
|
||||
- emc
|
||||
- resets: Must contain an entry for each entry in reset-names. See
|
||||
../../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- actmon
|
||||
|
||||
Example:
|
||||
actmon@6000c800 {
|
||||
compatible = "nvidia,tegra124-actmon";
|
||||
reg = <0x0 0x6000c800 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
|
||||
<&tegra_car TEGRA124_CLK_EMC>;
|
||||
clock-names = "actmon", "emc";
|
||||
resets = <&tegra_car 119>;
|
||||
reset-names = "actmon";
|
||||
};
|
||||
|
|
@ -3,29 +3,48 @@ STMicroelectronics STi SATA controller
|
|||
This binding describes a SATA device.
|
||||
|
||||
Required properties:
|
||||
- compatible : Must be "st,sti-ahci"
|
||||
- compatible : Must be "st,ahci"
|
||||
- reg : Physical base addresses and length of register sets
|
||||
- interrupts : Interrupt associated with the SATA device
|
||||
- interrupt-names : Associated name must be; "hostc"
|
||||
- resets : The power-down and soft-reset lines of SATA IP
|
||||
- reset-names : Associated names must be; "pwr-dwn" and "sw-rst"
|
||||
- clocks : The phandle for the clock
|
||||
- clock-names : Associated name must be; "ahci_clk"
|
||||
- phys : The phandle for the PHY device
|
||||
- phys : The phandle for the PHY port
|
||||
- phy-names : Associated name must be; "ahci_phy"
|
||||
|
||||
Optional properties:
|
||||
- resets : The power-down, soft-reset and power-reset lines of SATA IP
|
||||
- reset-names : Associated names must be; "pwr-dwn", "sw-rst" and "pwr-rst"
|
||||
|
||||
Example:
|
||||
|
||||
/* Example for stih416 */
|
||||
sata0: sata@fe380000 {
|
||||
compatible = "st,sti-ahci";
|
||||
reg = <0xfe380000 0x1000>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "hostc";
|
||||
phys = <&miphy365x_phy MIPHY_PORT_0 MIPHY_TYPE_SATA>;
|
||||
phy-names = "ahci_phy";
|
||||
resets = <&powerdown STIH416_SATA0_POWERDOWN>,
|
||||
compatible = "st,ahci";
|
||||
reg = <0xfe380000 0x1000>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "hostc";
|
||||
phys = <&phy_port0 PHY_TYPE_SATA>;
|
||||
phy-names = "ahci_phy";
|
||||
resets = <&powerdown STIH416_SATA0_POWERDOWN>,
|
||||
<&softreset STIH416_SATA0_SOFTRESET>;
|
||||
reset-names = "pwr-dwn", "sw-rst";
|
||||
clocks = <&clk_s_a0_ls CLK_ICN_REG>;
|
||||
clock-names = "ahci_clk";
|
||||
reset-names = "pwr-dwn", "sw-rst";
|
||||
clocks = <&clk_s_a0_ls CLK_ICN_REG>;
|
||||
clock-names = "ahci_clk";
|
||||
};
|
||||
|
||||
/* Example for stih407 family silicon */
|
||||
sata0: sata@9b20000 {
|
||||
compatible = "st,ahci";
|
||||
reg = <0x9b20000 0x1000>;
|
||||
interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "hostc";
|
||||
phys = <&phy_port0 PHY_TYPE_SATA>;
|
||||
phy-names = "ahci_phy";
|
||||
resets = <&powerdown STIH407_SATA0_POWERDOWN>,
|
||||
<&softreset STIH407_SATA0_SOFTRESET>,
|
||||
<&softreset STIH407_SATA0_PWR_SOFTRESET>;
|
||||
reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
|
||||
clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
|
||||
clock-names = "ahci_clk";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,7 +1,8 @@
|
|||
* OMAP OCP2SCP - ocp interface to scp interface
|
||||
|
||||
properties:
|
||||
- compatible : Should be "ti,omap-ocp2scp"
|
||||
- compatible : Should be "ti,am437x-ocp2scp" for AM437x processor
|
||||
Should be "ti,omap-ocp2scp" for all others
|
||||
- reg : Address and length of the register set for the device
|
||||
- #address-cells, #size-cells : Must be present if the device has sub-nodes
|
||||
- ranges : the child address space are mapped 1:1 onto the parent address space
|
||||
|
|
|
|||
|
|
@ -0,0 +1,46 @@
|
|||
Renesas Bus State Controller (BSC)
|
||||
==================================
|
||||
|
||||
The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus
|
||||
Bridge", or "External Bus Interface") can be found in several Renesas ARM SoCs.
|
||||
It provides an external bus for connecting multiple external devices to the
|
||||
SoC, driving several chip select lines, for e.g. NOR FLASH, Ethernet and USB.
|
||||
|
||||
While the BSC is a fairly simple memory-mapped bus, it may be part of a PM
|
||||
domain, and may have a gateable functional clock.
|
||||
Before a device connected to the BSC can be accessed, the PM domain
|
||||
containing the BSC must be powered on, and the functional clock
|
||||
driving the BSC must be enabled.
|
||||
|
||||
The bindings for the BSC extend the bindings for "simple-pm-bus".
|
||||
|
||||
|
||||
Required properties
|
||||
- compatible: Must contain an SoC-specific value, and "renesas,bsc" and
|
||||
"simple-pm-bus" as fallbacks.
|
||||
SoC-specific values can be:
|
||||
"renesas,bsc-r8a73a4" for R-Mobile APE6 (r8a73a4)
|
||||
"renesas,bsc-sh73a0" for SH-Mobile AG5 (sh73a0)
|
||||
- #address-cells, #size-cells, ranges: Must describe the mapping between
|
||||
parent address and child address spaces.
|
||||
- reg: Must contain the base address and length to access the bus controller.
|
||||
|
||||
Optional properties:
|
||||
- interrupts: Must contain a reference to the BSC interrupt, if available.
|
||||
- clocks: Must contain a reference to the functional clock, if available.
|
||||
- power-domains: Must contain a reference to the PM domain, if available.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
bsc: bus@fec10000 {
|
||||
compatible = "renesas,bsc-sh73a0", "renesas,bsc",
|
||||
"simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x20000000>;
|
||||
reg = <0xfec10000 0x400>;
|
||||
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&zb_clk>;
|
||||
power-domains = <&pd_a4s>;
|
||||
};
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
Simple Power-Managed Bus
|
||||
========================
|
||||
|
||||
A Simple Power-Managed Bus is a transparent bus that doesn't need a real
|
||||
driver, as it's typically initialized by the boot loader.
|
||||
|
||||
However, its bus controller is part of a PM domain, or under the control of a
|
||||
functional clock. Hence, the bus controller's PM domain and/or clock must be
|
||||
enabled for child devices connected to the bus (either on-SoC or externally)
|
||||
to function.
|
||||
|
||||
While "simple-pm-bus" follows the "simple-bus" set of properties, as specified
|
||||
in ePAPR, it is not an extension of "simple-bus".
|
||||
|
||||
|
||||
Required properties:
|
||||
- compatible: Must contain at least "simple-pm-bus".
|
||||
Must not contain "simple-bus".
|
||||
It's recommended to let this be preceded by one or more
|
||||
vendor-specific compatible values.
|
||||
- #address-cells, #size-cells, ranges: Must describe the mapping between
|
||||
parent address and child address spaces.
|
||||
|
||||
Optional platform-specific properties for clock or PM domain control (at least
|
||||
one of them is required):
|
||||
- clocks: Must contain a reference to the functional clock(s),
|
||||
- power-domains: Must contain a reference to the PM domain.
|
||||
Please refer to the binding documentation for the clock and/or PM domain
|
||||
providers for more details.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
bsc: bus@fec10000 {
|
||||
compatible = "renesas,bsc-sh73a0", "renesas,bsc",
|
||||
"simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x20000000>;
|
||||
reg = <0xfec10000 0x400>;
|
||||
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&zb_clk>;
|
||||
power-domains = <&pd_a4s>;
|
||||
};
|
||||
|
|
@ -9,6 +9,8 @@ Required Properties:
|
|||
- "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC.
|
||||
- "samsung,exynos3250-cmu-dmc" - controller compatible with
|
||||
Exynos3250 SoC for Dynamic Memory Controller domain.
|
||||
- "samsung,exynos3250-cmu-isp" - ISP block clock controller compatible
|
||||
with Exynos3250 SOC
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
|
@ -36,6 +38,12 @@ Example 1: Examples of clock controller nodes are listed below.
|
|||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
cmu_isp: clock-controller@10048000 {
|
||||
compatible = "samsung,exynos3250-cmu-isp";
|
||||
reg = <0x10048000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example 2: UART controller node that consumes the clock generated by the clock
|
||||
controller. Refer to the standard clock bindings for information
|
||||
about 'clocks' and 'clock-names' property.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,462 @@
|
|||
* Samsung Exynos5433 CMU (Clock Management Units)
|
||||
|
||||
The Exynos5433 clock controller generates and supplies clock to various
|
||||
controllers within the Exynos5433 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
|
||||
which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
|
||||
domains and bus clocks.
|
||||
- "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
|
||||
which generates clocks for LLI (Low Latency Interface) IP.
|
||||
- "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
|
||||
which generates clocks for DRAM Memory Controller domain.
|
||||
- "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
|
||||
which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
|
||||
- "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
|
||||
which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
|
||||
- "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
|
||||
which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
|
||||
- "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
|
||||
which generates clocks for G2D/MDMA IPs.
|
||||
- "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
|
||||
which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
|
||||
- "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
|
||||
which generates clocks for Cortex-A5/BUS/AUDIO clocks.
|
||||
- "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
|
||||
and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
|
||||
which generates global data buses clock and global peripheral buses clock.
|
||||
- "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D
|
||||
which generates clocks for 3D Graphics Engine IP.
|
||||
- "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL
|
||||
which generates clocks for GSCALER IPs.
|
||||
- "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO
|
||||
which generates clocks for Cortex-A53 Quad-core processor.
|
||||
- "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS
|
||||
which generates clocks for Cortex-A57 Quad-core processor, CoreSight and
|
||||
L2 cache controller.
|
||||
- "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL
|
||||
which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs.
|
||||
- "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC
|
||||
which generates clocks for MFC(Multi-Format Codec) IP.
|
||||
- "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC
|
||||
which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.
|
||||
- "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP
|
||||
which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
|
||||
- "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0
|
||||
which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1}
|
||||
IPs.
|
||||
- "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
|
||||
which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
- clocks: list of the clock controller input clock identifiers,
|
||||
from common clock bindings. Please refer the next section
|
||||
to find the input clocks for a given controller.
|
||||
|
||||
- clock-names: list of the clock controller input clock names,
|
||||
as described in clock-bindings.txt.
|
||||
|
||||
Input clocks for top clock controller:
|
||||
- oscclk
|
||||
- sclk_mphy_pll
|
||||
- sclk_mfc_pll
|
||||
- sclk_bus_pll
|
||||
|
||||
Input clocks for cpif clock controller:
|
||||
- oscclk
|
||||
|
||||
Input clocks for mif clock controller:
|
||||
- oscclk
|
||||
- sclk_mphy_pll
|
||||
|
||||
Input clocks for fsys clock controller:
|
||||
- oscclk
|
||||
- sclk_ufs_mphy
|
||||
- div_aclk_fsys_200
|
||||
- sclk_pcie_100_fsys
|
||||
- sclk_ufsunipro_fsys
|
||||
- sclk_mmc2_fsys
|
||||
- sclk_mmc1_fsys
|
||||
- sclk_mmc0_fsys
|
||||
- sclk_usbhost30_fsys
|
||||
- sclk_usbdrd30_fsys
|
||||
|
||||
Input clocks for g2d clock controller:
|
||||
- oscclk
|
||||
- aclk_g2d_266
|
||||
- aclk_g2d_400
|
||||
|
||||
Input clocks for disp clock controller:
|
||||
- oscclk
|
||||
- sclk_dsim1_disp
|
||||
- sclk_dsim0_disp
|
||||
- sclk_dsd_disp
|
||||
- sclk_decon_tv_eclk_disp
|
||||
- sclk_decon_vclk_disp
|
||||
- sclk_decon_eclk_disp
|
||||
- sclk_decon_tv_vclk_disp
|
||||
- aclk_disp_333
|
||||
|
||||
Input clocks for bus0 clock controller:
|
||||
- aclk_bus0_400
|
||||
|
||||
Input clocks for bus1 clock controller:
|
||||
- aclk_bus1_400
|
||||
|
||||
Input clocks for bus2 clock controller:
|
||||
- oscclk
|
||||
- aclk_bus2_400
|
||||
|
||||
Input clocks for g3d clock controller:
|
||||
- oscclk
|
||||
- aclk_g3d_400
|
||||
|
||||
Input clocks for gscl clock controller:
|
||||
- oscclk
|
||||
- aclk_gscl_111
|
||||
- aclk_gscl_333
|
||||
|
||||
Input clocks for apollo clock controller:
|
||||
- oscclk
|
||||
- sclk_bus_pll_apollo
|
||||
|
||||
Input clocks for atlas clock controller:
|
||||
- oscclk
|
||||
- sclk_bus_pll_atlas
|
||||
|
||||
Input clocks for mscl clock controller:
|
||||
- oscclk
|
||||
- sclk_jpeg_mscl
|
||||
- aclk_mscl_400
|
||||
|
||||
Input clocks for mfc clock controller:
|
||||
- oscclk
|
||||
- aclk_mfc_400
|
||||
|
||||
Input clocks for hevc clock controller:
|
||||
- oscclk
|
||||
- aclk_hevc_400
|
||||
|
||||
Input clocks for isp clock controller:
|
||||
- oscclk
|
||||
- aclk_isp_dis_400
|
||||
- aclk_isp_400
|
||||
|
||||
Input clocks for cam0 clock controller:
|
||||
- oscclk
|
||||
- aclk_cam0_333
|
||||
- aclk_cam0_400
|
||||
- aclk_cam0_552
|
||||
|
||||
Input clocks for cam1 clock controller:
|
||||
- oscclk
|
||||
- sclk_isp_uart_cam1
|
||||
- sclk_isp_spi1_cam1
|
||||
- sclk_isp_spi0_cam1
|
||||
- aclk_cam1_333
|
||||
- aclk_cam1_400
|
||||
- aclk_cam1_552
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/exynos5433.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
Example 1: Examples of 'oscclk' source clock node are listed below.
|
||||
|
||||
xxti: xxti {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "oscclk";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
Example 2: Examples of clock controller nodes are listed below.
|
||||
|
||||
cmu_top: clock-controller@10030000 {
|
||||
compatible = "samsung,exynos5433-cmu-top";
|
||||
reg = <0x10030000 0x0c04>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk",
|
||||
"sclk_mphy_pll",
|
||||
"sclk_mfc_pll",
|
||||
"sclk_bus_pll";
|
||||
clocks = <&xxti>,
|
||||
<&cmu_cpif CLK_SCLK_MPHY_PLL>,
|
||||
<&cmu_mif CLK_SCLK_MFC_PLL>,
|
||||
<&cmu_mif CLK_SCLK_BUS_PLL>;
|
||||
};
|
||||
|
||||
cmu_cpif: clock-controller@10fc0000 {
|
||||
compatible = "samsung,exynos5433-cmu-cpif";
|
||||
reg = <0x10fc0000 0x0c04>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk";
|
||||
clocks = <&xxti>;
|
||||
};
|
||||
|
||||
cmu_mif: clock-controller@105b0000 {
|
||||
compatible = "samsung,exynos5433-cmu-mif";
|
||||
reg = <0x105b0000 0x100c>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk",
|
||||
"sclk_mphy_pll";
|
||||
clocks = <&xxti>,
|
||||
<&cmu_cpif CLK_SCLK_MPHY_PLL>;
|
||||
};
|
||||
|
||||
cmu_peric: clock-controller@14c80000 {
|
||||
compatible = "samsung,exynos5433-cmu-peric";
|
||||
reg = <0x14c80000 0x0b08>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
cmu_peris: clock-controller@10040000 {
|
||||
compatible = "samsung,exynos5433-cmu-peris";
|
||||
reg = <0x10040000 0x0b20>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
cmu_fsys: clock-controller@156e0000 {
|
||||
compatible = "samsung,exynos5433-cmu-fsys";
|
||||
reg = <0x156e0000 0x0b04>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk",
|
||||
"sclk_ufs_mphy",
|
||||
"div_aclk_fsys_200",
|
||||
"sclk_pcie_100_fsys",
|
||||
"sclk_ufsunipro_fsys",
|
||||
"sclk_mmc2_fsys",
|
||||
"sclk_mmc1_fsys",
|
||||
"sclk_mmc0_fsys",
|
||||
"sclk_usbhost30_fsys",
|
||||
"sclk_usbdrd30_fsys";
|
||||
clocks = <&xxti>,
|
||||
<&cmu_cpif CLK_SCLK_UFS_MPHY>,
|
||||
<&cmu_top CLK_DIV_ACLK_FSYS_200>,
|
||||
<&cmu_top CLK_SCLK_PCIE_100_FSYS>,
|
||||
<&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
|
||||
<&cmu_top CLK_SCLK_MMC2_FSYS>,
|
||||
<&cmu_top CLK_SCLK_MMC1_FSYS>,
|
||||
<&cmu_top CLK_SCLK_MMC0_FSYS>,
|
||||
<&cmu_top CLK_SCLK_USBHOST30_FSYS>,
|
||||
<&cmu_top CLK_SCLK_USBDRD30_FSYS>;
|
||||
};
|
||||
|
||||
cmu_g2d: clock-controller@12460000 {
|
||||
compatible = "samsung,exynos5433-cmu-g2d";
|
||||
reg = <0x12460000 0x0b08>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk",
|
||||
"aclk_g2d_266",
|
||||
"aclk_g2d_400";
|
||||
clocks = <&xxti>,
|
||||
<&cmu_top CLK_ACLK_G2D_266>,
|
||||
<&cmu_top CLK_ACLK_G2D_400>;
|
||||
};
|
||||
|
||||
cmu_disp: clock-controller@13b90000 {
|
||||
compatible = "samsung,exynos5433-cmu-disp";
|
||||
reg = <0x13b90000 0x0c04>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk",
|
||||
"sclk_dsim1_disp",
|
||||
"sclk_dsim0_disp",
|
||||
"sclk_dsd_disp",
|
||||
"sclk_decon_tv_eclk_disp",
|
||||
"sclk_decon_vclk_disp",
|
||||
"sclk_decon_eclk_disp",
|
||||
"sclk_decon_tv_vclk_disp",
|
||||
"aclk_disp_333";
|
||||
clocks = <&xxti>,
|
||||
<&cmu_mif CLK_SCLK_DSIM1_DISP>,
|
||||
<&cmu_mif CLK_SCLK_DSIM0_DISP>,
|
||||
<&cmu_mif CLK_SCLK_DSD_DISP>,
|
||||
<&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
|
||||
<&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
|
||||
<&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
|
||||
<&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
|
||||
<&cmu_mif CLK_ACLK_DISP_333>;
|
||||
};
|
||||
|
||||
cmu_aud: clock-controller@114c0000 {
|
||||
compatible = "samsung,exynos5433-cmu-aud";
|
||||
reg = <0x114c0000 0x0b04>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
cmu_bus0: clock-controller@13600000 {
|
||||
compatible = "samsung,exynos5433-cmu-bus0";
|
||||
reg = <0x13600000 0x0b04>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "aclk_bus0_400";
|
||||
clocks = <&cmu_top CLK_ACLK_BUS0_400>;
|
||||
};
|
||||
|
||||
cmu_bus1: clock-controller@14800000 {
|
||||
compatible = "samsung,exynos5433-cmu-bus1";
|
||||
reg = <0x14800000 0x0b04>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "aclk_bus1_400";
|
||||
clocks = <&cmu_top CLK_ACLK_BUS1_400>;
|
||||
};
|
||||
|
||||
cmu_bus2: clock-controller@13400000 {
|
||||
compatible = "samsung,exynos5433-cmu-bus2";
|
||||
reg = <0x13400000 0x0b04>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk", "aclk_bus2_400";
|
||||
clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
|
||||
};
|
||||
|
||||
cmu_g3d: clock-controller@14aa0000 {
|
||||
compatible = "samsung,exynos5433-cmu-g3d";
|
||||
reg = <0x14aa0000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk", "aclk_g3d_400";
|
||||
clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
|
||||
};
|
||||
|
||||
cmu_gscl: clock-controller@13cf0000 {
|
||||
compatible = "samsung,exynos5433-cmu-gscl";
|
||||
reg = <0x13cf0000 0x0b10>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk",
|
||||
"aclk_gscl_111",
|
||||
"aclk_gscl_333";
|
||||
clocks = <&xxti>,
|
||||
<&cmu_top CLK_ACLK_GSCL_111>,
|
||||
<&cmu_top CLK_ACLK_GSCL_333>;
|
||||
};
|
||||
|
||||
cmu_apollo: clock-controller@11900000 {
|
||||
compatible = "samsung,exynos5433-cmu-apollo";
|
||||
reg = <0x11900000 0x1088>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk", "sclk_bus_pll_apollo";
|
||||
clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
|
||||
};
|
||||
|
||||
cmu_atlas: clock-controller@11800000 {
|
||||
compatible = "samsung,exynos5433-cmu-atlas";
|
||||
reg = <0x11800000 0x1088>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk", "sclk_bus_pll_atlas";
|
||||
clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
|
||||
};
|
||||
|
||||
cmu_mscl: clock-controller@105d0000 {
|
||||
compatible = "samsung,exynos5433-cmu-mscl";
|
||||
reg = <0x105d0000 0x0b10>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk",
|
||||
"sclk_jpeg_mscl",
|
||||
"aclk_mscl_400";
|
||||
clocks = <&xxti>,
|
||||
<&cmu_top CLK_SCLK_JPEG_MSCL>,
|
||||
<&cmu_top CLK_ACLK_MSCL_400>;
|
||||
};
|
||||
|
||||
cmu_mfc: clock-controller@15280000 {
|
||||
compatible = "samsung,exynos5433-cmu-mfc";
|
||||
reg = <0x15280000 0x0b08>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk", "aclk_mfc_400";
|
||||
clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
|
||||
};
|
||||
|
||||
cmu_hevc: clock-controller@14f80000 {
|
||||
compatible = "samsung,exynos5433-cmu-hevc";
|
||||
reg = <0x14f80000 0x0b08>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk", "aclk_hevc_400";
|
||||
clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
|
||||
};
|
||||
|
||||
cmu_isp: clock-controller@146d0000 {
|
||||
compatible = "samsung,exynos5433-cmu-isp";
|
||||
reg = <0x146d0000 0x0b0c>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk",
|
||||
"aclk_isp_dis_400",
|
||||
"aclk_isp_400";
|
||||
clocks = <&xxti>,
|
||||
<&cmu_top CLK_ACLK_ISP_DIS_400>,
|
||||
<&cmu_top CLK_ACLK_ISP_400>;
|
||||
};
|
||||
|
||||
cmu_cam0: clock-controller@120d0000 {
|
||||
compatible = "samsung,exynos5433-cmu-cam0";
|
||||
reg = <0x120d0000 0x0b0c>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk",
|
||||
"aclk_cam0_333",
|
||||
"aclk_cam0_400",
|
||||
"aclk_cam0_552";
|
||||
clocks = <&xxti>,
|
||||
<&cmu_top CLK_ACLK_CAM0_333>,
|
||||
<&cmu_top CLK_ACLK_CAM0_400>,
|
||||
<&cmu_top CLK_ACLK_CAM0_552>;
|
||||
};
|
||||
|
||||
cmu_cam1: clock-controller@145d0000 {
|
||||
compatible = "samsung,exynos5433-cmu-cam1";
|
||||
reg = <0x145d0000 0x0b08>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk",
|
||||
"sclk_isp_uart_cam1",
|
||||
"sclk_isp_spi1_cam1",
|
||||
"sclk_isp_spi0_cam1",
|
||||
"aclk_cam1_333",
|
||||
"aclk_cam1_400",
|
||||
"aclk_cam1_552";
|
||||
clocks = <&xxti>,
|
||||
<&cmu_top CLK_SCLK_ISP_UART_CAM1>,
|
||||
<&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
|
||||
<&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
|
||||
<&cmu_top CLK_ACLK_CAM1_333>,
|
||||
<&cmu_top CLK_ACLK_CAM1_400>,
|
||||
<&cmu_top CLK_ACLK_CAM1_552>;
|
||||
};
|
||||
|
||||
Example 3: UART controller node that consumes the clock generated by the clock
|
||||
controller.
|
||||
|
||||
serial_0: serial@14C10000 {
|
||||
compatible = "samsung,exynos5433-uart";
|
||||
reg = <0x14C10000 0x100>;
|
||||
interrupts = <0 421 0>;
|
||||
clocks = <&cmu_peric CLK_PCLK_UART0>,
|
||||
<&cmu_peric CLK_SCLK_UART0>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_bus>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
Fujitsu CRG11 clock driver bindings
|
||||
-----------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible : Shall contain "fujitsu,mb86s70-crg11"
|
||||
- #clock-cells : Shall be 3 {cntrlr domain port}
|
||||
|
||||
The consumer specifies the desired clock pointing to its phandle.
|
||||
|
||||
Example:
|
||||
|
||||
clock: crg11 {
|
||||
compatible = "fujitsu,mb86s70-crg11";
|
||||
#clock-cells = <3>;
|
||||
};
|
||||
|
||||
mhu: mhu0@2b1f0000 {
|
||||
#mbox-cells = <1>;
|
||||
compatible = "arm,mhu";
|
||||
reg = <0 0x2B1F0000 0x1000>;
|
||||
interrupts = <0 36 4>, /* LP Non-Sec */
|
||||
<0 35 4>, /* HP Non-Sec */
|
||||
<0 37 4>; /* Secure */
|
||||
clocks = <&clock 0 2 1>; /* Cntrlr:0 Domain:2 Port:1 */
|
||||
clock-names = "clk";
|
||||
};
|
||||
|
|
@ -23,6 +23,14 @@ The following is a list of provided IDs and clock names on Armada 380/385:
|
|||
2 = l2clk (L2 Cache clock)
|
||||
3 = ddrclk (DDR clock)
|
||||
|
||||
The following is a list of provided IDs and clock names on Armada 39x:
|
||||
0 = tclk (Internal Bus clock)
|
||||
1 = cpuclk (CPU clock)
|
||||
2 = nbclk (Coherent Fabric clock)
|
||||
3 = hclk (SDRAM Controller Internal Clock)
|
||||
4 = dclk (SDRAM Interface Clock)
|
||||
5 = refclk (Reference Clock)
|
||||
|
||||
The following is a list of provided IDs and clock names on Kirkwood and Dove:
|
||||
0 = tclk (Internal Bus clock)
|
||||
1 = cpuclk (CPU0 clock)
|
||||
|
|
@ -39,6 +47,7 @@ Required properties:
|
|||
"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
|
||||
"marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
|
||||
"marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
|
||||
"marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
|
||||
"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
|
||||
"marvell,dove-core-clock" - for Dove SoC core clocks
|
||||
"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
* Gated Clock bindings for Marvell EBU SoCs
|
||||
|
||||
Marvell Armada 370/375/380/385/XP, Dove and Kirkwood allow some
|
||||
Marvell Armada 370/375/380/385/39x/XP, Dove and Kirkwood allow some
|
||||
peripheral clocks to be gated to save some power. The clock consumer
|
||||
should specify the desired clock by having the clock ID in its
|
||||
"clocks" phandle cell. The clock ID is directly mapped to the
|
||||
|
|
@ -77,6 +77,18 @@ ID Clock Peripheral
|
|||
28 xor1 XOR 1
|
||||
30 sata1 SATA 1
|
||||
|
||||
The following is a list of provided IDs for Armada 39x:
|
||||
ID Clock Peripheral
|
||||
-----------------------------------
|
||||
5 pex1 PCIe 1
|
||||
6 pex2 PCIe 2
|
||||
7 pex3 PCIe 3
|
||||
8 pex0 PCIe 0
|
||||
9 usb3h0 USB3 Host 0
|
||||
17 sdio SDIO
|
||||
22 xor0 XOR 0
|
||||
28 xor1 XOR 1
|
||||
|
||||
The following is a list of provided IDs for Armada XP:
|
||||
ID Clock Peripheral
|
||||
-----------------------------------
|
||||
|
|
@ -152,6 +164,7 @@ Required properties:
|
|||
"marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
|
||||
"marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
|
||||
"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
|
||||
"marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
|
||||
"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
|
||||
"marvell,dove-gating-clock" - for Dove SoC clock gating
|
||||
"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
|
||||
|
|
|
|||
|
|
@ -0,0 +1,123 @@
|
|||
Imagination Technologies Pistachio SoC clock controllers
|
||||
========================================================
|
||||
|
||||
Pistachio has four clock controllers (core clock, peripheral clock, peripheral
|
||||
general control, and top general control) which are instantiated individually
|
||||
from the device-tree.
|
||||
|
||||
External clocks:
|
||||
----------------
|
||||
|
||||
There are three external inputs to the clock controllers which should be
|
||||
defined with the following clock-output-names:
|
||||
- "xtal": External 52Mhz oscillator (required)
|
||||
- "audio_clk_in": Alternate audio reference clock (optional)
|
||||
- "enet_clk_in": Alternate ethernet PHY clock (optional)
|
||||
|
||||
Core clock controller:
|
||||
----------------------
|
||||
|
||||
The core clock controller generates clocks for the CPU, RPU (WiFi + BT
|
||||
co-processor), audio, and several peripherals.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "img,pistachio-clk".
|
||||
- reg: Must contain the base address and length of the core clock controller.
|
||||
- #clock-cells: Must be 1. The single cell is the clock identifier.
|
||||
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
|
||||
- clocks: Must contain an entry for each clock in clock-names.
|
||||
- clock-names: Must include "xtal" (see "External clocks") and
|
||||
"audio_clk_in_gate", "enet_clk_in_gate" which are generated by the
|
||||
top-level general control.
|
||||
|
||||
Example:
|
||||
clk_core: clock-controller@18144000 {
|
||||
compatible = "img,pistachio-clk";
|
||||
reg = <0x18144000 0x800>;
|
||||
clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
|
||||
<&cr_top EXT_CLK_ENET_IN>;
|
||||
clock-names = "xtal", "audio_clk_in_gate", "enet_clk_in_gate";
|
||||
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Peripheral clock controller:
|
||||
----------------------------
|
||||
|
||||
The peripheral clock controller generates clocks for the DDR, ROM, and other
|
||||
peripherals. The peripheral system clock ("periph_sys") generated by the core
|
||||
clock controller is the input clock to the peripheral clock controller.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "img,pistachio-periph-clk".
|
||||
- reg: Must contain the base address and length of the peripheral clock
|
||||
controller.
|
||||
- #clock-cells: Must be 1. The single cell is the clock identifier.
|
||||
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
|
||||
- clocks: Must contain an entry for each clock in clock-names.
|
||||
- clock-names: Must include "periph_sys", the peripheral system clock generated
|
||||
by the core clock controller.
|
||||
|
||||
Example:
|
||||
clk_periph: clock-controller@18144800 {
|
||||
compatible = "img,pistachio-clk-periph";
|
||||
reg = <0x18144800 0x800>;
|
||||
clocks = <&clk_core CLK_PERIPH_SYS>;
|
||||
clock-names = "periph_sys";
|
||||
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Peripheral general control:
|
||||
---------------------------
|
||||
|
||||
The peripheral general control block generates system interface clocks and
|
||||
resets for various peripherals. It also contains miscellaneous peripheral
|
||||
control registers. The system clock ("sys") generated by the peripheral clock
|
||||
controller is the input clock to the system clock controller.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must include "img,pistachio-periph-cr" and "syscon".
|
||||
- reg: Must contain the base address and length of the peripheral general
|
||||
control registers.
|
||||
- #clock-cells: Must be 1. The single cell is the clock identifier.
|
||||
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
|
||||
- clocks: Must contain an entry for each clock in clock-names.
|
||||
- clock-names: Must include "sys", the system clock generated by the peripheral
|
||||
clock controller.
|
||||
|
||||
Example:
|
||||
cr_periph: syscon@18144800 {
|
||||
compatible = "img,pistachio-cr-periph", "syscon";
|
||||
reg = <0x18148000 0x1000>;
|
||||
clocks = <&clock_periph PERIPH_CLK_PERIPH_SYS>;
|
||||
clock-names = "sys";
|
||||
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Top-level general control:
|
||||
--------------------------
|
||||
|
||||
The top-level general control block contains miscellaneous control registers and
|
||||
gates for the external clocks "audio_clk_in" and "enet_clk_in".
|
||||
|
||||
Required properties:
|
||||
- compatible: Must include "img,pistachio-cr-top" and "syscon".
|
||||
- reg: Must contain the base address and length of the top-level
|
||||
control registers.
|
||||
- clocks: Must contain an entry for each clock in clock-names.
|
||||
- clock-names: Two optional clocks, "audio_clk_in" and "enet_clk_in" (see
|
||||
"External clocks").
|
||||
- #clock-cells: Must be 1. The single cell is the clock identifier.
|
||||
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
|
||||
|
||||
Example:
|
||||
cr_top: syscon@18144800 {
|
||||
compatible = "img,pistachio-cr-top", "syscon";
|
||||
reg = <0x18149000 0x200>;
|
||||
clocks = <&audio_refclk>, <&ext_enet_in>;
|
||||
clock-names = "audio_clk_in", "enet_clk_in";
|
||||
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
Binding for an external clock signal driven by a PWM pin.
|
||||
|
||||
This binding uses the common clock binding[1] and the common PWM binding[2].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/pwm/pwm.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "pwm-clock".
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- pwms : from common PWM binding; this determines the clock frequency
|
||||
via the period given in the PWM specifier.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : From common clock binding.
|
||||
- clock-frequency : Exact output frequency, in case the PWM period
|
||||
is not exact but was rounded to nanoseconds.
|
||||
|
||||
Example:
|
||||
clock {
|
||||
compatible = "pwm-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "mipi_mclk";
|
||||
pwms = <&pwm2 0 40>; /* 1 / 40 ns = 25 MHz */
|
||||
};
|
||||
|
|
@ -8,6 +8,7 @@ Required properties :
|
|||
"qcom,gcc-apq8084"
|
||||
"qcom,gcc-ipq8064"
|
||||
"qcom,gcc-msm8660"
|
||||
"qcom,gcc-msm8916"
|
||||
"qcom,gcc-msm8960"
|
||||
"qcom,gcc-msm8974"
|
||||
"qcom,gcc-msm8974pro"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,25 @@
|
|||
* Renesas R8A7778 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the R8A7778. It includes two PLLs and
|
||||
several fixed ratio dividers
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be "renesas,r8a7778-cpg-clocks"
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The names of the clocks. Supported clocks are
|
||||
"plla", "pllb", "b", "out", "p", "s", and "s1".
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
cpg_clocks: cpg_clocks@ffc80000 {
|
||||
compatible = "renesas,r8a7778-cpg-clocks";
|
||||
reg = <0xffc80000 0x80>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&extal_clk>;
|
||||
clock-output-names = "plla", "pllb", "b",
|
||||
"out", "p", "s", "s1";
|
||||
};
|
||||
|
|
@ -20,6 +20,7 @@ Required properties:
|
|||
"allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
|
||||
"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
|
||||
"allwinner,sun4i-a10-ahb-clk" - for the AHB clock
|
||||
"allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13
|
||||
"allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
|
||||
"allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
|
||||
"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
|
||||
|
|
@ -66,6 +67,8 @@ Required properties:
|
|||
"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
|
||||
"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
|
||||
"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
|
||||
"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
|
||||
"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
|
||||
|
||||
Required properties for all clocks:
|
||||
- reg : shall be the control register address for the clock.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,60 @@
|
|||
Common properties
|
||||
|
||||
The ePAPR specification does not define any properties related to hardware
|
||||
byteswapping, but endianness issues show up frequently in porting Linux to
|
||||
different machine types. This document attempts to provide a consistent
|
||||
way of handling byteswapping across drivers.
|
||||
|
||||
Optional properties:
|
||||
- big-endian: Boolean; force big endian register accesses
|
||||
unconditionally (e.g. ioread32be/iowrite32be). Use this if you
|
||||
know the peripheral always needs to be accessed in BE mode.
|
||||
- little-endian: Boolean; force little endian register accesses
|
||||
unconditionally (e.g. readl/writel). Use this if you know the
|
||||
peripheral always needs to be accessed in LE mode.
|
||||
- native-endian: Boolean; always use register accesses matched to the
|
||||
endianness of the kernel binary (e.g. LE vmlinux -> readl/writel,
|
||||
BE vmlinux -> ioread32be/iowrite32be). In this case no byteswaps
|
||||
will ever be performed. Use this if the hardware "self-adjusts"
|
||||
register endianness based on the CPU's configured endianness.
|
||||
|
||||
If a binding supports these properties, then the binding should also
|
||||
specify the default behavior if none of these properties are present.
|
||||
In such cases, little-endian is the preferred default, but it is not
|
||||
a requirement. The of_device_is_big_endian() and of_fdt_is_big_endian()
|
||||
helper functions do assume that little-endian is the default, because
|
||||
most existing (PCI-based) drivers implicitly default to LE by using
|
||||
readl/writel for MMIO accesses.
|
||||
|
||||
Examples:
|
||||
Scenario 1 : CPU in LE mode & device in LE mode.
|
||||
dev: dev@40031000 {
|
||||
compatible = "name";
|
||||
reg = <0x40031000 0x1000>;
|
||||
...
|
||||
native-endian;
|
||||
};
|
||||
|
||||
Scenario 2 : CPU in LE mode & device in BE mode.
|
||||
dev: dev@40031000 {
|
||||
compatible = "name";
|
||||
reg = <0x40031000 0x1000>;
|
||||
...
|
||||
big-endian;
|
||||
};
|
||||
|
||||
Scenario 3 : CPU in BE mode & device in BE mode.
|
||||
dev: dev@40031000 {
|
||||
compatible = "name";
|
||||
reg = <0x40031000 0x1000>;
|
||||
...
|
||||
native-endian;
|
||||
};
|
||||
|
||||
Scenario 4 : CPU in BE mode & device in LE mode.
|
||||
dev: dev@40031000 {
|
||||
compatible = "name";
|
||||
reg = <0x40031000 0x1000>;
|
||||
...
|
||||
little-endian;
|
||||
};
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
Axis Communications AB
|
||||
ARTPEC series SoC Device Tree Bindings
|
||||
|
||||
|
||||
CRISv32 based SoCs are ETRAX FS and ARTPEC-3:
|
||||
|
||||
- compatible = "axis,crisv32";
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
Boards based on the CRIS SoCs:
|
||||
|
||||
Required root node properties:
|
||||
- compatible = should be one or more of the following:
|
||||
- "axis,dev88" - for Axis devboard 88 with ETRAX FS
|
||||
|
||||
Optional:
|
||||
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
* CRISv32 Interrupt Controller
|
||||
|
||||
Interrupt controller for the CRISv32 SoCs.
|
||||
|
||||
Main node required properties:
|
||||
|
||||
- compatible : should be:
|
||||
"axis,crisv32-intc"
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. The type shall be a <u32> and the value shall be 1.
|
||||
- reg: physical base address and size of the intc registers map.
|
||||
|
||||
Example:
|
||||
|
||||
intc: interrupt-controller {
|
||||
compatible = "axis,crisv32-intc";
|
||||
reg = <0xb001c000 0x1000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
Imagination Technologies hardware hash accelerator
|
||||
|
||||
The hash accelerator provides hardware hashing acceleration for
|
||||
SHA1, SHA224, SHA256 and MD5 hashes
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : "img,hash-accelerator"
|
||||
- reg : Offset and length of the register set for the module, and the DMA port
|
||||
- interrupts : The designated IRQ line for the hashing module.
|
||||
- dmas : DMA specifier as per Documentation/devicetree/bindings/dma/dma.txt
|
||||
- dma-names : Should be "tx"
|
||||
- clocks : Clock specifiers
|
||||
- clock-names : "sys" Used to clock the hash block registers
|
||||
"hash" Used to clock data through the accelerator
|
||||
|
||||
Example:
|
||||
|
||||
hash: hash@18149600 {
|
||||
compatible = "img,hash-accelerator";
|
||||
reg = <0x18149600 0x100>, <0x18101100 0x4>;
|
||||
interrupts = <GIC_SHARED 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&dma 8 0xffffffff 0>;
|
||||
dma-names = "tx";
|
||||
clocks = <&cr_periph SYS_CLK_HASH>, <&clk_periph PERIPH_CLK_ROM>;
|
||||
clock-names = "sys", "hash";
|
||||
};
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
Applied Micro X-Gene SoC DMA nodes
|
||||
|
||||
DMA nodes are defined to describe on-chip DMA interfaces in
|
||||
APM X-Gene SoC.
|
||||
|
||||
Required properties for DMA interfaces:
|
||||
- compatible: Should be "apm,xgene-dma".
|
||||
- device_type: set to "dma".
|
||||
- reg: Address and length of the register set for the device.
|
||||
It contains the information of registers in the following order:
|
||||
1st - DMA control and status register address space.
|
||||
2nd - Descriptor ring control and status register address space.
|
||||
3rd - Descriptor ring command register address space.
|
||||
4th - Soc efuse register address space.
|
||||
- interrupts: DMA has 5 interrupts sources. 1st interrupt is
|
||||
DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts
|
||||
are completion interrupts for each DMA channels.
|
||||
- clocks: Reference to the clock entry.
|
||||
|
||||
Optional properties:
|
||||
- dma-coherent : Present if dma operations are coherent
|
||||
|
||||
Example:
|
||||
dmaclk: dmaclk@1f27c000 {
|
||||
compatible = "apm,xgene-device-clock";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&socplldiv2 0>;
|
||||
reg = <0x0 0x1f27c000 0x0 0x1000>;
|
||||
reg-names = "csr-reg";
|
||||
clock-output-names = "dmaclk";
|
||||
};
|
||||
|
||||
dma: dma@1f270000 {
|
||||
compatible = "apm,xgene-storm-dma";
|
||||
device_type = "dma";
|
||||
reg = <0x0 0x1f270000 0x0 0x10000>,
|
||||
<0x0 0x1f200000 0x0 0x10000>,
|
||||
<0x0 0x1b008000 0x0 0x2000>,
|
||||
<0x0 0x1054a000 0x0 0x100>;
|
||||
interrupts = <0x0 0x82 0x4>,
|
||||
<0x0 0xb8 0x4>,
|
||||
<0x0 0xb9 0x4>,
|
||||
<0x0 0xba 0x4>,
|
||||
<0x0 0xbb 0x4>;
|
||||
dma-coherent;
|
||||
clocks = <&dmaclk 0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
* Ingenic JZ4780 DMA Controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be "ingenic,jz4780-dma"
|
||||
- reg: Should contain the DMA controller registers location and length.
|
||||
- interrupts: Should contain the interrupt specifier of the DMA controller.
|
||||
- interrupt-parent: Should be the phandle of the interrupt controller that
|
||||
- clocks: Should contain a clock specifier for the JZ4780 PDMA clock.
|
||||
- #dma-cells: Must be <2>. Number of integer cells in the dmas property of
|
||||
DMA clients (see below).
|
||||
|
||||
Optional properties:
|
||||
|
||||
- ingenic,reserved-channels: Bitmask of channels to reserve for devices that
|
||||
need a specific channel. These channels will only be assigned when explicitly
|
||||
requested by a client. The primary use for this is channels 0 and 1, which
|
||||
can be configured to have special behaviour for NAND/BCH when using
|
||||
programmable firmware.
|
||||
|
||||
Example:
|
||||
|
||||
dma: dma@13420000 {
|
||||
compatible = "ingenic,jz4780-dma";
|
||||
reg = <0x13420000 0x10000>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <10>;
|
||||
|
||||
clocks = <&cgu JZ4780_CLK_PDMA>;
|
||||
|
||||
#dma-cells = <2>;
|
||||
|
||||
ingenic,reserved-channels = <0x3>;
|
||||
};
|
||||
|
||||
DMA clients must use the format described in dma.txt, giving a phandle to the
|
||||
DMA controller plus the following 2 integer cells:
|
||||
|
||||
1. Request type: The DMA request type for transfers to/from the device on
|
||||
the allocated channel, as defined in the SoC documentation.
|
||||
|
||||
2. Channel: If set to 0xffffffff, any available channel will be allocated for
|
||||
the client. Otherwise, the exact channel specified will be used. The channel
|
||||
should be reserved on the DMA controller using the ingenic,reserved-channels
|
||||
property.
|
||||
|
||||
Example:
|
||||
|
||||
uart0: serial@10030000 {
|
||||
...
|
||||
dmas = <&dma 0x14 0xffffffff
|
||||
&dma 0x15 0xffffffff>;
|
||||
dma-names = "tx", "rx";
|
||||
...
|
||||
};
|
||||
|
|
@ -4,6 +4,7 @@ Required properties:
|
|||
- compatible: must be one of the following:
|
||||
* "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084
|
||||
* "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960
|
||||
* "qcom,bam-v1.7.0" for MSM8916
|
||||
- reg: Address range for DMA registers
|
||||
- interrupts: Should contain the one interrupt shared by all channels
|
||||
- #dma-cells: must be <1>, the cell in the dmas property of the client device
|
||||
|
|
|
|||
|
|
@ -1,29 +0,0 @@
|
|||
* R-Car Audio DMAC peri peri Device Tree bindings
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "renesas,rcar-audmapp"
|
||||
- #dma-cells: should be <1>, see "dmas" property below
|
||||
|
||||
Example:
|
||||
audmapp: audio-dma-pp@0xec740000 {
|
||||
compatible = "renesas,rcar-audmapp";
|
||||
#dma-cells = <1>;
|
||||
|
||||
reg = <0 0xec740000 0 0x200>;
|
||||
};
|
||||
|
||||
|
||||
* DMA client
|
||||
|
||||
Required properties:
|
||||
- dmas: a list of <[DMA multiplexer phandle] [SRS << 8 | DRS]> pairs.
|
||||
where SRS/DRS are specified in the SoC manual.
|
||||
It will be written into PDMACHCR as high 16-bit parts.
|
||||
- dma-names: a list of DMA channel names, one per "dmas" entry
|
||||
|
||||
Example:
|
||||
|
||||
dmas = <&audmapp 0x2d00
|
||||
&audmapp 0x3700>;
|
||||
dma-names = "src0_ssiu0",
|
||||
"dvc0_ssiu0";
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
* Renesas USB DMA Controller Device Tree bindings
|
||||
|
||||
Required Properties:
|
||||
- compatible: must contain "renesas,usb-dmac"
|
||||
- reg: base address and length of the registers block for the DMAC
|
||||
- interrupts: interrupt specifiers for the DMAC, one for each entry in
|
||||
interrupt-names.
|
||||
- interrupt-names: one entry per channel, named "ch%u", where %u is the
|
||||
channel number ranging from zero to the number of channels minus one.
|
||||
- clocks: a list of phandle + clock-specifier pairs.
|
||||
- #dma-cells: must be <1>, the cell specifies the channel number of the DMAC
|
||||
port connected to the DMA client.
|
||||
- dma-channels: number of DMA channels
|
||||
|
||||
Example: R8A7790 (R-Car H2) USB-DMACs
|
||||
|
||||
usb_dmac0: dma-controller@e65a0000 {
|
||||
compatible = "renesas,usb-dmac";
|
||||
reg = <0 0xe65a0000 0 0x100>;
|
||||
interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH
|
||||
0 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
|
||||
usb_dmac1: dma-controller@e65b0000 {
|
||||
compatible = "renesas,usb-dmac";
|
||||
reg = <0 0xe65b0000 0 0x100>;
|
||||
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH
|
||||
0 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
|
|
@ -44,23 +44,30 @@ Optional properties:
|
|||
LVDS Channel
|
||||
============
|
||||
|
||||
Each LVDS Channel has to contain a display-timings node that describes the
|
||||
video timings for the connected LVDS display. For detailed information, also
|
||||
have a look at Documentation/devicetree/bindings/video/display-timing.txt.
|
||||
Each LVDS Channel has to contain either an of graph link to a panel device node
|
||||
or a display-timings node that describes the video timings for the connected
|
||||
LVDS display as well as the fsl,data-mapping and fsl,data-width properties.
|
||||
|
||||
Required properties:
|
||||
- reg : should be <0> or <1>
|
||||
- port: Input and output port nodes with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/graph.txt.
|
||||
On i.MX5, the internal two-input-multiplexer is used. Due to hardware
|
||||
limitations, only one input port (port@[0,1]) can be used for each channel
|
||||
(lvds-channel@[0,1], respectively).
|
||||
On i.MX6, there should be four input ports (port@[0-3]) that correspond
|
||||
to the four LVDS multiplexer inputs.
|
||||
A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected
|
||||
to a panel input port. Optionally, the output port can be left out if
|
||||
display-timings are used instead.
|
||||
|
||||
Optional properties (required if display-timings are used):
|
||||
- display-timings : A node that describes the display timings as defined in
|
||||
Documentation/devicetree/bindings/video/display-timing.txt.
|
||||
- fsl,data-mapping : should be "spwg" or "jeida"
|
||||
This describes how the color bits are laid out in the
|
||||
serialized LVDS signal.
|
||||
- fsl,data-width : should be <18> or <24>
|
||||
- port: A port node with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt.
|
||||
On i.MX5, the internal two-input-multiplexer is used.
|
||||
Due to hardware limitations, only one port (port@[0,1])
|
||||
can be used for each channel (lvds-channel@[0,1], respectively)
|
||||
On i.MX6, there should be four ports (port@[0-3]) that correspond
|
||||
to the four LVDS multiplexer inputs.
|
||||
|
||||
example:
|
||||
|
||||
|
|
@ -73,23 +80,21 @@ ldb: ldb@53fa8008 {
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-ldb";
|
||||
gpr = <&gpr>;
|
||||
clocks = <&clks 122>, <&clks 120>,
|
||||
<&clks 115>, <&clks 116>,
|
||||
<&clks 123>, <&clks 85>;
|
||||
clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
|
||||
<&clks IMX5_CLK_LDB_DI1_SEL>,
|
||||
<&clks IMX5_CLK_IPU_DI0_SEL>,
|
||||
<&clks IMX5_CLK_IPU_DI1_SEL>,
|
||||
<&clks IMX5_CLK_LDB_DI0_GATE>,
|
||||
<&clks IMX5_CLK_LDB_DI1_GATE>;
|
||||
clock-names = "di0_pll", "di1_pll",
|
||||
"di0_sel", "di1_sel",
|
||||
"di0", "di1";
|
||||
|
||||
/* Using an of-graph endpoint link to connect the panel */
|
||||
lvds-channel@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <24>;
|
||||
|
||||
display-timings {
|
||||
/* ... */
|
||||
};
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
|
@ -98,8 +103,17 @@ ldb: ldb@53fa8008 {
|
|||
remote-endpoint = <&ipu_di0_lvds0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Using display-timings and fsl,data-mapping/width instead */
|
||||
lvds-channel@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -120,3 +134,13 @@ ldb: ldb@53fa8008 {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel: lvds-panel {
|
||||
/* ... */
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,18 @@
|
|||
USB GPIO Extcon device
|
||||
|
||||
This is a virtual device used to generate USB cable states from the USB ID pin
|
||||
connected to a GPIO pin.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "linux,extcon-usb-gpio"
|
||||
- id-gpio: gpio for USB ID pin. See gpio binding.
|
||||
|
||||
Example: Examples of extcon-usb-gpio node in dra7-evm.dts as listed below:
|
||||
extcon_usb1 {
|
||||
compatible = "linux,extcon-usb-gpio";
|
||||
id-gpio = <&gpio6 1 GPIO_ACTIVE_HIGH>;
|
||||
}
|
||||
|
||||
&omap_dwc3_1 {
|
||||
extcon = <&extcon_usb1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
Altera GPIO controller bindings
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
- "altr,pio-1.0"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- #gpio-cells : Should be 2
|
||||
- The first cell is the gpio offset number.
|
||||
- The second cell is reserved and is currently unused.
|
||||
- gpio-controller : Marks the device node as a GPIO controller.
|
||||
- interrupt-controller: Mark the device node as an interrupt controller
|
||||
- #interrupt-cells : Should be 1. The interrupt type is fixed in the hardware.
|
||||
- The first cell is the GPIO offset number within the GPIO controller.
|
||||
- interrupts: Specify the interrupt.
|
||||
- altr,interrupt-trigger: Specifies the interrupt trigger type the GPIO
|
||||
hardware is synthesized. This field is required if the Altera GPIO controller
|
||||
used has IRQ enabled as the interrupt type is not software controlled,
|
||||
but hardware synthesized. Required if GPIO is used as an interrupt
|
||||
controller. The value is defined in <dt-bindings/interrupt-controller/irq.h>
|
||||
Only the following flags are supported:
|
||||
IRQ_TYPE_EDGE_RISING
|
||||
IRQ_TYPE_EDGE_FALLING
|
||||
IRQ_TYPE_EDGE_BOTH
|
||||
IRQ_TYPE_LEVEL_HIGH
|
||||
|
||||
Optional properties:
|
||||
- altr,ngpio: Width of the GPIO bank. This defines how many pins the
|
||||
GPIO device has. Ranges between 1-32. Optional and defaults to 32 if not
|
||||
specified.
|
||||
|
||||
Example:
|
||||
|
||||
gpio_altr: gpio@0xff200000 {
|
||||
compatible = "altr,pio-1.0";
|
||||
reg = <0xff200000 0x10>;
|
||||
interrupts = <0 45 4>;
|
||||
altr,ngpio = <32>;
|
||||
altr,interrupt-trigger = <IRQ_TYPE_EDGE_RISING>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
|
@ -2,15 +2,20 @@ Bindings for fan connected to GPIO lines
|
|||
|
||||
Required properties:
|
||||
- compatible : "gpio-fan"
|
||||
|
||||
Optional properties:
|
||||
- gpios: Specifies the pins that map to bits in the control value,
|
||||
ordered MSB-->LSB.
|
||||
- gpio-fan,speed-map: A mapping of possible fan RPM speeds and the
|
||||
control value that should be set to achieve them. This array
|
||||
must have the RPM values in ascending order.
|
||||
|
||||
Optional properties:
|
||||
- alarm-gpios: This pin going active indicates something is wrong with
|
||||
the fan, and a udev event will be fired.
|
||||
- cooling-cells: If used as a cooling device, must be <2>
|
||||
Also see: Documentation/devicetree/bindings/thermal/thermal.txt
|
||||
min and max states are derived from the speed-map of the fan.
|
||||
|
||||
Note: At least one the "gpios" or "alarm-gpios" properties must be set.
|
||||
|
||||
Examples:
|
||||
|
||||
|
|
@ -23,3 +28,13 @@ Examples:
|
|||
6000 2>;
|
||||
alarm-gpios = <&gpio1 15 1>;
|
||||
};
|
||||
gpio_fan_cool: gpio_fan {
|
||||
compatible = "gpio-fan";
|
||||
gpios = <&gpio2 14 1
|
||||
&gpio2 13 1>;
|
||||
gpio-fan,speed-map = <0 0>,
|
||||
<3000 1>,
|
||||
<6000 2>;
|
||||
alarm-gpios = <&gpio2 15 1>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -116,6 +116,29 @@ Every GPIO controller node must contain both an empty "gpio-controller"
|
|||
property, and a #gpio-cells integer property, which indicates the number of
|
||||
cells in a gpio-specifier.
|
||||
|
||||
The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism
|
||||
providing automatic GPIO request and configuration as part of the
|
||||
gpio-controller's driver probe function.
|
||||
|
||||
Each GPIO hog definition is represented as a child node of the GPIO controller.
|
||||
Required properties:
|
||||
- gpio-hog: A property specifying that this child node represent a GPIO hog.
|
||||
- gpios: Store the GPIO information (id, flags, ...). Shall contain the
|
||||
number of cells specified in its parent node (GPIO controller
|
||||
node).
|
||||
Only one of the following properties scanned in the order shown below.
|
||||
This means that when multiple properties are present they will be searched
|
||||
in the order presented below and the first match is taken as the intended
|
||||
configuration.
|
||||
- input: A property specifying to set the GPIO direction as input.
|
||||
- output-low A property specifying to set the GPIO direction as output with
|
||||
the value low.
|
||||
- output-high A property specifying to set the GPIO direction as output with
|
||||
the value high.
|
||||
|
||||
Optional properties:
|
||||
- line-name: The GPIO label name. If not present the node name is used.
|
||||
|
||||
Example of two SOC GPIO banks defined as gpio-controller nodes:
|
||||
|
||||
qe_pio_a: gpio-controller@1400 {
|
||||
|
|
@ -123,6 +146,13 @@ Example of two SOC GPIO banks defined as gpio-controller nodes:
|
|||
reg = <0x1400 0x18>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
line_b {
|
||||
gpio-hog;
|
||||
gpios = <6 0>;
|
||||
output-low;
|
||||
line-name = "foo-bar-gpio";
|
||||
};
|
||||
};
|
||||
|
||||
qe_pio_e: gpio-controller@1460 {
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ Required properties:
|
|||
gpio_mux.
|
||||
- interrupt-names : Should be the names of irq resources. Each interrupt
|
||||
uses its own interrupt name, so there should be as many interrupt names
|
||||
as referenced interrups.
|
||||
as referenced interrupts.
|
||||
- interrupt-controller : Identifies the node as an interrupt controller.
|
||||
- #interrupt-cells: Specifies the number of cells needed to encode an
|
||||
interrupt source.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,12 @@
|
|||
HWRNG support for the iproc-rng200 driver
|
||||
|
||||
Required properties:
|
||||
- compatible : "brcm,iproc-rng200"
|
||||
- reg : base address and size of control register block
|
||||
|
||||
Example:
|
||||
|
||||
rng {
|
||||
compatible = "brcm,iproc-rng200";
|
||||
reg = <0x18032000 0x28>;
|
||||
};
|
||||
|
|
@ -10,6 +10,9 @@ Required properties:
|
|||
Recommended properties :
|
||||
- interrupts : standard interrupt property.
|
||||
- clock-frequency : desired I2C bus clock frequency in Hz.
|
||||
- ti,has-pfunc: boolean; if defined, it indicates that SoC supports PFUNC
|
||||
registers. PFUNC registers allow to switch I2C pins to function as
|
||||
GPIOs, so they can by toggled manually.
|
||||
|
||||
Example (enbw_cmc board):
|
||||
i2c@1c22000 {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,25 @@
|
|||
Conexant Digicolor I2C controller
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "cnxt,cx92755-i2c"
|
||||
- reg: physical address and length of the device registers
|
||||
- interrupts: a single interrupt specifier
|
||||
- clocks: clock for the device
|
||||
- #address-cells: should be <1>
|
||||
- #size-cells: should be <0>
|
||||
|
||||
Optional properties:
|
||||
- clock-frequency: the desired I2C bus clock frequency in Hz; in
|
||||
absence of this property the default value is used (100 kHz).
|
||||
|
||||
Example:
|
||||
|
||||
i2c: i2c@f0000120 {
|
||||
compatible = "cnxt,cx92755-i2c";
|
||||
reg = <0xf0000120 0x10>;
|
||||
interrupts = <28>;
|
||||
clocks = <&main_clk>;
|
||||
clock-frequency = <100000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
* Ingenic JZ4780 I2C Bus controller
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "ingenic,jz4780-i2c"
|
||||
- reg: Should contain the address & size of the I2C controller registers.
|
||||
- interrupts: Should specify the interrupt provided by parent.
|
||||
- clocks: Should contain a single clock specifier for the JZ4780 I2C clock.
|
||||
- clock-frequency: desired I2C bus clock frequency in Hz.
|
||||
|
||||
Recommended properties:
|
||||
- pinctrl-names: should be "default";
|
||||
- pinctrl-0: phandle to pinctrl function
|
||||
|
||||
Optional properties:
|
||||
- interrupt-parent: Should be the phandle of the interrupt controller that
|
||||
delivers interrupts to the I2C block.
|
||||
|
||||
Example
|
||||
|
||||
/ {
|
||||
i2c4: i2c4@0x10054000 {
|
||||
compatible = "ingenic,jz4780-i2c";
|
||||
reg = <0x10054000 0x1000>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <56>;
|
||||
|
||||
clocks = <&cgu JZ4780_CLK_SMB4>;
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pins_i2c4_data>;
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
Device tree configuration for the I2C controller on the XLP9xx/5xx SoC
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "netlogic,xlp980-i2c"
|
||||
- reg : bus address start and address range size of device
|
||||
- interrupts : interrupt number
|
||||
|
||||
Optional properties:
|
||||
- clock-frequency : frequency of bus clock in Hz
|
||||
Defaults to 100 KHz when the property is not specified
|
||||
|
||||
Example:
|
||||
|
||||
i2c0: i2c@113100 {
|
||||
compatible = "netlogic,xlp980-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0 0x113100 0x100>;
|
||||
clock-frequency = <400000>;
|
||||
interrupts = <30>;
|
||||
interrupt-parent = <&pic>;
|
||||
};
|
||||
|
|
@ -77,6 +77,7 @@ nxp,pca9556 Octal SMBus and I2C registered interface
|
|||
nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset
|
||||
nxp,pcf8563 Real-time clock/calendar
|
||||
nxp,pcf85063 Tiny Real-Time Clock
|
||||
oki,ml86v7667 OKI ML86V7667 video decoder
|
||||
ovti,ov5642 OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus
|
||||
pericom,pt7c4338 Real-time Clock Module
|
||||
plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch
|
||||
|
|
@ -89,6 +90,7 @@ ricoh,rv5c386 I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
|
|||
ricoh,rv5c387a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
|
||||
samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power)
|
||||
sii,s35390a 2-wire CMOS real-time clock
|
||||
skyworks,sky81452 Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply
|
||||
st-micro,24c256 i2c serial eeprom (24cxx)
|
||||
stm,m41t00 Serial Access TIMEKEEPER
|
||||
stm,m41t62 Serial real-time clock (RTC) with alarm
|
||||
|
|
|
|||
|
|
@ -0,0 +1,16 @@
|
|||
Dialog Semiconductor DA9150 IIO GPADC bindings
|
||||
|
||||
Required properties:
|
||||
- compatible: "dlg,da9150-gpadc" for DA9150 IIO GPADC
|
||||
- #io-channel-cells: Should be set to <1>
|
||||
(See Documentation/devicetree/bindings/iio/iio-bindings.txt for further info)
|
||||
|
||||
For further information on GPADC channels, see device datasheet.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
gpadc: da9150-gpadc {
|
||||
compatible = "dlg,da9150-gpadc";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
* Microchip Analog to Digital Converter (ADC)
|
||||
|
||||
The node for this driver must be a child node of a SPI controller, hence
|
||||
all mandatory properties described in
|
||||
|
||||
Documentation/devicetree/bindings/spi/spi-bus.txt
|
||||
|
||||
must be specified.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be one of the following, depending on the
|
||||
model:
|
||||
"mcp3001"
|
||||
"mcp3002"
|
||||
"mcp3004"
|
||||
"mcp3008"
|
||||
"mcp3201"
|
||||
"mcp3202"
|
||||
"mcp3204"
|
||||
"mcp3208"
|
||||
|
||||
|
||||
Examples:
|
||||
spi_controller {
|
||||
mcp3x0x@0 {
|
||||
compatible = "mcp3002";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
* Microchip mcp3422/3/4/6/7/8 chip family (ADC)
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be
|
||||
"microchip,mcp3422" or
|
||||
"microchip,mcp3423" or
|
||||
"microchip,mcp3424" or
|
||||
"microchip,mcp3426" or
|
||||
"microchip,mcp3427" or
|
||||
"microchip,mcp3428"
|
||||
- reg: I2C address for the device
|
||||
|
||||
Example:
|
||||
adc@0 {
|
||||
compatible = "microchip,mcp3424";
|
||||
reg = <0x68>;
|
||||
};
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
* Texas Instruments' ADC128S052 ADC chip
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "ti,adc128s052"
|
||||
- reg: spi chip select number for the device
|
||||
- vref-supply: The regulator supply for ADC reference voltage
|
||||
|
||||
Recommended properties:
|
||||
- spi-max-frequency: Definition as per
|
||||
Documentation/devicetree/bindings/spi/spi-bus.txt
|
||||
|
||||
Example:
|
||||
adc@0 {
|
||||
compatible = "ti,adc128s052";
|
||||
reg = <0>;
|
||||
vref-supply = <&vdd_supply>;
|
||||
spi-max-frequency = <1000000>;
|
||||
};
|
||||
|
|
@ -23,6 +23,7 @@ standard bindings from pinctrl/pinctrl-bindings.txt.
|
|||
Valid compatible strings:
|
||||
|
||||
Accelerometers:
|
||||
- st,lis3lv02dl-accel
|
||||
- st,lsm303dlh-accel
|
||||
- st,lsm303dlhc-accel
|
||||
- st,lis3dh-accel
|
||||
|
|
|
|||
|
|
@ -0,0 +1,108 @@
|
|||
* Broadcom Keypad Controller device tree bindings
|
||||
|
||||
Broadcom Keypad controller is used to interface a SoC with a matrix-type
|
||||
keypad device. The keypad controller supports multiple row and column lines.
|
||||
A key can be placed at each intersection of a unique row and a unique column.
|
||||
The keypad controller can sense a key-press and key-release and report the
|
||||
event using a interrupt to the cpu.
|
||||
|
||||
This binding is based on the matrix-keymap binding with the following
|
||||
changes:
|
||||
|
||||
keypad,num-rows and keypad,num-columns are required.
|
||||
|
||||
Required SoC Specific Properties:
|
||||
- compatible: should be "brcm,bcm-keypad"
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- interrupts: The interrupt number to the cpu.
|
||||
|
||||
Board Specific Properties:
|
||||
- keypad,num-rows: Number of row lines connected to the keypad
|
||||
controller.
|
||||
|
||||
- keypad,num-columns: Number of column lines connected to the
|
||||
keypad controller.
|
||||
|
||||
- col-debounce-filter-period: The debounce period for the Column filter.
|
||||
|
||||
KEYPAD_DEBOUNCE_1_ms = 0
|
||||
KEYPAD_DEBOUNCE_2_ms = 1
|
||||
KEYPAD_DEBOUNCE_4_ms = 2
|
||||
KEYPAD_DEBOUNCE_8_ms = 3
|
||||
KEYPAD_DEBOUNCE_16_ms = 4
|
||||
KEYPAD_DEBOUNCE_32_ms = 5
|
||||
KEYPAD_DEBOUNCE_64_ms = 6
|
||||
KEYPAD_DEBOUNCE_128_ms = 7
|
||||
|
||||
- status-debounce-filter-period: The debounce period for the Status filter.
|
||||
|
||||
KEYPAD_DEBOUNCE_1_ms = 0
|
||||
KEYPAD_DEBOUNCE_2_ms = 1
|
||||
KEYPAD_DEBOUNCE_4_ms = 2
|
||||
KEYPAD_DEBOUNCE_8_ms = 3
|
||||
KEYPAD_DEBOUNCE_16_ms = 4
|
||||
KEYPAD_DEBOUNCE_32_ms = 5
|
||||
KEYPAD_DEBOUNCE_64_ms = 6
|
||||
KEYPAD_DEBOUNCE_128_ms = 7
|
||||
|
||||
- row-output-enabled: An optional property indicating whether the row or
|
||||
column is being used as output. If specified the row is being used
|
||||
as the output. Else defaults to column.
|
||||
|
||||
- pull-up-enabled: An optional property indicating the Keypad scan mode.
|
||||
If specified implies the keypad scan pull-up has been enabled.
|
||||
|
||||
- autorepeat: Boolean, Enable auto repeat feature of Linux input
|
||||
subsystem (optional).
|
||||
|
||||
- linux,keymap: The keymap for keys as described in the binding document
|
||||
devicetree/bindings/input/matrix-keymap.txt.
|
||||
|
||||
Example:
|
||||
#include "dt-bindings/input/input.h"
|
||||
|
||||
/ {
|
||||
keypad: keypad@180ac000 {
|
||||
/* Required SoC specific properties */
|
||||
compatible = "brcm,bcm-keypad";
|
||||
|
||||
/* Required Board specific properties */
|
||||
keypad,num-rows = <5>;
|
||||
keypad,num-columns = <5>;
|
||||
status = "okay";
|
||||
|
||||
linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_F) /* key_forward */
|
||||
MATRIX_KEY(0x00, 0x03, KEY_HOME) /* key_home */
|
||||
MATRIX_KEY(0x00, 0x04, KEY_M) /* key_message */
|
||||
MATRIX_KEY(0x01, 0x00, KEY_A) /* key_contacts */
|
||||
MATRIX_KEY(0x01, 0x01, KEY_1) /* key_1 */
|
||||
MATRIX_KEY(0x01, 0x02, KEY_2) /* key_2 */
|
||||
MATRIX_KEY(0x01, 0x03, KEY_3) /* key_3 */
|
||||
MATRIX_KEY(0x01, 0x04, KEY_S) /* key_speaker */
|
||||
MATRIX_KEY(0x02, 0x00, KEY_P) /* key_phone */
|
||||
MATRIX_KEY(0x02, 0x01, KEY_4) /* key_4 */
|
||||
MATRIX_KEY(0x02, 0x02, KEY_5) /* key_5 */
|
||||
MATRIX_KEY(0x02, 0x03, KEY_6) /* key_6 */
|
||||
MATRIX_KEY(0x02, 0x04, KEY_VOLUMEUP) /* key_vol_up */
|
||||
MATRIX_KEY(0x03, 0x00, KEY_C) /* key_call_log */
|
||||
MATRIX_KEY(0x03, 0x01, KEY_7) /* key_7 */
|
||||
MATRIX_KEY(0x03, 0x02, KEY_8) /* key_8 */
|
||||
MATRIX_KEY(0x03, 0x03, KEY_9) /* key_9 */
|
||||
MATRIX_KEY(0x03, 0x04, KEY_VOLUMEDOWN) /* key_vol_down */
|
||||
MATRIX_KEY(0x04, 0x00, KEY_H) /* key_headset */
|
||||
MATRIX_KEY(0x04, 0x01, KEY_KPASTERISK) /* key_* */
|
||||
MATRIX_KEY(0x04, 0x02, KEY_0) /* key_0 */
|
||||
MATRIX_KEY(0x04, 0x03, KEY_GRAVE) /* key_# */
|
||||
MATRIX_KEY(0x04, 0x04, KEY_MUTE) /* key_mute */
|
||||
>;
|
||||
|
||||
/* Optional board specific properties */
|
||||
col-debounce-filter-period = <5>;
|
||||
row-output-enabled;
|
||||
pull-up-enabled;
|
||||
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
Qualcomm PM8941 PMIC Power Key
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be one of:
|
||||
"qcom,pm8941-pwrkey"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: base address of registers for block
|
||||
|
||||
- interrupts:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: key change interrupt; The format of the specifier is
|
||||
defined by the binding document describing the node's
|
||||
interrupt parent.
|
||||
|
||||
- debounce:
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: time in microseconds that key must be pressed or released
|
||||
for state change interrupt to trigger.
|
||||
|
||||
- bias-pull-up:
|
||||
Usage: optional
|
||||
Value type: <empty>
|
||||
Definition: presence of this property indicates that the KPDPWR_N pin
|
||||
should be configured for pull up.
|
||||
|
||||
EXAMPLE
|
||||
|
||||
pwrkey@800 {
|
||||
compatible = "qcom,pm8941-pwrkey";
|
||||
reg = <0x800>;
|
||||
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
|
||||
debounce = <15625>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
* Broadcom's IPROC Touchscreen Controller
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "brcm,iproc-touchscreen"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- clocks: The clock provided by the SOC to driver the tsc
|
||||
- clock-name: name for the clock
|
||||
- interrupts: The touchscreen controller's interrupt
|
||||
|
||||
Optional properties:
|
||||
- scanning_period: Time between scans. Each step is 1024 us. Valid 1-256.
|
||||
- debounce_timeout: Each step is 512 us. Valid 0-255
|
||||
- settling_timeout: The settling duration (in ms) is the amount of time
|
||||
the tsc waits to allow the voltage to settle after
|
||||
turning on the drivers in detection mode.
|
||||
Valid values: 0-11
|
||||
0 = 0.008 ms
|
||||
1 = 0.01 ms
|
||||
2 = 0.02 ms
|
||||
3 = 0.04 ms
|
||||
4 = 0.08 ms
|
||||
5 = 0.16 ms
|
||||
6 = 0.32 ms
|
||||
7 = 0.64 ms
|
||||
8 = 1.28 ms
|
||||
9 = 2.56 ms
|
||||
10 = 5.12 ms
|
||||
11 = 10.24 ms
|
||||
- touch_timeout: The continuous number of scan periods in which touch is
|
||||
not detected before the controller returns to idle state.
|
||||
Valid values 0-255.
|
||||
- average_data: Number of data samples which are averaged before a final
|
||||
data point is placed into the FIFO
|
||||
Valid values 0-7
|
||||
0 = 1 sample
|
||||
1 = 2 samples
|
||||
2 = 4 samples
|
||||
3 = 8 samples
|
||||
4 = 16 samples
|
||||
5 = 32 samples
|
||||
6 = 64 samples
|
||||
7 = 128 samples
|
||||
- fifo_threshold: Interrupt is generated whenever the number of fifo
|
||||
entries exceeds this value
|
||||
Valid values 0-31
|
||||
- touchscreen-size-x: horizontal resolution of touchscreen (in pixels)
|
||||
- touchscreen-size-y: vertical resolution of touchscreen (in pixels)
|
||||
- touchscreen-fuzz-x: horizontal noise value of the absolute input
|
||||
device (in pixels)
|
||||
- touchscreen-fuzz-y: vertical noise value of the absolute input
|
||||
device (in pixels)
|
||||
- touchscreen-inverted-x: X axis is inverted (boolean)
|
||||
- touchscreen-inverted-y: Y axis is inverted (boolean)
|
||||
|
||||
Example:
|
||||
|
||||
touchscreen: tsc@0x180A6000 {
|
||||
compatible = "brcm,iproc-touchscreen";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x180A6000 0x40>;
|
||||
clocks = <&adc_clk>;
|
||||
clock-names = "tsc_clk";
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
scanning_period = <5>;
|
||||
debounce_timeout = <40>;
|
||||
settling_timeout = <7>;
|
||||
touch_timeout = <10>;
|
||||
average_data = <5>;
|
||||
fifo_threshold = <1>;
|
||||
/* Touchscreen is rotated 180 degrees. */
|
||||
touchscreen-inverted-x;
|
||||
touchscreen-inverted-y;
|
||||
};
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
* ChipOne icn8318 I2C touchscreen controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "chipone,icn8318"
|
||||
- reg : I2C slave address of the chip (0x40)
|
||||
- interrupt-parent : a phandle pointing to the interrupt controller
|
||||
serving the interrupt for this chip
|
||||
- interrupts : interrupt specification for the icn8318 interrupt
|
||||
- wake-gpios : GPIO specification for the WAKE input
|
||||
- touchscreen-size-x : horizontal resolution of touchscreen (in pixels)
|
||||
- touchscreen-size-y : vertical resolution of touchscreen (in pixels)
|
||||
|
||||
Optional properties:
|
||||
- pinctrl-names : should be "default"
|
||||
- pinctrl-0: : a phandle pointing to the pin settings for the
|
||||
control gpios
|
||||
- touchscreen-fuzz-x : horizontal noise value of the absolute input
|
||||
device (in pixels)
|
||||
- touchscreen-fuzz-y : vertical noise value of the absolute input
|
||||
device (in pixels)
|
||||
- touchscreen-inverted-x : X axis is inverted (boolean)
|
||||
- touchscreen-inverted-y : Y axis is inverted (boolean)
|
||||
- touchscreen-swapped-x-y : X and Y axis are swapped (boolean)
|
||||
Swapping is done after inverting the axis
|
||||
|
||||
Example:
|
||||
|
||||
i2c@00000000 {
|
||||
/* ... */
|
||||
|
||||
chipone_icn8318@40 {
|
||||
compatible = "chipone,icn8318";
|
||||
reg = <0x40>;
|
||||
interrupt-parent = <&pio>;
|
||||
interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ts_wake_pin_p66>;
|
||||
wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
|
||||
touchscreen-size-x = <800>;
|
||||
touchscreen-size-y = <480>;
|
||||
touchscreen-inverted-x;
|
||||
touchscreen-swapped-x-y;
|
||||
};
|
||||
|
||||
/* ... */
|
||||
};
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
Device tree bindings for Goodix GT9xx series touchscreen controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should be "goodix,gt911"
|
||||
or "goodix,gt9110"
|
||||
or "goodix,gt912"
|
||||
or "goodix,gt927"
|
||||
or "goodix,gt9271"
|
||||
or "goodix,gt928"
|
||||
or "goodix,gt967"
|
||||
- reg : I2C address of the chip. Should be 0x5d or 0x14
|
||||
- interrupt-parent : Interrupt controller to which the chip is connected
|
||||
- interrupts : Interrupt to which the chip is connected
|
||||
|
||||
Example:
|
||||
|
||||
i2c@00000000 {
|
||||
/* ... */
|
||||
|
||||
gt928@5d {
|
||||
compatible = "goodix,gt928";
|
||||
reg = <0x5d>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <0 0>;
|
||||
};
|
||||
|
||||
/* ... */
|
||||
};
|
||||
|
|
@ -2,14 +2,27 @@ sun4i resistive touchscreen controller
|
|||
--------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: "allwinner,sun4i-a10-ts" or "allwinner,sun6i-a31-ts"
|
||||
- compatible: "allwinner,sun4i-a10-ts", "allwinner,sun5i-a13-ts" or
|
||||
"allwinner,sun6i-a31-ts"
|
||||
- reg: mmio address range of the chip
|
||||
- interrupts: interrupt to which the chip is connected
|
||||
- #thermal-sensor-cells: shall be 0
|
||||
|
||||
Optional properties:
|
||||
- allwinner,ts-attached: boolean indicating that an actual touchscreen is
|
||||
attached to the controller
|
||||
- allwinner,ts-attached : boolean indicating that an actual touchscreen
|
||||
is attached to the controller
|
||||
- allwinner,tp-sensitive-adjust : integer (4 bits)
|
||||
adjust sensitivity of pen down detection
|
||||
between 0 (least sensitive) and 15
|
||||
(defaults to 15)
|
||||
- allwinner,filter-type : integer (2 bits)
|
||||
select median and averaging filter
|
||||
samples used for median / averaging filter
|
||||
0: 4/2
|
||||
1: 5/3
|
||||
2: 8/4
|
||||
3: 16/8
|
||||
(defaults to 1)
|
||||
|
||||
Example:
|
||||
|
||||
|
|
@ -19,4 +32,7 @@ Example:
|
|||
interrupts = <29>;
|
||||
allwinner,ts-attached;
|
||||
#thermal-sensor-cells = <0>;
|
||||
/* sensitive/noisy touch panel */
|
||||
allwinner,tp-sensitive-adjust = <0>;
|
||||
allwinner,filter-type = <3>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,16 @@
|
|||
* Semtech SX8654 I2C Touchscreen Controller
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "semtech,sx8654"
|
||||
- reg: i2c slave address
|
||||
- interrupt-parent: the phandle for the interrupt controller
|
||||
- interrupts: touch controller interrupt
|
||||
|
||||
Example:
|
||||
|
||||
sx8654@48 {
|
||||
compatible = "semtech,sx8654";
|
||||
reg = <0x48>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
|
|
@ -16,6 +16,8 @@ Optional properties for Touchscreens:
|
|||
controller)
|
||||
- touchscreen-inverted-x : X axis is inverted (boolean)
|
||||
- touchscreen-inverted-y : Y axis is inverted (boolean)
|
||||
- touchscreen-swapped-x-y : X and Y axis are swapped (boolean)
|
||||
Swapping is done after inverting the axis
|
||||
|
||||
Deprecated properties for Touchscreens:
|
||||
- x-size : deprecated name for touchscreen-size-x
|
||||
|
|
|
|||
|
|
@ -0,0 +1,41 @@
|
|||
Broadcom BCM3380-style Level 1 / Level 2 interrupt controller
|
||||
|
||||
This interrupt controller shows up in various forms on many BCM338x/BCM63xx
|
||||
chipsets. It has the following properties:
|
||||
|
||||
- outputs a single interrupt signal to its interrupt controller parent
|
||||
|
||||
- contains one or more enable/status word pairs, which often appear at
|
||||
different offsets in different blocks
|
||||
|
||||
- no atomic set/clear operations
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be "brcm,bcm3380-l2-intc"
|
||||
- reg: specifies one or more enable/status pairs, in the following format:
|
||||
<enable_reg 0x4 status_reg 0x4>...
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
|
||||
source, should be 1.
|
||||
- interrupt-parent: specifies the phandle to the parent interrupt controller
|
||||
this one is cascaded from
|
||||
- interrupts: specifies the interrupt line in the interrupt-parent controller
|
||||
node, valid values depend on the type of parent interrupt controller
|
||||
|
||||
Optional properties:
|
||||
|
||||
- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
|
||||
wakeup source for system suspend/resume.
|
||||
|
||||
Example:
|
||||
|
||||
irq0_intc: interrupt-controller@10000020 {
|
||||
compatible = "brcm,bcm3380-l2-intc";
|
||||
reg = <0x10000024 0x4 0x1000002c 0x4>,
|
||||
<0x10000020 0x4 0x10000028 0x4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
Broadcom BCM7038-style Level 1 interrupt controller
|
||||
|
||||
This block is a first level interrupt controller that is typically connected
|
||||
directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
|
||||
since BCM7038 has contained this hardware.
|
||||
|
||||
Key elements of the hardware design include:
|
||||
|
||||
- 64, 96, 128, or 160 incoming level IRQ lines
|
||||
|
||||
- Most onchip peripherals are wired directly to an L1 input
|
||||
|
||||
- A separate instance of the register set for each CPU, allowing individual
|
||||
peripheral IRQs to be routed to any CPU
|
||||
|
||||
- Atomic mask/unmask operations
|
||||
|
||||
- No polarity/level/edge settings
|
||||
|
||||
- No FIFO or priority encoder logic; software is expected to read all
|
||||
2-5 status words to determine which IRQs are pending
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be "brcm,bcm7038-l1-intc"
|
||||
- reg: specifies the base physical address and size of the registers;
|
||||
the number of supported IRQs is inferred from the size argument
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
|
||||
source, should be 1.
|
||||
- interrupt-parent: specifies the phandle to the parent interrupt controller(s)
|
||||
this one is cascaded from
|
||||
- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
|
||||
node; valid values depend on the type of parent interrupt controller
|
||||
|
||||
If multiple reg ranges and interrupt-parent entries are present on an SMP
|
||||
system, the driver will allow IRQ SMP affinity to be set up through the
|
||||
/proc/irq/ interface. In the simplest possible configuration, only one
|
||||
reg range and one interrupt-parent is needed.
|
||||
|
||||
Example:
|
||||
|
||||
periph_intc: periph_intc@1041a400 {
|
||||
compatible = "brcm,bcm7038-l1-intc";
|
||||
reg = <0x1041a400 0x30 0x1041a600 0x30>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <2>, <3>;
|
||||
};
|
||||
|
|
@ -13,8 +13,7 @@ Such an interrupt controller has the following hardware design:
|
|||
or if they will output an interrupt signal at this 2nd level interrupt
|
||||
controller, in particular for UARTs
|
||||
|
||||
- typically has one 32-bit enable word and one 32-bit status word, but on
|
||||
some hardware may have more than one enable/status pair
|
||||
- has one 32-bit enable word and one 32-bit status word
|
||||
|
||||
- no atomic set/clear operations
|
||||
|
||||
|
|
@ -53,9 +52,7 @@ The typical hardware layout for this controller is represented below:
|
|||
Required properties:
|
||||
|
||||
- compatible: should be "brcm,bcm7120-l2-intc"
|
||||
- reg: specifies the base physical address and size of the registers;
|
||||
multiple pairs may be specified, with the first pair handling IRQ offsets
|
||||
0..31 and the second pair handling 32..63
|
||||
- reg: specifies the base physical address and size of the registers
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
|
||||
source, should be 1.
|
||||
|
|
@ -66,10 +63,7 @@ Required properties:
|
|||
- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts
|
||||
are wired to this 2nd level interrupt controller, and how they match their
|
||||
respective interrupt parents. Should match exactly the number of interrupts
|
||||
specified in the 'interrupts' property, multiplied by the number of
|
||||
enable/status register pairs implemented by this controller. For
|
||||
multiple parent IRQs with multiple enable/status words, this looks like:
|
||||
<irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
|
||||
specified in the 'interrupts' property.
|
||||
|
||||
Optional properties:
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,18 @@
|
|||
* Xtensa Interrupt Distributor and Programmable Interrupt Controller (MX)
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "cdns,xtensa-mx".
|
||||
|
||||
Remaining properties have exact same meaning as in Xtensa PIC
|
||||
(see cdns,xtensa-pic.txt).
|
||||
|
||||
Examples:
|
||||
pic: pic {
|
||||
compatible = "cdns,xtensa-mx";
|
||||
/* one cell: internal irq number,
|
||||
* two cells: second cell == 0: internal irq number
|
||||
* second cell == 1: external irq number
|
||||
*/
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
* Xtensa built-in Programmable Interrupt Controller (PIC)
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "cdns,xtensa-pic".
|
||||
- interrupt-controller: Identifies the node as an interrupt controller.
|
||||
- #interrupt-cells: The number of cells to define the interrupts.
|
||||
It may be either 1 or 2.
|
||||
When it's 1, the first cell is the internal IRQ number.
|
||||
When it's 2, the first cell is the IRQ number, and the second cell
|
||||
specifies whether it's internal (0) or external (1).
|
||||
Periferals are usually connected to a fixed external IRQ, but for different
|
||||
core variants it may be mapped to different internal IRQ.
|
||||
IRQ sensitivity and priority are fixed for each core variant and may not be
|
||||
changed at runtime.
|
||||
|
||||
Examples:
|
||||
pic: pic {
|
||||
compatible = "cdns,xtensa-pic";
|
||||
/* one cell: internal irq number,
|
||||
* two cells: second cell == 0: internal irq number
|
||||
* second cell == 1: external irq number
|
||||
*/
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
|
@ -27,8 +27,13 @@ Optional properties:
|
|||
Required properties for timer sub-node:
|
||||
- compatible : Should be "mti,gic-timer".
|
||||
- interrupts : Interrupt for the GIC local timer.
|
||||
|
||||
Optional properties for timer sub-node:
|
||||
- clocks : GIC timer operating clock.
|
||||
- clock-frequency : Clock frequency at which the GIC timers operate.
|
||||
|
||||
Note that one of clocks or clock-frequency must be specified.
|
||||
|
||||
Example:
|
||||
|
||||
gic: interrupt-controller@1bdc0000 {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,43 @@
|
|||
NVIDIA Legacy Interrupt Controller
|
||||
|
||||
All Tegra SoCs contain a legacy interrupt controller that routes
|
||||
interrupts to the GIC, and also serves as a wakeup source. It is also
|
||||
referred to as "ictlr", hence the name of the binding.
|
||||
|
||||
The HW block exposes a number of interrupt controllers, each
|
||||
implementing a set of 32 interrupts.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be: "nvidia,tegra<chip>-ictlr". The LIC on
|
||||
subsequent SoCs remained backwards-compatible with Tegra30, so on
|
||||
Tegra generations later than Tegra30 the compatible value should
|
||||
include "nvidia,tegra30-ictlr".
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
Each controller must be described separately (Tegra20 has 4 of them,
|
||||
whereas Tegra30 and later have 5"
|
||||
- interrupt-controller : Identifies the node as an interrupt controller.
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. The value must be 3.
|
||||
- interrupt-parent : a phandle to the GIC these interrupts are routed
|
||||
to.
|
||||
|
||||
Notes:
|
||||
|
||||
- Because this HW ultimately routes interrupts to the GIC, the
|
||||
interrupt specifier must be that of the GIC.
|
||||
- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
|
||||
are explicitly forbidden.
|
||||
|
||||
Example:
|
||||
|
||||
ictlr: interrupt-controller@60004000 {
|
||||
compatible = "nvidia,tegra20-ictlr", "nvidia,tegra-ictlr";
|
||||
reg = <0x60004000 64>,
|
||||
<0x60004100 64>,
|
||||
<0x60004200 64>,
|
||||
<0x60004300 64>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&intc>;
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue