BUBINGA405EP board added (IBM PPC405EP Eval Board).
This commit is contained in:
stroese
parent
c93f70962b
commit
46578cc018
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@ -0,0 +1,47 @@
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#
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o flash.o
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SOBJS = init.o
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $^
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend
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#########################################################################
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@ -0,0 +1,126 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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long int spd_sdram (void);
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#include <common.h>
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#include "bubinga405ep.h"
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#include <asm/processor.h>
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int board_pre_init (void)
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{
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr (uicer, 0x00000000); /* disable all ints */
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mtdcr (uiccr, 0x00000010);
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mtdcr (uicpr, 0xFFFF7FF0); /* set int polarities */
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mtdcr (uictr, 0x00000010); /* set int trigger levels */
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
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#if 0
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#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
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/* CS1 */
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/* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
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mtebc (pb1ap, 0x02815480);
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mtebc (pb1cr, 0xF0018000);
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p = (unsigned int*)0xEF600708;
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t = *p;
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t = t | 0x00000400;
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*p = t;
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/* BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
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mtebc (pb2ap, 0x04815A80);
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mtebc (pb2cr, 0xF0118000);
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/* BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
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mtebc (pb3ap, 0x01815280);
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mtebc (pb3cr, 0xF0218000);
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/* BAS=0xF03,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
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mtebc (pb7ap, 0x01815280);
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mtebc (pb7cr, 0xF0318000);
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/* set UART1 control to select CTS/RTS */
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#define FPGA_BRDC 0xF0300004
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*(volatile char *) (FPGA_BRDC) |= 0x1;
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#endif
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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unsigned char *s = getenv ("serial#");
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unsigned char *e;
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puts ("Board: ");
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if (!s || strncmp (s, "BUBINGA405EP", 9)) {
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puts ("### No HW ID - assuming WALNUT405");
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} else {
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for (e = s; *e; ++e) {
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if (*e == ' ')
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break;
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}
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for (; s < e; ++s) {
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putc (*s);
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}
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}
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putc ('\n');
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return (0);
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}
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/* -------------------------------------------------------------------------
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initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
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the necessary info for SDRAM controller configuration
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------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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long int ret;
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ret = spd_sdram ();
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return ret;
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}
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/* ------------------------------------------------------------------------- */
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int testdram (void)
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{
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/* TODO: XXX XXX XXX */
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printf ("test: xxx MB - ok\n");
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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@ -0,0 +1,44 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/****************************************************************************
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* FLASH Memory Map as used by TQ Monitor:
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*
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* Start Address Length
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* +-----------------------+ 0x4000_0000 Start of Flash -----------------
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* | MON8xx code | 0x4000_0100 Reset Vector
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* +-----------------------+ 0x400?_????
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* | (unused) |
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* +-----------------------+ 0x4001_FF00
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* | Ethernet Addresses | 0x78
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* +-----------------------+ 0x4001_FF78
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* | (Reserved for MON8xx) | 0x44
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* +-----------------------+ 0x4001_FFBC
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* | Lock Address | 0x04
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* +-----------------------+ 0x4001_FFC0 ^
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* | Hardware Information | 0x40 | MON8xx
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* +=======================+ 0x4002_0000 (sector border) -----------------
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* | Autostart Header | | Applications
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* | ... | v
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*
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*****************************************************************************/
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@ -0,0 +1,29 @@
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#
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# esd ADCIOP boards
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#
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#TEXT_BASE = 0xFFFE0000
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TEXT_BASE = 0xFFF80000
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@ -0,0 +1,737 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
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* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Modified 4/5/2001
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* Wait for completion of each sector erase command issued
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* 4/5/2001
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* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
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*/
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#include <common.h>
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#include <ppc4xx.h>
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#include <asm/processor.h>
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size (vu_long *addr, flash_info_t *info);
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static int write_word (flash_info_t *info, ulong dest, ulong data);
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static void flash_get_offsets (ulong base, flash_info_t *info);
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#ifdef CONFIG_ADCIOP
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#define ADDR0 0x0aa9
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#define ADDR1 0x0556
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#define FLASH_WORD_SIZE unsigned char
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#endif
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#ifdef CONFIG_CPCI405
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#define ADDR0 0x5555
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#define ADDR1 0x2aaa
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#define FLASH_WORD_SIZE unsigned short
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#endif
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#ifdef CONFIG_WALNUT405
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#define ADDR0 0x5555
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#define ADDR1 0x2aaa
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#define FLASH_WORD_SIZE unsigned char
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#endif
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#ifdef CONFIG_BUBINGA405EP
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#define ADDR0 0x5555
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#define ADDR1 0x2aaa
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#define FLASH_WORD_SIZE unsigned char
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#endif
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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unsigned long size_b0, size_b1;
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int i;
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uint pbcr;
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unsigned long base_b0, base_b1;
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/* Init: no FLASHes known */
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for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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}
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/* Static FLASH Bank configuration here - FIXME XXX */
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size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
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if (flash_info[0].flash_id == FLASH_UNKNOWN) {
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
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size_b0, size_b0<<20);
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}
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/* Only one bank */
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if (CFG_MAX_FLASH_BANKS == 1)
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{
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/* Setup offsets */
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flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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FLASH_BASE0_PRELIM,
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FLASH_BASE0_PRELIM+CFG_MONITOR_LEN-1,
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&flash_info[0]);
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size_b1 = 0 ;
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flash_info[0].size = size_b0;
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}
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/* 2 banks */
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else
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{
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size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
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/* Re-do sizing to get full correct info */
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if (size_b1)
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{
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mtdcr(ebccfga, pb0cr);
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pbcr = mfdcr(ebccfgd);
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mtdcr(ebccfga, pb0cr);
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base_b1 = -size_b1;
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pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
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mtdcr(ebccfgd, pbcr);
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/* printf("pb1cr = %x\n", pbcr); */
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}
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if (size_b0)
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{
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mtdcr(ebccfga, pb1cr);
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pbcr = mfdcr(ebccfgd);
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mtdcr(ebccfga, pb1cr);
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base_b0 = base_b1 - size_b0;
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pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
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mtdcr(ebccfgd, pbcr);
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/* printf("pb0cr = %x\n", pbcr); */
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}
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size_b0 = flash_get_size((vu_long *)base_b0, &flash_info[0]);
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flash_get_offsets (base_b0, &flash_info[0]);
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/* monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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base_b0+size_b0-CFG_MONITOR_LEN,
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base_b0+size_b0-1,
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&flash_info[0]);
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if (size_b1) {
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/* Re-do sizing to get full correct info */
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size_b1 = flash_get_size((vu_long *)base_b1, &flash_info[1]);
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flash_get_offsets (base_b1, &flash_info[1]);
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/* monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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base_b1+size_b1-CFG_MONITOR_LEN,
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base_b1+size_b1-1,
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&flash_info[1]);
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/* monitor protection OFF by default (one is enough) */
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(void)flash_protect(FLAG_PROTECT_CLEAR,
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base_b0+size_b0-CFG_MONITOR_LEN,
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base_b0+size_b0-1,
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&flash_info[0]);
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} else {
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flash_info[1].flash_id = FLASH_UNKNOWN;
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flash_info[1].sector_count = -1;
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}
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flash_info[0].size = size_b0;
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flash_info[1].size = size_b1;
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}/* else 2 banks */
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return (size_b0 + size_b1);
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}
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/*-----------------------------------------------------------------------
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*/
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static void flash_get_offsets (ulong base, flash_info_t *info)
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{
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int i;
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/* set up sector start address table */
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if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
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(info->flash_id == FLASH_AM040)){
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for (i = 0; i < info->sector_count; i++)
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info->start[i] = base + (i * 0x00010000);
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} else {
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if (info->flash_id & FLASH_BTYPE) {
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/* set sector offsets for bottom boot block type */
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info->start[0] = base + 0x00000000;
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info->start[1] = base + 0x00004000;
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info->start[2] = base + 0x00006000;
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info->start[3] = base + 0x00008000;
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for (i = 4; i < info->sector_count; i++) {
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info->start[i] = base + (i * 0x00010000) - 0x00030000;
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}
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} else {
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/* set sector offsets for top boot block type */
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i = info->sector_count - 1;
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info->start[i--] = base + info->size - 0x00004000;
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info->start[i--] = base + info->size - 0x00006000;
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info->start[i--] = base + info->size - 0x00008000;
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for (; i >= 0; i--) {
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info->start[i] = base + i * 0x00010000;
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}
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}
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}
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t *info)
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{
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int i;
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int k;
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int size;
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int erased;
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||||
volatile unsigned long *flash;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
|
||||
}
|
||||
|
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_AMD: printf ("AMD "); break;
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case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
|
||||
case FLASH_MAN_SST: printf ("SST "); break;
|
||||
default: printf ("Unknown Vendor "); break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n");
|
||||
break;
|
||||
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
|
||||
break;
|
||||
case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
|
||||
break;
|
||||
default: printf ("Unknown Chip Type\n");
|
||||
break;
|
||||
}
|
||||
|
||||
printf (" Size: %ld KB in %d Sectors\n",
|
||||
info->size >> 10, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i=0; i<info->sector_count; ++i) {
|
||||
/*
|
||||
* Check if whole sector is erased
|
||||
*/
|
||||
if (i != (info->sector_count-1))
|
||||
size = info->start[i+1] - info->start[i];
|
||||
else
|
||||
size = info->start[0] + info->size - info->start[i];
|
||||
erased = 1;
|
||||
flash = (volatile unsigned long *)info->start[i];
|
||||
size = size >> 2; /* divide by 4 for longword access */
|
||||
for (k=0; k<size; k++)
|
||||
{
|
||||
if (*flash++ != 0xffffffff)
|
||||
{
|
||||
erased = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
#if 0 /* test-only */
|
||||
printf (" %08lX%s",
|
||||
info->start[i],
|
||||
info->protect[i] ? " (RO)" : " "
|
||||
#else
|
||||
printf (" %08lX%s%s",
|
||||
info->start[i],
|
||||
erased ? " E" : " ",
|
||||
info->protect[i] ? "RO " : " "
|
||||
#endif
|
||||
);
|
||||
}
|
||||
printf ("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*/
|
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
|
||||
{
|
||||
short i;
|
||||
FLASH_WORD_SIZE value;
|
||||
ulong base = (ulong)addr;
|
||||
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
|
||||
|
||||
/* Write auto select command: read Manufacturer ID */
|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
|
||||
|
||||
#ifdef CONFIG_ADCIOP
|
||||
value = addr2[2];
|
||||
#else
|
||||
value = addr2[0];
|
||||
#endif
|
||||
|
||||
switch (value) {
|
||||
case (FLASH_WORD_SIZE)AMD_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_AMD;
|
||||
break;
|
||||
case (FLASH_WORD_SIZE)FUJ_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_FUJ;
|
||||
break;
|
||||
case (FLASH_WORD_SIZE)SST_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_SST;
|
||||
break;
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ADCIOP
|
||||
value = addr2[0]; /* device ID */
|
||||
/* printf("\ndev_code=%x\n", value); */
|
||||
#else
|
||||
value = addr2[1]; /* device ID */
|
||||
#endif
|
||||
|
||||
switch (value) {
|
||||
case (FLASH_WORD_SIZE)AMD_ID_F040B:
|
||||
info->flash_id += FLASH_AM040;
|
||||
info->sector_count = 8;
|
||||
info->size = 0x0080000; /* => 512 ko */
|
||||
break;
|
||||
case (FLASH_WORD_SIZE)AMD_ID_LV400T:
|
||||
info->flash_id += FLASH_AM400T;
|
||||
info->sector_count = 11;
|
||||
info->size = 0x00080000;
|
||||
break; /* => 0.5 MB */
|
||||
|
||||
case (FLASH_WORD_SIZE)AMD_ID_LV400B:
|
||||
info->flash_id += FLASH_AM400B;
|
||||
info->sector_count = 11;
|
||||
info->size = 0x00080000;
|
||||
break; /* => 0.5 MB */
|
||||
|
||||
case (FLASH_WORD_SIZE)AMD_ID_LV800T:
|
||||
info->flash_id += FLASH_AM800T;
|
||||
info->sector_count = 19;
|
||||
info->size = 0x00100000;
|
||||
break; /* => 1 MB */
|
||||
|
||||
case (FLASH_WORD_SIZE)AMD_ID_LV800B:
|
||||
info->flash_id += FLASH_AM800B;
|
||||
info->sector_count = 19;
|
||||
info->size = 0x00100000;
|
||||
break; /* => 1 MB */
|
||||
|
||||
case (FLASH_WORD_SIZE)AMD_ID_LV160T:
|
||||
info->flash_id += FLASH_AM160T;
|
||||
info->sector_count = 35;
|
||||
info->size = 0x00200000;
|
||||
break; /* => 2 MB */
|
||||
|
||||
case (FLASH_WORD_SIZE)AMD_ID_LV160B:
|
||||
info->flash_id += FLASH_AM160B;
|
||||
info->sector_count = 35;
|
||||
info->size = 0x00200000;
|
||||
break; /* => 2 MB */
|
||||
#if 0 /* enable when device IDs are available */
|
||||
case (FLASH_WORD_SIZE)AMD_ID_LV320T:
|
||||
info->flash_id += FLASH_AM320T;
|
||||
info->sector_count = 67;
|
||||
info->size = 0x00400000;
|
||||
break; /* => 4 MB */
|
||||
|
||||
case (FLASH_WORD_SIZE)AMD_ID_LV320B:
|
||||
info->flash_id += FLASH_AM320B;
|
||||
info->sector_count = 67;
|
||||
info->size = 0x00400000;
|
||||
break; /* => 4 MB */
|
||||
#endif
|
||||
case (FLASH_WORD_SIZE)SST_ID_xF800A:
|
||||
info->flash_id += FLASH_SST800A;
|
||||
info->sector_count = 16;
|
||||
info->size = 0x00100000;
|
||||
break; /* => 1 MB */
|
||||
|
||||
case (FLASH_WORD_SIZE)SST_ID_xF160A:
|
||||
info->flash_id += FLASH_SST160A;
|
||||
info->sector_count = 32;
|
||||
info->size = 0x00200000;
|
||||
break; /* => 2 MB */
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
return (0); /* => no or unknown flash */
|
||||
|
||||
}
|
||||
|
||||
/* set up sector start address table */
|
||||
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
|
||||
(info->flash_id == FLASH_AM040)){
|
||||
for (i = 0; i < info->sector_count; i++)
|
||||
info->start[i] = base + (i * 0x00010000);
|
||||
} else {
|
||||
if (info->flash_id & FLASH_BTYPE) {
|
||||
/* set sector offsets for bottom boot block type */
|
||||
info->start[0] = base + 0x00000000;
|
||||
info->start[1] = base + 0x00004000;
|
||||
info->start[2] = base + 0x00006000;
|
||||
info->start[3] = base + 0x00008000;
|
||||
for (i = 4; i < info->sector_count; i++) {
|
||||
info->start[i] = base + (i * 0x00010000) - 0x00030000;
|
||||
}
|
||||
} else {
|
||||
/* set sector offsets for top boot block type */
|
||||
i = info->sector_count - 1;
|
||||
info->start[i--] = base + info->size - 0x00004000;
|
||||
info->start[i--] = base + info->size - 0x00006000;
|
||||
info->start[i--] = base + info->size - 0x00008000;
|
||||
for (; i >= 0; i--) {
|
||||
info->start[i] = base + i * 0x00010000;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* check for protected sectors */
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
|
||||
/* D0 = 1 if protected */
|
||||
#ifdef CONFIG_ADCIOP
|
||||
addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
|
||||
info->protect[i] = addr2[4] & 1;
|
||||
#else
|
||||
addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
|
||||
info->protect[i] = 0;
|
||||
else
|
||||
info->protect[i] = addr2[2] & 1;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Prevent writes to uninitialized FLASH.
|
||||
*/
|
||||
if (info->flash_id != FLASH_UNKNOWN) {
|
||||
#if 0 /* test-only */
|
||||
#ifdef CONFIG_ADCIOP
|
||||
addr2 = (volatile unsigned char *)info->start[0];
|
||||
addr2[ADDR0] = 0xAA;
|
||||
addr2[ADDR1] = 0x55;
|
||||
addr2[ADDR0] = 0xF0; /* reset bank */
|
||||
#else
|
||||
addr2 = (FLASH_WORD_SIZE *)info->start[0];
|
||||
*addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
|
||||
#endif
|
||||
#else /* test-only */
|
||||
addr2 = (FLASH_WORD_SIZE *)info->start[0];
|
||||
*addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
|
||||
#endif /* test-only */
|
||||
}
|
||||
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
int wait_for_DQ7(flash_info_t *info, int sect)
|
||||
{
|
||||
ulong start, now, last;
|
||||
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
|
||||
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return -1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
|
||||
volatile FLASH_WORD_SIZE *addr2;
|
||||
int flag, prot, sect, l_sect;
|
||||
int i;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("Can't erase unknown flash type - aborted\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect=s_first; sect<=s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect<=s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
|
||||
printf("Erasing sector %p\n", addr2); /* CLH */
|
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
|
||||
addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
|
||||
for (i=0; i<50; i++)
|
||||
udelay(1000); /* wait 1 ms */
|
||||
} else {
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
|
||||
addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
|
||||
}
|
||||
l_sect = sect;
|
||||
/*
|
||||
* Wait for each sector to complete, it's more
|
||||
* reliable. According to AMD Spec, you must
|
||||
* issue all erase commands within a specified
|
||||
* timeout. This has been seen to fail, especially
|
||||
* if printf()s are included (for debug)!!
|
||||
*/
|
||||
wait_for_DQ7(info, sect);
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
|
||||
#if 0
|
||||
/*
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
if (l_sect < 0)
|
||||
goto DONE;
|
||||
wait_for_DQ7(info, l_sect);
|
||||
|
||||
DONE:
|
||||
#endif
|
||||
/* reset to read mode */
|
||||
addr = (FLASH_WORD_SIZE *)info->start[0];
|
||||
addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
|
||||
|
||||
printf (" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp, data;
|
||||
int i, l, rc;
|
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
for (; i<4 && cnt>0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt==0 && i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cnt >= 4) {
|
||||
data = 0;
|
||||
for (i=0; i<4; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
}
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
cnt -= 4;
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
return (write_word(info, wp, data));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word (flash_info_t * info, ulong dest, ulong data)
|
||||
{
|
||||
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
|
||||
volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
|
||||
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
|
||||
ulong start;
|
||||
int i;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*((volatile FLASH_WORD_SIZE *) dest) &
|
||||
(FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
|
||||
return (2);
|
||||
}
|
||||
|
||||
for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
|
||||
int flag;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts ();
|
||||
|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
|
||||
|
||||
dest2[i] = data2[i];
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts ();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
|
||||
(data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
|
||||
|
||||
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*------------------------------------------------------------------------------+ */
|
||||
/* */
|
||||
/* This source code has been made available to you by IBM on an AS-IS */
|
||||
/* basis. Anyone receiving this source is licensed under IBM */
|
||||
/* copyrights to use it in any way he or she deems fit, including */
|
||||
/* copying it, modifying it, compiling it, and redistributing it either */
|
||||
/* with or without modifications. No license under IBM patents or */
|
||||
/* patent applications is to be implied by the copyright license. */
|
||||
/* */
|
||||
/* Any user of this software should understand that IBM cannot provide */
|
||||
/* technical support for this software and will not be responsible for */
|
||||
/* any consequences resulting from the use of this software. */
|
||||
/* */
|
||||
/* Any person who transfers this source code or any derivative work */
|
||||
/* must include the IBM copyright notice, this paragraph, and the */
|
||||
/* preceding two paragraphs in the transferred software. */
|
||||
/* */
|
||||
/* COPYRIGHT I B M CORPORATION 1995 */
|
||||
/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
|
||||
/*------------------------------------------------------------------------------- */
|
||||
|
||||
/*----------------------------------------------------------------------------- */
|
||||
/* Function: ext_bus_cntlr_init */
|
||||
/* Description: Initializes the External Bus Controller for the external */
|
||||
/* peripherals. IMPORTANT: For pass1 this code must run from */
|
||||
/* cache since you can not reliably change a peripheral banks */
|
||||
/* timing register (pbxap) while running code from that bank. */
|
||||
/* For ex., since we are running from ROM on bank 0, we can NOT */
|
||||
/* execute the code that modifies bank 0 timings from ROM, so */
|
||||
/* we run it from cache. */
|
||||
/* Bank 0 - Flash and SRAM */
|
||||
/* Bank 1 - NVRAM/RTC */
|
||||
/* Bank 2 - Keyboard/Mouse controller */
|
||||
/* Bank 3 - IR controller */
|
||||
/* Bank 4 - not used */
|
||||
/* Bank 5 - not used */
|
||||
/* Bank 6 - not used */
|
||||
/* Bank 7 - FPGA registers */
|
||||
/*----------------------------------------------------------------------------- */
|
||||
#include <ppc4xx.h>
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <ppc_defs.h>
|
||||
|
||||
#include <asm/cache.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------- */
|
||||
/* Function: sdram_init */
|
||||
/* Description: Dummy implementation here - done in C later */
|
||||
/*----------------------------------------------------------------------------- */
|
||||
.globl sdram_init
|
||||
sdram_init:
|
||||
blr
|
||||
|
|
@ -0,0 +1,144 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
.resetvec 0xFFFFFFFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
board/bubinga405ep/init.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
cpu/ppc4xx/405gp_enet.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* . = env_offset;*/
|
||||
/* common/environment.o(.text)*/
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -0,0 +1,147 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
/*
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/vsprintf.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
*/
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
board/bubinga405ep/init.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
cpu/ppc4xx/405gp_enet.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
|
||||
common/environment.o(.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,426 @@
|
|||
/*
|
||||
* (C) Copyright 2000, 2001
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* Debug options */
|
||||
//#define __DEBUG_START_FROM_SRAM__
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
|
||||
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
|
||||
#define CONFIG_BUBINGA405EP 1 /* ...on a BUBINGA405EP board */
|
||||
|
||||
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
|
||||
|
||||
#define CONFIG_NO_SERIAL_EEPROM
|
||||
/*#undef CONFIG_NO_SERIAL_EEPROM*/
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*----------------------------------------------------------------------------*/
|
||||
#ifdef CONFIG_NO_SERIAL_EEPROM
|
||||
|
||||
/*
|
||||
!-------------------------------------------------------------------------------
|
||||
! Defines for entry options.
|
||||
! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
|
||||
! are plugged in the board will be utilized as non-ECC DIMMs.
|
||||
!-------------------------------------------------------------------------------
|
||||
*/
|
||||
#define AUTO_MEMORY_CONFIG
|
||||
#define DIMM_READ_ADDR 0xAB
|
||||
#define DIMM_WRITE_ADDR 0xAA
|
||||
|
||||
/*
|
||||
!-------------------------------------------------------------------------------
|
||||
! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
|
||||
! assuming a 33MHz input clock to the 405EP from the C9531.
|
||||
!-------------------------------------------------------------------------------
|
||||
*/
|
||||
#define PLLMR0_DEFAULT PLLMR0_266_133_66
|
||||
#define PLLMR1_DEFAULT PLLMR1_266_133_66
|
||||
|
||||
#endif
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/*#define CFG_ENV_IS_IN_FLASH 1*/ /* use FLASH for environment vars */
|
||||
#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
|
||||
|
||||
#ifdef CFG_ENV_IS_IN_NVRAM
|
||||
#undef CFG_ENV_IS_IN_FLASH
|
||||
#else
|
||||
#ifdef CFG_ENV_IS_IN_FLASH
|
||||
#undef CFG_ENV_IS_IN_NVRAM
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
|
||||
|
||||
#if 1
|
||||
#define CONFIG_BOOTCOMMAND "" /* autoboot command */
|
||||
#else
|
||||
#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
|
||||
#endif
|
||||
|
||||
/* Size (bytes) of interrupt driven serial port buffer.
|
||||
* Set to 0 to use polling instead of interrupts.
|
||||
* Setting to 0 will also disable RTS/CTS handshaking.
|
||||
*/
|
||||
#if 0
|
||||
#define CONFIG_SERIAL_SOFTWARE_FIFO 4000
|
||||
#else
|
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
#define CONFIG_BOOTARGS "root=/dev/nfs " \
|
||||
"ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
|
||||
"nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
|
||||
#else
|
||||
#define CONFIG_BOOTARGS "root=/dev/hda1 " \
|
||||
"ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
|
||||
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 1 /* PHY address */
|
||||
|
||||
#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */
|
||||
|
||||
/*
|
||||
#ifndef __DEBUG_START_FROM_SRAM__
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_KGDB | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_BEDBUG | \
|
||||
CFG_CMD_ELF )
|
||||
#else
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_KGDB | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_ELF )
|
||||
#endif
|
||||
*/
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_KGDB | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_ELF )
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
/*
|
||||
* If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
|
||||
* If CFG_405_UART_ERRATA_59, then UART divisor is 31.
|
||||
* Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
|
||||
* The Linux BASE_BAUD define should match this configuration.
|
||||
* baseBaud = cpuClock/(uartDivisor*16)
|
||||
* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
|
||||
* set Linux BASE_BAUD to 403200.
|
||||
*/
|
||||
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
|
||||
#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
|
||||
#define CFG_BASE_BAUD 691200
|
||||
|
||||
/* The following table includes the supported baudrates */
|
||||
#define CFG_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
|
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */
|
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
|
||||
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
/* resource configuration */
|
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
|
||||
#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
|
||||
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
|
||||
#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
|
||||
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
|
||||
#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
|
||||
#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
|
||||
#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External peripheral base address
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#undef CONFIG_IDE_LED /* no led for ide supported */
|
||||
#undef CONFIG_IDE_RESET /* no reset for ide supported */
|
||||
|
||||
#define CFG_KEY_REG_BASE_ADDR 0xF0100000
|
||||
#define CFG_IR_REG_BASE_ADDR 0xF0200000
|
||||
#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#ifdef __DEBUG_START_FROM_SRAM__
|
||||
#define CFG_SRAM_BASE 0xFFF80000
|
||||
#define CFG_FLASH_BASE 0xFFF00000
|
||||
#define CFG_MONITOR_BASE CFG_SRAM_BASE
|
||||
#else
|
||||
#define CFG_SRAM_BASE 0xFFF00000
|
||||
#define CFG_FLASH_BASE 0xFFF80000
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE
|
||||
#endif
|
||||
|
||||
|
||||
//#define CFG_MONITOR_LEN (200 * 1024) /* Reserve 200 kB for Monitor */
|
||||
#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 200 kB for Monitor */
|
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
/* BEG ENVIRONNEMENT FLASH */
|
||||
#ifdef CFG_ENV_IS_IN_FLASH
|
||||
#define CFG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */
|
||||
#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
|
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
|
||||
#endif
|
||||
/* END ENVIRONNEMENT FLASH */
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM organization
|
||||
*/
|
||||
#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
|
||||
#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
|
||||
|
||||
#ifdef CFG_ENV_IS_IN_NVRAM
|
||||
#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
|
||||
#define CFG_ENV_ADDR \
|
||||
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
|
||||
#endif
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
|
||||
#define CFG_CACHELINE_SIZE 32 /* ... */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
|
||||
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
|
||||
|
||||
|
||||
/* Configuration Port location */
|
||||
#define CONFIG_PORT_ADDR 0xF0000500
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in data cache)
|
||||
*/
|
||||
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
|
||||
#define CFG_TEMP_STACK_OCM 1
|
||||
|
||||
/* On Chip Memory location */
|
||||
#define CFG_OCM_DATA_ADDR 0xF8000000
|
||||
#define CFG_OCM_DATA_SIZE 0x1000
|
||||
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
|
||||
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup
|
||||
*/
|
||||
|
||||
/* Memory Bank 0 (Flash/SRAM) initialization */
|
||||
#define CFG_EBC_PB0AP 0x04006000
|
||||
#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
|
||||
|
||||
/* Memory Bank 1 (NVRAM/RTC) initialization */
|
||||
#define CFG_EBC_PB1AP 0x04041000
|
||||
#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
|
||||
|
||||
/* Memory Bank 2 (not used) initialization */
|
||||
#define CFG_EBC_PB2AP 0x00000000
|
||||
#define CFG_EBC_PB2CR 0x00000000
|
||||
|
||||
/* Memory Bank 2 (not used) initialization */
|
||||
#define CFG_EBC_PB3AP 0x00000000
|
||||
#define CFG_EBC_PB3CR 0x00000000
|
||||
|
||||
/* Memory Bank 4 (FPGA regs) initialization */
|
||||
#define CFG_EBC_PB4AP 0x01815000
|
||||
#define CFG_EBC_PB4CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for Serial Presence Detect EEPROM address
|
||||
* (to get SDRAM settings)
|
||||
*/
|
||||
#define SPD_EEPROM_ADDRESS 0x55
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for GPIO setup (PPC405EP specific)
|
||||
*
|
||||
* GPIO0[0] - External Bus Controller BLAST output
|
||||
* GPIO0[1-9] - Instruction trace outputs
|
||||
* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
|
||||
* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
|
||||
* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
|
||||
* GPIO0[24-27] - UART0 control signal inputs/outputs
|
||||
* GPIO0[28-29] - UART1 data signal input/output
|
||||
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
|
||||
*/
|
||||
#define CFG_GPIO0_OSRH 0x55555555
|
||||
#define CFG_GPIO0_OSRL 0x40000110
|
||||
#define CFG_GPIO0_ISR1H 0x00000000
|
||||
#define CFG_GPIO0_ISR1L 0x15555445
|
||||
#define CFG_GPIO0_TSRH 0x00000000
|
||||
#define CFG_GPIO0_TSRL 0x00000000
|
||||
#define CFG_GPIO0_TCR 0xFFFF8014
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Some BUBINGA stuff...
|
||||
*/
|
||||
#define NVRAM_BASE 0xF0000000
|
||||
#define FPGA_REG0 0xF0300000 /* FPGA Reg 0 */
|
||||
#define FPGA_REG1 0xF0300001 /* FPGA Reg 1 */
|
||||
#define NVRVFY1 0x4f532d4f /* used to determine if state data in */
|
||||
#define NVRVFY2 0x50454e00 /* NVRAM initialized (ascii for OS-OPEN)*/
|
||||
|
||||
#define FPGA_REG0_F_RANGE 0x80 /* SDRAM PLL freq range */
|
||||
#define FPGA_REG0_EXT_INT_DIS 0x20 /* External interface disable */
|
||||
#define FPGA_REG0_LED_MASK 0x07 /* Board LEDs DS9, DS10, and DS11 */
|
||||
#define FPGA_REG0_LED0 0x04 /* Turn on LED0 */
|
||||
#define FPGA_REG0_LED1 0x02 /* Turn on LED1 */
|
||||
#define FPGA_REG0_LED2 0x01 /* Turn on LED2 */
|
||||
|
||||
#define FPGA_REG1_SSPEC_DIS 0x80 /* C9531 Spread Spectrum disabled */
|
||||
#define FPGA_REG1_OFFBD_PCICLK 0x40 /* Onboard PCI clock selected */
|
||||
#define FPGA_REG1_CLOCK_MASK 0x30 /* Mask for C9531 output freq select */
|
||||
#define FPGA_REG1_CLOCK_BIT_SHIFT 4
|
||||
#define FPGA_REG1_PCI_INT_ARB 0x08 /* PCI Internal arbiter selected */
|
||||
#define FPGA_REG1_PCI_FREQ 0x04 /* PCI Frequency select */
|
||||
#define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */
|
||||
#define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */
|
||||
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue